NVAPI Reference Documentation 545
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nvapi.h
1#include"nvapi_lite_salstart.h"
2#include"nvapi_lite_common.h"
3#include"nvapi_lite_sli.h"
4#include"nvapi_lite_surround.h"
5#include"nvapi_lite_stereo.h"
6#include"nvapi_lite_d3dext.h"
7 /************************************************************************************************************************************\
8|* *|
9|* Copyright © 2012 NVIDIA Corporation. All rights reserved. *|
10|* *|
11|* NOTICE TO USER: *|
12|* *|
13|* This software is subject to NVIDIA ownership rights under U.S. and international Copyright laws. *|
14|* *|
15|* This software and the information contained herein are PROPRIETARY and CONFIDENTIAL to NVIDIA *|
16|* and are being provided solely under the terms and conditions of an NVIDIA software license agreement. *|
17|* Otherwise, you have no rights to use or access this software in any manner. *|
18|* *|
19|* If not covered by the applicable NVIDIA software license agreement: *|
20|* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOFTWARE FOR ANY PURPOSE. *|
21|* IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. *|
22|* NVIDIA DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, *|
23|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE. *|
24|* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, *|
25|* OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, *|
26|* NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27|* *|
28|* U.S. Government End Users. *|
29|* This software is a "commercial item" as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30|* consisting of "commercial computer software" and "commercial computer software documentation" *|
31|* as such terms are used in 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Government only as a commercial end item. *|
32|* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
33|* all U.S. Government End Users acquire the software with only those rights set forth herein. *|
34|* *|
35|* Any use of this software in individual and commercial software must include, *|
36|* in the user documentation and internal comments to the code, *|
37|* the above Disclaimer (as applicable) and U.S. Government End Users Notice. *|
38|* *|
39 \************************************************************************************************************************************/
40
41
43//
44// Date: Oct 20, 2023
45// File: nvapi.h
46//
47// NvAPI provides an interface to NVIDIA devices. This file contains the
48// interface constants, structure definitions and function prototypes.
49//
50// Target Profile: developer
51// Target Platform: windows
52//
54#ifndef _NVAPI_H
55#define _NVAPI_H
56
57#pragma pack(push,8) // Make sure we have consistent structure packings
58
59#ifdef __cplusplus
60extern "C" {
61#endif
62// ====================================================
63// Universal NvAPI Definitions
64// ====================================================
65#ifndef _WIN32
66#define __cdecl
67#endif
68
69
70
72
73
75#define NVAPI_API_NOT_INTIALIZED NVAPI_API_NOT_INITIALIZED
76
78//
79// FUNCTION NAME: NvAPI_Initialize
80//
97NVAPI_INTERFACE NvAPI_Initialize();
98
99
101//
102// FUNCTION NAME: NvAPI_Unload
103//
127NVAPI_INTERFACE NvAPI_Unload();
128
130//
131// FUNCTION NAME: NvAPI_GetErrorMessage
132//
146NVAPI_INTERFACE NvAPI_GetErrorMessage(NvAPI_Status nr,NvAPI_ShortString szDesc);
147
149//
150// FUNCTION NAME: NvAPI_GetInterfaceVersionString
151//
167NVAPI_INTERFACE NvAPI_GetInterfaceVersionString(NvAPI_ShortString szDesc);
168
170//
171// FUNCTION NAME: NvAPI_GetInterfaceVersionStringEx
172//
187NVAPI_INTERFACE NvAPI_GetInterfaceVersionStringEx(NvAPI_ShortString szDesc);
188
189
191// All display port related data types definition starts
193
194// This category is intentionally added before the #ifdef. The #endif should also be in the same scope
195
196#ifndef DISPLAYPORT_STRUCTS_DEFINED
197#define DISPLAYPORT_STRUCTS_DEFINED
198
202{
203 NV_DP_1_62GBPS = 6,
204 NV_DP_2_70GBPS = 0xA,
205 NV_DP_5_40GBPS = 0x14,
206 NV_DP_8_10GBPS = 0x1E,
207// Recommended Intermidiate Link Transfer Rates
208 NV_EDP_2_16GBPS = 8,
209 NV_EDP_2_43GBPS = 9,
210 NV_EDP_3_24GBPS = 0xC,
211 NV_EDP_4_32GBPS = 0x10
213
214
218{
219 NV_DP_1_LANE = 1,
220 NV_DP_2_LANE = 2,
221 NV_DP_4_LANE = 4,
223
224
228{
229 NV_DP_COLOR_FORMAT_RGB = 0,
230 NV_DP_COLOR_FORMAT_YCbCr422,
231 NV_DP_COLOR_FORMAT_YCbCr444,
233
234
238{
239 NV_DP_COLORIMETRY_RGB = 0,
240 NV_DP_COLORIMETRY_YCbCr_ITU601,
241 NV_DP_COLORIMETRY_YCbCr_ITU709,
243
244
248{
249 NV_DP_DYNAMIC_RANGE_VESA = 0,
250 NV_DP_DYNAMIC_RANGE_CEA,
252
253
256typedef enum _NV_DP_BPC
257{
258 NV_DP_BPC_DEFAULT = 0,
259 NV_DP_BPC_6,
260 NV_DP_BPC_8,
261 NV_DP_BPC_10,
262 NV_DP_BPC_12,
263 NV_DP_BPC_16,
265
266
267#endif //#ifndef DISPLAYPORT_STRUCTS_DEFINED
268
270// All display port related data types definitions end
272
274//
275// FUNCTION NAME: NvAPI_GPU_GetEDID
276//
291//
293
296
297#define NV_EDID_V1_DATA_SIZE 256
298
299#define NV_EDID_DATA_SIZE NV_EDID_V1_DATA_SIZE
300
301typedef struct
302{
303 NvU32 version; //structure version
304 NvU8 EDID_Data[NV_EDID_DATA_SIZE];
305} NV_EDID_V1;
306
308typedef struct
309{
310 NvU32 version;
311 NvU8 EDID_Data[NV_EDID_DATA_SIZE];
312 NvU32 sizeofEDID;
313} NV_EDID_V2;
314
316typedef struct
317{
318 NvU32 version;
319 NvU8 EDID_Data[NV_EDID_DATA_SIZE];
320 NvU32 sizeofEDID;
321 NvU32 edidId;
324 NvU32 offset;
327} NV_EDID_V3;
328
329typedef NV_EDID_V3 NV_EDID;
330
331#define NV_EDID_VER1 MAKE_NVAPI_VERSION(NV_EDID_V1,1)
332#define NV_EDID_VER2 MAKE_NVAPI_VERSION(NV_EDID_V2,2)
333#define NV_EDID_VER3 MAKE_NVAPI_VERSION(NV_EDID_V3,3)
334#define NV_EDID_VER NV_EDID_VER3
335
337
339NVAPI_INTERFACE NvAPI_GPU_GetEDID(NvPhysicalGpuHandle hPhysicalGpu, NvU32 displayOutputId, NV_EDID *pEDID);
340
342
344
345#define NV_EDID_DATA_SIZE_MAX 1024
346
347typedef enum
348{
350 NV_EDID_FLAG_RAW = 1,
356} NV_EDID_FLAG;
357
361{
362 NVAPI_GPU_CONNECTOR_VGA_15_PIN = 0x00000000,
363 NVAPI_GPU_CONNECTOR_TV_COMPOSITE = 0x00000010,
364 NVAPI_GPU_CONNECTOR_TV_SVIDEO = 0x00000011,
365 NVAPI_GPU_CONNECTOR_TV_HDTV_COMPONENT = 0x00000013,
366 NVAPI_GPU_CONNECTOR_TV_SCART = 0x00000014,
367 NVAPI_GPU_CONNECTOR_TV_COMPOSITE_SCART_ON_EIAJ4120 = 0x00000016,
368 NVAPI_GPU_CONNECTOR_TV_HDTV_EIAJ4120 = 0x00000017,
369 NVAPI_GPU_CONNECTOR_PC_POD_HDTV_YPRPB = 0x00000018,
370 NVAPI_GPU_CONNECTOR_PC_POD_SVIDEO = 0x00000019,
371 NVAPI_GPU_CONNECTOR_PC_POD_COMPOSITE = 0x0000001A,
372 NVAPI_GPU_CONNECTOR_DVI_I_TV_SVIDEO = 0x00000020,
373 NVAPI_GPU_CONNECTOR_DVI_I_TV_COMPOSITE = 0x00000021,
374 NVAPI_GPU_CONNECTOR_DVI_I = 0x00000030,
375 NVAPI_GPU_CONNECTOR_DVI_D = 0x00000031,
376 NVAPI_GPU_CONNECTOR_ADC = 0x00000032,
377 NVAPI_GPU_CONNECTOR_LFH_DVI_I_1 = 0x00000038,
378 NVAPI_GPU_CONNECTOR_LFH_DVI_I_2 = 0x00000039,
379 NVAPI_GPU_CONNECTOR_SPWG = 0x00000040,
380 NVAPI_GPU_CONNECTOR_OEM = 0x00000041,
381 NVAPI_GPU_CONNECTOR_DISPLAYPORT_EXTERNAL = 0x00000046,
382 NVAPI_GPU_CONNECTOR_DISPLAYPORT_INTERNAL = 0x00000047,
383 NVAPI_GPU_CONNECTOR_DISPLAYPORT_MINI_EXT = 0x00000048,
384 NVAPI_GPU_CONNECTOR_HDMI_A = 0x00000061,
385 NVAPI_GPU_CONNECTOR_HDMI_C_MINI = 0x00000063,
386 NVAPI_GPU_CONNECTOR_LFH_DISPLAYPORT_1 = 0x00000064,
387 NVAPI_GPU_CONNECTOR_LFH_DISPLAYPORT_2 = 0x00000065,
389 NVAPI_GPU_CONNECTOR_USB_C = 0x00000071,
390 NVAPI_GPU_CONNECTOR_UNKNOWN = 0xFFFFFFFF,
392
394//
395// NvAPI_TVOutput Information
396//
398
401typedef enum _NV_DISPLAY_TV_FORMAT
402{
403 NV_DISPLAY_TV_FORMAT_NONE = 0,
404 NV_DISPLAY_TV_FORMAT_SD_NTSCM = 0x00000001,
405 NV_DISPLAY_TV_FORMAT_SD_NTSCJ = 0x00000002,
406 NV_DISPLAY_TV_FORMAT_SD_PALM = 0x00000004,
407 NV_DISPLAY_TV_FORMAT_SD_PALBDGH = 0x00000008,
408 NV_DISPLAY_TV_FORMAT_SD_PALN = 0x00000010,
409 NV_DISPLAY_TV_FORMAT_SD_PALNC = 0x00000020,
410 NV_DISPLAY_TV_FORMAT_SD_576i = 0x00000100,
411 NV_DISPLAY_TV_FORMAT_SD_480i = 0x00000200,
412 NV_DISPLAY_TV_FORMAT_ED_480p = 0x00000400,
413 NV_DISPLAY_TV_FORMAT_ED_576p = 0x00000800,
414 NV_DISPLAY_TV_FORMAT_HD_720p = 0x00001000,
415 NV_DISPLAY_TV_FORMAT_HD_1080i = 0x00002000,
416 NV_DISPLAY_TV_FORMAT_HD_1080p = 0x00004000,
417 NV_DISPLAY_TV_FORMAT_HD_720p50 = 0x00008000,
418 NV_DISPLAY_TV_FORMAT_HD_1080p24 = 0x00010000,
419 NV_DISPLAY_TV_FORMAT_HD_1080i50 = 0x00020000,
420 NV_DISPLAY_TV_FORMAT_HD_1080p50 = 0x00040000,
421 NV_DISPLAY_TV_FORMAT_UHD_4Kp30 = 0x00080000,
422 NV_DISPLAY_TV_FORMAT_UHD_4Kp30_3840 = NV_DISPLAY_TV_FORMAT_UHD_4Kp30,
423 NV_DISPLAY_TV_FORMAT_UHD_4Kp25 = 0x00100000,
424 NV_DISPLAY_TV_FORMAT_UHD_4Kp25_3840 = NV_DISPLAY_TV_FORMAT_UHD_4Kp25,
425 NV_DISPLAY_TV_FORMAT_UHD_4Kp24 = 0x00200000,
426 NV_DISPLAY_TV_FORMAT_UHD_4Kp24_3840 = NV_DISPLAY_TV_FORMAT_UHD_4Kp24,
427 NV_DISPLAY_TV_FORMAT_UHD_4Kp24_SMPTE = 0x00400000,
428 NV_DISPLAY_TV_FORMAT_UHD_4Kp50_3840 = 0x00800000,
429 NV_DISPLAY_TV_FORMAT_UHD_4Kp60_3840 = 0x00900000,
430 NV_DISPLAY_TV_FORMAT_UHD_4Kp30_4096 = 0x00A00000,
431 NV_DISPLAY_TV_FORMAT_UHD_4Kp25_4096 = 0x00B00000,
432 NV_DISPLAY_TV_FORMAT_UHD_4Kp24_4096 = 0x00C00000,
433 NV_DISPLAY_TV_FORMAT_UHD_4Kp50_4096 = 0x00D00000,
434 NV_DISPLAY_TV_FORMAT_UHD_4Kp60_4096 = 0x00E00000,
435 NV_DISPLAY_TV_FORMAT_UHD_8Kp24_7680 = 0x01000000,
436 NV_DISPLAY_TV_FORMAT_UHD_8Kp25_7680 = 0x02000000,
437 NV_DISPLAY_TV_FORMAT_UHD_8Kp30_7680 = 0x04000000,
438 NV_DISPLAY_TV_FORMAT_UHD_8Kp48_7680 = 0x08000000,
439 NV_DISPLAY_TV_FORMAT_UHD_8Kp50_7680 = 0x09000000,
440 NV_DISPLAY_TV_FORMAT_UHD_8Kp60_7680 = 0x0A000000,
441 NV_DISPLAY_TV_FORMAT_UHD_8Kp100_7680 = 0x0B000000,
442 NV_DISPLAY_TV_FORMAT_UHD_8Kp120_7680 = 0x0C000000,
443 NV_DISPLAY_TV_FORMAT_UHD_4Kp48_3840 = 0x0D000000,
444 NV_DISPLAY_TV_FORMAT_UHD_4Kp48_4096 = 0x0E000000,
445 NV_DISPLAY_TV_FORMAT_UHD_4Kp100_4096 = 0x0F000000,
446 NV_DISPLAY_TV_FORMAT_UHD_4Kp100_3840 = 0x10000000,
447 NV_DISPLAY_TV_FORMAT_UHD_4Kp120_4096 = 0x11000000,
448 NV_DISPLAY_TV_FORMAT_UHD_4Kp120_3840 = 0x12000000,
449 NV_DISPLAY_TV_FORMAT_UHD_4Kp100_5120 = 0x13000000,
450 NV_DISPLAY_TV_FORMAT_UHD_4Kp120_5120 = 0x14000000,
451 NV_DISPLAY_TV_FORMAT_UHD_4Kp24_5120 = 0x15000000,
452 NV_DISPLAY_TV_FORMAT_UHD_4Kp25_5120 = 0x16000000,
453 NV_DISPLAY_TV_FORMAT_UHD_4Kp30_5120 = 0x17000000,
454 NV_DISPLAY_TV_FORMAT_UHD_4Kp48_5120 = 0x18000000,
455 NV_DISPLAY_TV_FORMAT_UHD_4Kp50_5120 = 0x19000000,
456 NV_DISPLAY_TV_FORMAT_UHD_4Kp60_5120 = 0x20000000,
457 NV_DISPLAY_TV_FORMAT_UHD_10Kp24_10240 = 0x21000000,
458 NV_DISPLAY_TV_FORMAT_UHD_10Kp25_10240 = 0x22000000,
459 NV_DISPLAY_TV_FORMAT_UHD_10Kp30_10240 = 0x23000000,
460 NV_DISPLAY_TV_FORMAT_UHD_10Kp48_10240 = 0x24000000,
461 NV_DISPLAY_TV_FORMAT_UHD_10Kp50_10240 = 0x25000000,
462 NV_DISPLAY_TV_FORMAT_UHD_10Kp60_10240 = 0x26000000,
463 NV_DISPLAY_TV_FORMAT_UHD_10Kp100_10240 = 0x27000000,
464 NV_DISPLAY_TV_FORMAT_UHD_10Kp120_10240 = 0x28000000,
465
466
467 NV_DISPLAY_TV_FORMAT_SD_OTHER = 0x30000000,
468 NV_DISPLAY_TV_FORMAT_ED_OTHER = 0x40000000,
469 NV_DISPLAY_TV_FORMAT_HD_OTHER = 0x50000000,
470
471 NV_DISPLAY_TV_FORMAT_ANY = 0x80000000,
472
473} NV_DISPLAY_TV_FORMAT;
474
475
478#define NVAPI_MAX_VIEW_TARGET 2
479#define NVAPI_ADVANCED_MAX_VIEW_TARGET 4
480
481#ifndef _NV_TARGET_VIEW_MODE_
482#define _NV_TARGET_VIEW_MODE_
483
486{
487 NV_VIEW_MODE_STANDARD = 0,
488 NV_VIEW_MODE_CLONE = 1,
489 NV_VIEW_MODE_HSPAN = 2,
490 NV_VIEW_MODE_VSPAN = 3,
491 NV_VIEW_MODE_DUALVIEW = 4,
492 NV_VIEW_MODE_MULTIVIEW = 5,
494#endif
495
497
498// Following definitions are used in NvAPI_SetViewEx.
499
523
525
527typedef enum _NV_ROTATE
528{
529 NV_ROTATE_0 = 0,
530 NV_ROTATE_90 = 1,
531 NV_ROTATE_180 = 2,
532 NV_ROTATE_270 = 3,
533 NV_ROTATE_IGNORED = 4,
535
538#define NVFORMAT_MAKEFOURCC(ch0, ch1, ch2, ch3) \
539 ((NvU32)(NvU8)(ch0) | ((NvU32)(NvU8)(ch1) << 8) | \
540 ((NvU32)(NvU8)(ch2) << 16) | ((NvU32)(NvU8)(ch3) << 24 ))
541
542
543
555
556// TV standard
557
558typedef struct
559{
560 float x;
561 float y;
562 float w;
563 float h;
565
566
567
570
571
592
593
594#ifndef NV_TIMING_STRUCTS_DEFINED
595#define NV_TIMING_STRUCTS_DEFINED
596
597//***********************
598// The Timing Structure
599//***********************
600//
604typedef struct tagNV_TIMINGEXT
605{
606 NvU32 flag;
607 NvU16 rr;
608 NvU32 rrx1k;
609 NvU32 aspect;
610 NvU16 rep;
611 NvU32 status;
612 NvU8 name[40];
614
615
616
644typedef struct _NV_TIMING
645{
646 // VESA scan out timing parameters:
647 NvU16 HVisible;
648 NvU16 HBorder;
651 NvU16 HTotal;
652 NvU8 HSyncPol;
653
654 NvU16 VVisible;
655 NvU16 VBorder;
658 NvU16 VTotal;
659 NvU8 VSyncPol;
660
662 NvU32 pclk;
663
664 //other timing related extras
665 NV_TIMINGEXT etc;
667#endif //NV_TIMING_STRUCTS_DEFINED
668
669
673#define NV_TIMING_H_SYNC_POSITIVE 0
674#define NV_TIMING_H_SYNC_NEGATIVE 1
675#define NV_TIMING_H_SYNC_DEFAULT NV_TIMING_H_SYNC_NEGATIVE
676//
677#define NV_TIMING_V_SYNC_POSITIVE 0
678#define NV_TIMING_V_SYNC_NEGATIVE 1
679#define NV_TIMING_V_SYNC_DEFAULT NV_TIMING_V_SYNC_POSITIVE
680//
681#define NV_TIMING_PROGRESSIVE 0
682#define NV_TIMING_INTERLACED 1
683#define NV_TIMING_INTERLACED_EXTRA_VBLANK_ON_FIELD2 1
684#define NV_TIMING_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2 2
686
688//
689// FUNCTION NAME: NvAPI_SetView
690//
713//
715
718typedef struct
719{
720 NvU32 version;
721 NvU32 count;
722 struct
723 {
725 NvU32 sourceId;
726 NvU32 bPrimary:1;
728 NvU32 bInterlaced:1;
729 NvU32 bGDIPrimary:1;
731 } target[NVAPI_MAX_VIEW_TARGET];
733
735#define NV_VIEW_TARGET_INFO_VER MAKE_NVAPI_VERSION(NV_VIEW_TARGET_INFO,2)
736
738__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_DISP_SetDisplayConfig.")
739NVAPI_INTERFACE NvAPI_SetView(NvDisplayHandle hNvDisplay, NV_VIEW_TARGET_INFO *pTargetInfo, NV_TARGET_VIEW_MODE targetView);
740
741
743//
744// FUNCTION NAME: NvAPI_SetViewEx
745//
769//
771
773#define NVAPI_MAX_DISPLAY_PATH NVAPI_MAX_VIEW_TARGET
774
776#define NVAPI_ADVANCED_MAX_DISPLAY_PATH NVAPI_ADVANCED_MAX_VIEW_TARGET
777
778
779
782typedef struct
783{
785 NvU32 sourceId;
786 NvU32 bPrimary:1;
789
790 // source mode information
791 NvU32 width;
792 NvU32 height;
793 NvU32 depth;
795
796 //rotation setting of the mode
798
799 // the scaling mode
801
802 // Timing info
804 NvU32 interlaced:1;
805
806 NV_DISPLAY_TV_FORMAT tvFormat;
807
808 // Windows desktop position
809 NvU32 posx;
810 NvU32 posy;
811 NvU32 bGDIPrimary:1;
812
815 NvU32 gpuId:24;
816
818
821typedef struct
822{
823 NvU32 version;
824 NvU32 count;
825 NV_DISPLAY_PATH path[NVAPI_MAX_DISPLAY_PATH];
827
830typedef struct
831{
832 NvU32 version;
833 NvU32 count;
834 NV_DISPLAY_PATH path[NVAPI_ADVANCED_MAX_DISPLAY_PATH];
836
840#define NV_DISPLAY_PATH_INFO_VER NV_DISPLAY_PATH_INFO_VER4
841#define NV_DISPLAY_PATH_INFO_VER4 MAKE_NVAPI_VERSION(NV_DISPLAY_PATH_INFO,4)
842#define NV_DISPLAY_PATH_INFO_VER3 MAKE_NVAPI_VERSION(NV_DISPLAY_PATH_INFO,3)
843#define NV_DISPLAY_PATH_INFO_VER2 MAKE_NVAPI_VERSION(NV_DISPLAY_PATH_INFO,2)
844#define NV_DISPLAY_PATH_INFO_VER1 MAKE_NVAPI_VERSION(NV_DISPLAY_PATH_INFO,1)
847//
848// FUNCTION NAME: NvAPI_SetViewEx
849//
873//
875
877__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_DISP_SetDisplayConfig.")
878NVAPI_INTERFACE NvAPI_SetViewEx(NvDisplayHandle hNvDisplay, NV_DISPLAY_PATH_INFO *pPathInfo, NV_TARGET_VIEW_MODE displayView);
879
880
881
883// SetDisplayConfig/GetDisplayConfig
886
887typedef struct _NV_POSITION
888{
889 NvS32 x;
890 NvS32 y;
892
894typedef struct _NV_RESOLUTION
895{
896 NvU32 width;
897 NvU32 height;
898 NvU32 colorDepth;
900
903{
904 NvU32 version;
905
906 // Rotation and Scaling
909
910 // Refresh Rate
913 // Flags
914 NvU32 interlaced:1;
915 NvU32 primary:1;
918#ifdef NV_PAN_AND_SCAN_DEFINED
919 NvU32 isPanAndScanTarget:1;
921#else
922 NvU32 reservedBit1:1;
923#endif
924 NvU32 disableVirtualModeSupport:1;
925 NvU32 isPreferredUnscaledTarget:1;
926 NvU32 reserved:27;
927 // TV format information
929 NV_DISPLAY_TV_FORMAT tvFormat;
934
935 // Backend (raster) timing standard
941
944
946#define NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO_VER1 MAKE_NVAPI_VERSION(NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO_V1,1)
947
949#define NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO_VER NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO_VER1
950
957
965
966
970
971
973typedef enum _NV_DISPLAYCONFIG_SPANNING_ORIENTATION
974{
975 NV_DISPLAYCONFIG_SPAN_NONE = 0,
976 NV_DISPLAYCONFIG_SPAN_HORIZONTAL = 1,
977 NV_DISPLAYCONFIG_SPAN_VERTICAL = 2,
978} NV_DISPLAYCONFIG_SPANNING_ORIENTATION;
979
982{
983 NV_RESOLUTION resolution;
988 NV_DISPLAYCONFIG_SPANNING_ORIENTATION spanningOrientation;
989 NvU32 bGDIPrimary : 1;
990 NvU32 bSLIFocus : 1;
991 NvU32 reserved : 30;
993
994
995
1007
1010#define _NV_DISPLAYCONFIG_PATH_INFO_V2 _NV_DISPLAYCONFIG_PATH_INFO
1011
1029
1031#define NV_DISPLAYCONFIG_PATH_INFO_VER1 MAKE_NVAPI_VERSION(NV_DISPLAYCONFIG_PATH_INFO_V1,1)
1032
1034#define NV_DISPLAYCONFIG_PATH_INFO_VER2 MAKE_NVAPI_VERSION(NV_DISPLAYCONFIG_PATH_INFO_V2,2)
1035
1036#ifndef NV_DISPLAYCONFIG_PATH_INFO_VER
1037
1039
1040#define NV_DISPLAYCONFIG_PATH_INFO_VER NV_DISPLAYCONFIG_PATH_INFO_VER2
1041
1043
1044#endif
1045
1046
1049{
1050 NV_DISPLAYCONFIG_VALIDATE_ONLY = 0x00000001,
1051 NV_DISPLAYCONFIG_SAVE_TO_PERSISTENCE = 0x00000002,
1055} NV_DISPLAYCONFIG_FLAGS;
1056
1057
1058#define NVAPI_UNICODE_STRING_MAX 2048
1059#define NVAPI_BINARY_DATA_MAX 4096
1060
1061typedef NvU16 NvAPI_UnicodeString[NVAPI_UNICODE_STRING_MAX];
1062typedef const NvU16 *NvAPI_LPCWSTR;
1063
1064// Common
1065
1066
1067
1070#define NVAPI_MAX_GPU_CLOCKS 32
1071#define NVAPI_MAX_GPU_PUBLIC_CLOCKS 32
1072#define NVAPI_MAX_GPU_PERF_CLOCKS 32
1073#define NVAPI_MAX_GPU_PERF_VOLTAGES 16
1074#define NVAPI_MAX_GPU_PERF_PSTATES 16
1076
1078typedef enum _NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID
1079{
1080 NVAPI_GPU_PERF_VOLTAGE_INFO_DOMAIN_CORE = 0,
1081 NVAPI_GPU_PERF_VOLTAGE_INFO_DOMAIN_UNDEFINED = NVAPI_MAX_GPU_PERF_VOLTAGES,
1082} NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID;
1083
1085typedef enum _NV_GPU_PUBLIC_CLOCK_ID
1086{
1087 NVAPI_GPU_PUBLIC_CLOCK_GRAPHICS = 0,
1088 NVAPI_GPU_PUBLIC_CLOCK_MEMORY = 4,
1089 NVAPI_GPU_PUBLIC_CLOCK_PROCESSOR = 7,
1090 NVAPI_GPU_PUBLIC_CLOCK_VIDEO = 8,
1091 NVAPI_GPU_PUBLIC_CLOCK_UNDEFINED = NVAPI_MAX_GPU_PUBLIC_CLOCKS,
1092} NV_GPU_PUBLIC_CLOCK_ID;
1093
1094
1097
1098typedef enum _NV_GPU_PERF_PSTATE_ID
1099{
1100 NVAPI_GPU_PERF_PSTATE_P0 = 0,
1101 NVAPI_GPU_PERF_PSTATE_P1,
1102 NVAPI_GPU_PERF_PSTATE_P2,
1103 NVAPI_GPU_PERF_PSTATE_P3,
1104 NVAPI_GPU_PERF_PSTATE_P4,
1105 NVAPI_GPU_PERF_PSTATE_P5,
1106 NVAPI_GPU_PERF_PSTATE_P6,
1107 NVAPI_GPU_PERF_PSTATE_P7,
1108 NVAPI_GPU_PERF_PSTATE_P8,
1109 NVAPI_GPU_PERF_PSTATE_P9,
1110 NVAPI_GPU_PERF_PSTATE_P10,
1111 NVAPI_GPU_PERF_PSTATE_P11,
1112 NVAPI_GPU_PERF_PSTATE_P12,
1113 NVAPI_GPU_PERF_PSTATE_P13,
1114 NVAPI_GPU_PERF_PSTATE_P14,
1115 NVAPI_GPU_PERF_PSTATE_P15,
1116 NVAPI_GPU_PERF_PSTATE_UNDEFINED = NVAPI_MAX_GPU_PERF_PSTATES,
1117 NVAPI_GPU_PERF_PSTATE_ALL,
1118
1119} NV_GPU_PERF_PSTATE_ID;
1120
1122
1123
1124
1127
1128#define NVAPI_MAX_GPU_PSTATE20_PSTATES 16
1129#define NVAPI_MAX_GPU_PSTATE20_CLOCKS 8
1130#define NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES 4
1131
1141
1143typedef struct
1144{
1146 NvS32 value;
1147
1148 struct
1149 {
1151 NvS32 min;
1152
1154 NvS32 max;
1155 } valueRange;
1157
1159typedef struct
1160{
1162 NV_GPU_PUBLIC_CLOCK_ID domainId;
1163
1166 NvU32 bIsEditable:1;
1167
1169 NvU32 reserved:31;
1170
1173
1175 union
1176 {
1177 struct
1178 {
1181 } single;
1182
1183 struct
1184 {
1187
1190
1192 NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId;
1193 NvU32 minVoltage_uV;
1194 NvU32 maxVoltage_uV;
1195 } range;
1196 } data;
1198
1200typedef struct
1201{
1203 NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId;
1204 NvU32 bIsEditable:1;
1205
1207 NvU32 reserved:31;
1208
1210 NvU32 volt_uV;
1211
1212 NV_GPU_PERF_PSTATES20_PARAM_DELTA voltDelta_uV; // Current base voltage delta from nominal settings in [uV]
1214
1216
1217typedef struct
1218{
1220 NvU32 version;
1221
1222 NvU32 bIsEditable:1;
1223
1225 NvU32 reserved:31;
1226
1229
1232
1235
1238 struct
1239 {
1241 NV_GPU_PERF_PSTATE_ID pstateId;
1242
1243 NvU32 bIsEditable:1;
1244
1246 NvU32 reserved:31;
1247
1250 NV_GPU_PSTATE20_CLOCK_ENTRY_V1 clocks[NVAPI_MAX_GPU_PSTATE20_CLOCKS];
1251
1254 NV_GPU_PSTATE20_BASE_VOLTAGE_ENTRY_V1 baseVoltages[NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES];
1255 } pstates[NVAPI_MAX_GPU_PSTATE20_PSTATES];
1257
1259
1261{
1263 NvU32 version;
1264
1265 NvU32 bIsEditable:1;
1266
1268 NvU32 reserved:31;
1269
1272
1275
1278
1281 struct
1282 {
1284 NV_GPU_PERF_PSTATE_ID pstateId;
1285
1286 NvU32 bIsEditable:1;
1287
1289 NvU32 reserved:31;
1290
1293 NV_GPU_PSTATE20_CLOCK_ENTRY_V1 clocks[NVAPI_MAX_GPU_PSTATE20_CLOCKS];
1294
1297 NV_GPU_PSTATE20_BASE_VOLTAGE_ENTRY_V1 baseVoltages[NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES];
1298 } pstates[NVAPI_MAX_GPU_PSTATE20_PSTATES];
1299
1302 struct
1303 {
1306
1309 NV_GPU_PSTATE20_BASE_VOLTAGE_ENTRY_V1 voltages[NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES];
1312
1314
1316#define NV_GPU_PERF_PSTATES20_INFO_VER1 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES20_INFO_V1,1)
1317
1319#define NV_GPU_PERF_PSTATES20_INFO_VER2 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES20_INFO_V2,2)
1320
1322#define NV_GPU_PERF_PSTATES20_INFO_VER3 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES20_INFO_V2,3)
1323
1325#define NV_GPU_PERF_PSTATES20_INFO_VER NV_GPU_PERF_PSTATES20_INFO_VER3
1326
1328
1330//
1331// FUNCTION NAME: NvAPI_GetDisplayDriverVersion
1348
1351typedef struct
1352{
1353 NvU32 version; // Structure version
1354 NvU32 drvVersion;
1355 NvU32 bldChangeListNum;
1356 NvAPI_ShortString szBuildBranchString;
1357 NvAPI_ShortString szAdapterString;
1359
1361#define NV_DISPLAY_DRIVER_VERSION_VER MAKE_NVAPI_VERSION(NV_DISPLAY_DRIVER_VERSION,1)
1362
1363
1365__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_SYS_GetDriverAndBranchVersion.")
1366NVAPI_INTERFACE NvAPI_GetDisplayDriverVersion(NvDisplayHandle hNvDisplay, NV_DISPLAY_DRIVER_VERSION *pVersion);
1367
1368
1369
1370
1372//
1373// FUNCTION NAME: NvAPI_OGL_ExpertModeSet[Get]
1374//
1376
1377
1425//
1427
1430#define NVAPI_OGLEXPERT_DETAIL_NONE 0x00000000
1431#define NVAPI_OGLEXPERT_DETAIL_ERROR 0x00000001
1432#define NVAPI_OGLEXPERT_DETAIL_SWFALLBACK 0x00000002
1433#define NVAPI_OGLEXPERT_DETAIL_BASIC_INFO 0x00000004
1434#define NVAPI_OGLEXPERT_DETAIL_DETAILED_INFO 0x00000008
1435#define NVAPI_OGLEXPERT_DETAIL_PERFORMANCE_WARNING 0x00000010
1436#define NVAPI_OGLEXPERT_DETAIL_QUALITY_WARNING 0x00000020
1437#define NVAPI_OGLEXPERT_DETAIL_USAGE_WARNING 0x00000040
1438#define NVAPI_OGLEXPERT_DETAIL_ALL 0xFFFFFFFF
1439
1440#define NVAPI_OGLEXPERT_REPORT_NONE 0x00000000
1441#define NVAPI_OGLEXPERT_REPORT_ERROR 0x00000001
1442#define NVAPI_OGLEXPERT_REPORT_SWFALLBACK 0x00000002
1443#define NVAPI_OGLEXPERT_REPORT_PIPELINE_VERTEX 0x00000004
1444#define NVAPI_OGLEXPERT_REPORT_PIPELINE_GEOMETRY 0x00000008
1445#define NVAPI_OGLEXPERT_REPORT_PIPELINE_XFB 0x00000010
1446#define NVAPI_OGLEXPERT_REPORT_PIPELINE_RASTER 0x00000020
1447#define NVAPI_OGLEXPERT_REPORT_PIPELINE_FRAGMENT 0x00000040
1448#define NVAPI_OGLEXPERT_REPORT_PIPELINE_ROP 0x00000080
1449#define NVAPI_OGLEXPERT_REPORT_PIPELINE_FRAMEBUFFER 0x00000100
1450#define NVAPI_OGLEXPERT_REPORT_PIPELINE_PIXEL 0x00000200
1451#define NVAPI_OGLEXPERT_REPORT_PIPELINE_TEXTURE 0x00000400
1452#define NVAPI_OGLEXPERT_REPORT_OBJECT_BUFFEROBJECT 0x00000800
1453#define NVAPI_OGLEXPERT_REPORT_OBJECT_TEXTURE 0x00001000
1454#define NVAPI_OGLEXPERT_REPORT_OBJECT_PROGRAM 0x00002000
1455#define NVAPI_OGLEXPERT_REPORT_OBJECT_FBO 0x00004000
1456#define NVAPI_OGLEXPERT_REPORT_FEATURE_SLI 0x00008000
1457#define NVAPI_OGLEXPERT_REPORT_ALL 0xFFFFFFFF
1458
1459
1460#define NVAPI_OGLEXPERT_OUTPUT_TO_NONE 0x00000000
1461#define NVAPI_OGLEXPERT_OUTPUT_TO_CONSOLE 0x00000001
1462#define NVAPI_OGLEXPERT_OUTPUT_TO_DEBUGGER 0x00000004
1463#define NVAPI_OGLEXPERT_OUTPUT_TO_CALLBACK 0x00000008
1464#define NVAPI_OGLEXPERT_OUTPUT_TO_ALL 0xFFFFFFFF
1465
1467
1469//
1470// FUNCTION TYPE: NVAPI_OGLEXPERT_CALLBACK
1471//
1488typedef void (* NVAPI_OGLEXPERT_CALLBACK) (unsigned int categoryId, unsigned int messageId, unsigned int detailLevel, int objectId, const char *messageStr);
1489
1490
1491
1495NVAPI_INTERFACE NvAPI_OGL_ExpertModeSet(NvU32 expertDetailLevel,
1496 NvU32 expertReportMask,
1497 NvU32 expertOutputMask,
1498 NVAPI_OGLEXPERT_CALLBACK expertCallback);
1499
1503NVAPI_INTERFACE NvAPI_OGL_ExpertModeGet(NvU32 *pExpertDetailLevel,
1504 NvU32 *pExpertReportMask,
1505 NvU32 *pExpertOutputMask,
1506 NVAPI_OGLEXPERT_CALLBACK *pExpertCallback);
1507
1509
1510//
1513
1514
1539//
1541
1545NVAPI_INTERFACE NvAPI_OGL_ExpertModeDefaultsSet(NvU32 expertDetailLevel,
1546 NvU32 expertReportMask,
1547 NvU32 expertOutputMask);
1548
1552NVAPI_INTERFACE NvAPI_OGL_ExpertModeDefaultsGet(NvU32 *pExpertDetailLevel,
1553 NvU32 *pExpertReportMask,
1554 NvU32 *pExpertOutputMask);
1556
1557
1558
1559
1561//
1562// FUNCTION NAME: NvAPI_EnumTCCPhysicalGPUs
1563//
1587NVAPI_INTERFACE NvAPI_EnumTCCPhysicalGPUs( NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
1588
1590//
1591// FUNCTION NAME: NvAPI_EnumLogicalGPUs
1592//
1618NVAPI_INTERFACE NvAPI_EnumLogicalGPUs(NvLogicalGpuHandle nvGPUHandle[NVAPI_MAX_LOGICAL_GPUS], NvU32 *pGpuCount);
1619
1621//
1622// FUNCTION NAME: NvAPI_GetPhysicalGPUsFromDisplay
1623//
1644NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromDisplay(NvDisplayHandle hNvDisp, NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
1645
1646
1648//
1649// FUNCTION NAME: NvAPI_GetPhysicalGPUFromUnAttachedDisplay
1650//
1666NVAPI_INTERFACE NvAPI_GetPhysicalGPUFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvPhysicalGpuHandle *pPhysicalGpu);
1667
1668
1669
1671//
1672// FUNCTION NAME: NvAPI_GetLogicalGPUFromDisplay
1673//
1688NVAPI_INTERFACE NvAPI_GetLogicalGPUFromDisplay(NvDisplayHandle hNvDisp, NvLogicalGpuHandle *pLogicalGPU);
1689
1690
1692//
1693// FUNCTION NAME: NvAPI_GetLogicalGPUFromPhysicalGPU
1694//
1708NVAPI_INTERFACE NvAPI_GetLogicalGPUFromPhysicalGPU(NvPhysicalGpuHandle hPhysicalGPU, NvLogicalGpuHandle *pLogicalGPU);
1709
1711//
1712// FUNCTION NAME: NvAPI_GetPhysicalGPUsFromLogicalGPU
1713//
1731NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromLogicalGPU(NvLogicalGpuHandle hLogicalGPU,NvPhysicalGpuHandle hPhysicalGPU[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
1732
1734//
1735// FUNCTION NAME: NvAPI_GetPhysicalGPUFromGPUID
1736//
1751NVAPI_INTERFACE NvAPI_GetPhysicalGPUFromGPUID(NvU32 gpuId, NvPhysicalGpuHandle *pPhysicalGPU);
1752
1754//
1755// FUNCTION NAME: NvAPI_GetGPUIDfromPhysicalGPU
1756//
1758//
1771NVAPI_INTERFACE NvAPI_GetGPUIDfromPhysicalGPU(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pGpuId);
1772
1774//
1775// FUNCTION NAME: NvAPI_GPU_GetShaderSubPipeCount
1776//
1794NVAPI_INTERFACE NvAPI_GPU_GetShaderSubPipeCount(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pCount);
1795
1796
1798//
1799// FUNCTION NAME: NvAPI_GPU_GetGpuCoreCount
1800//
1817NVAPI_INTERFACE NvAPI_GPU_GetGpuCoreCount(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pCount);
1818
1819
1821//
1822// FUNCTION NAME: NvAPI_GPU_GetAllOutputs
1823//
1838__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_GPU_GetAllDisplayIds.")
1839NVAPI_INTERFACE NvAPI_GPU_GetAllOutputs(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pOutputsMask);
1840
1841
1842
1844//
1845// FUNCTION NAME: NvAPI_GPU_GetConnectedOutputs
1846//
1862__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_GPU_GetConnectedDisplayIds.")
1863NVAPI_INTERFACE NvAPI_GPU_GetConnectedOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
1864
1865
1867//
1868// FUNCTION NAME: NvAPI_GPU_GetConnectedSLIOutputs
1869//
1889__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_GPU_GetConnectedDisplayIds.")
1890NVAPI_INTERFACE NvAPI_GPU_GetConnectedSLIOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
1891
1892
1893
1894
1896typedef enum
1897{
1898 NV_MONITOR_CONN_TYPE_UNINITIALIZED = 0,
1899 NV_MONITOR_CONN_TYPE_VGA,
1900 NV_MONITOR_CONN_TYPE_COMPONENT,
1901 NV_MONITOR_CONN_TYPE_SVIDEO,
1902 NV_MONITOR_CONN_TYPE_HDMI,
1903 NV_MONITOR_CONN_TYPE_DVI,
1904 NV_MONITOR_CONN_TYPE_LVDS,
1905 NV_MONITOR_CONN_TYPE_DP,
1906 NV_MONITOR_CONN_TYPE_COMPOSITE,
1907 NV_MONITOR_CONN_TYPE_UNKNOWN = -1
1908} NV_MONITOR_CONN_TYPE;
1909
1910
1913#define NV_GPU_CONNECTED_IDS_FLAG_UNCACHED NV_BIT(0)
1914#define NV_GPU_CONNECTED_IDS_FLAG_SLI NV_BIT(1)
1915#define NV_GPU_CONNECTED_IDS_FLAG_LIDSTATE NV_BIT(2)
1916#define NV_GPU_CONNECTED_IDS_FLAG_FAKE NV_BIT(3)
1917#define NV_GPU_CONNECTED_IDS_FLAG_EXCLUDE_MST NV_BIT(4)
1918
1920
1923{
1924 NvU32 version;
1925 NV_MONITOR_CONN_TYPE connectorType;
1928
1929 NvU32 isDynamic : 1;
1933 NvU32 isActive : 1;
1934 NvU32 isCluster : 1;
1935 NvU32 isOSVisible : 1;
1936 NvU32 isWFD : 1;
1937 NvU32 isConnected : 1;
1938
1939 NvU32 reservedInternal : 10;
1941 NvU32 reserved : 14;
1943
1946#define NV_GPU_DISPLAYIDS_VER1 MAKE_NVAPI_VERSION(NV_GPU_DISPLAYIDS,1)
1947#define NV_GPU_DISPLAYIDS_VER2 MAKE_NVAPI_VERSION(NV_GPU_DISPLAYIDS,3)
1948
1949#define NV_GPU_DISPLAYIDS_VER NV_GPU_DISPLAYIDS_VER2
1950
1952//
1953// FUNCTION NAME: NvAPI_GPU_GetConnectedDisplayIds
1954//
1982NVAPI_INTERFACE NvAPI_GPU_GetConnectedDisplayIds(__in NvPhysicalGpuHandle hPhysicalGpu, __inout_ecount_part_opt(*pDisplayIdCount, *pDisplayIdCount) NV_GPU_DISPLAYIDS* pDisplayIds, __inout NvU32* pDisplayIdCount, __in NvU32 flags);
1983
1984
1986//
1987// FUNCTION NAME: NvAPI_GPU_GetAllDisplayIds
1988//
2024NVAPI_INTERFACE NvAPI_GPU_GetAllDisplayIds(__in NvPhysicalGpuHandle hPhysicalGpu, __inout_ecount_part_opt(*pDisplayIdCount, *pDisplayIdCount) NV_GPU_DISPLAYIDS* pDisplayIds, __inout NvU32* pDisplayIdCount);
2025
2026
2027
2028
2030//
2031// FUNCTION NAME: NvAPI_GPU_GetConnectedOutputsWithLidState
2032//
2054__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_GPU_GetConnectedDisplayIds.")
2055NVAPI_INTERFACE NvAPI_GPU_GetConnectedOutputsWithLidState(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
2056
2057
2059//
2060// FUNCTION NAME: NvAPI_GPU_GetConnectedSLIOutputsWithLidState
2061//
2079__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_GPU_GetConnectedDisplayIds.")
2080NVAPI_INTERFACE NvAPI_GPU_GetConnectedSLIOutputsWithLidState(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
2081
2082
2084//
2085// FUNCTION NAME: NvAPI_GPU_GetSystemType
2086//
2101//
2103
2106typedef enum
2107{
2108 NV_SYSTEM_TYPE_UNKNOWN = 0,
2109 NV_SYSTEM_TYPE_LAPTOP = 1,
2110 NV_SYSTEM_TYPE_DESKTOP = 2,
2111
2113
2114
2115
2117NVAPI_INTERFACE NvAPI_GPU_GetSystemType(NvPhysicalGpuHandle hPhysicalGpu, NV_SYSTEM_TYPE *pSystemType);
2118
2119
2121//
2122// FUNCTION NAME: NvAPI_GPU_GetActiveOutputs
2123//
2138NVAPI_INTERFACE NvAPI_GPU_GetActiveOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
2139
2141//
2142// FUNCTION NAME: NvAPI_GPU_SetEDID
2143//
2169NVAPI_INTERFACE NvAPI_GPU_SetEDID(NvPhysicalGpuHandle hPhysicalGpu, NvU32 displayOutputId, NV_EDID *pEDID);
2170
2171
2173//
2174// FUNCTION NAME: NvAPI_GPU_GetOutputType
2175//
2189//
2191
2201
2202
2203
2204
2206NVAPI_INTERFACE NvAPI_GPU_GetOutputType(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputId, NV_GPU_OUTPUT_TYPE *pOutputType);
2207
2208
2210//
2211// FUNCTION NAME: NvAPI_GPU_ValidateOutputCombination
2212//
2235NVAPI_INTERFACE NvAPI_GPU_ValidateOutputCombination(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputsMask);
2236
2237
2238
2239
2241//
2242// FUNCTION NAME: NvAPI_GPU_GetFullName
2243//
2256NVAPI_INTERFACE NvAPI_GPU_GetFullName(NvPhysicalGpuHandle hPhysicalGpu, NvAPI_ShortString szName);
2257
2259//
2260// FUNCTION NAME: NvAPI_GPU_GetPCIIdentifiers
2261//
2282NVAPI_INTERFACE NvAPI_GPU_GetPCIIdentifiers(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pDeviceId,NvU32 *pSubSystemId,NvU32 *pRevisionId,NvU32 *pExtDeviceId);
2283
2284
2285
2286
2289typedef enum _NV_GPU_TYPE
2290{
2291 NV_SYSTEM_TYPE_GPU_UNKNOWN = 0,
2295
2296
2298//
2299// FUNCTION NAME: NvAPI_GPU_GetGPUType
2300//
2318NVAPI_INTERFACE NvAPI_GPU_GetGPUType(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_TYPE *pGpuType);
2319
2320
2321
2322
2326{
2327 NVAPI_GPU_BUS_TYPE_UNDEFINED = 0,
2328 NVAPI_GPU_BUS_TYPE_PCI = 1,
2329 NVAPI_GPU_BUS_TYPE_AGP = 2,
2330 NVAPI_GPU_BUS_TYPE_PCI_EXPRESS = 3,
2331 NVAPI_GPU_BUS_TYPE_FPCI = 4,
2332 NVAPI_GPU_BUS_TYPE_AXI = 5,
2335//
2336// FUNCTION NAME: NvAPI_GPU_GetBusType
2337//
2353NVAPI_INTERFACE NvAPI_GPU_GetBusType(NvPhysicalGpuHandle hPhysicalGpu,NV_GPU_BUS_TYPE *pBusType);
2354
2355
2357//
2358// FUNCTION NAME: NvAPI_GPU_GetBusId
2359//
2376NVAPI_INTERFACE NvAPI_GPU_GetBusId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusId);
2377
2379//
2380// FUNCTION NAME: NvAPI_GPU_GetBusSlotId
2381//
2398NVAPI_INTERFACE NvAPI_GPU_GetBusSlotId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusSlotId);
2399
2400
2401
2403//
2404// FUNCTION NAME: NvAPI_GPU_GetIRQ
2405//
2421NVAPI_INTERFACE NvAPI_GPU_GetIRQ(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pIRQ);
2422
2424//
2425// FUNCTION NAME: NvAPI_GPU_GetVbiosRevision
2426//
2442NVAPI_INTERFACE NvAPI_GPU_GetVbiosRevision(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pBiosRevision);
2443
2445//
2446// FUNCTION NAME: NvAPI_GPU_GetVbiosOEMRevision
2447//
2463NVAPI_INTERFACE NvAPI_GPU_GetVbiosOEMRevision(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pBiosRevision);
2464
2466//
2467// FUNCTION NAME: NvAPI_GPU_GetVbiosVersionString
2468//
2486NVAPI_INTERFACE NvAPI_GPU_GetVbiosVersionString(NvPhysicalGpuHandle hPhysicalGpu,NvAPI_ShortString szBiosRevision);
2487
2488
2490//
2491// FUNCTION NAME: NvAPI_GPU_GetAGPAperture
2492//
2506__nvapi_deprecated_function("Do not use this function - it is deprecated in release 455.")
2507NVAPI_INTERFACE NvAPI_GPU_GetAGPAperture(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
2508
2510//
2511// FUNCTION NAME: NvAPI_GPU_GetCurrentAGPRate
2512//
2526__nvapi_deprecated_function("Do not use this function - it is deprecated in release 455.")
2527NVAPI_INTERFACE NvAPI_GPU_GetCurrentAGPRate(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pRate);
2528
2530//
2531// FUNCTION NAME: NvAPI_GPU_GetCurrentPCIEDownstreamWidth
2532//
2549NVAPI_INTERFACE NvAPI_GPU_GetCurrentPCIEDownstreamWidth(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pWidth);
2550
2551
2552
2554//
2555// FUNCTION NAME: NvAPI_GPU_GetPhysicalFrameBufferSize
2556//
2573NVAPI_INTERFACE NvAPI_GPU_GetPhysicalFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
2574
2576//
2577// FUNCTION NAME: NvAPI_GPU_GetVirtualFrameBufferSize
2578//
2595NVAPI_INTERFACE NvAPI_GPU_GetVirtualFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
2596
2597
2598
2600//
2601// FUNCTION NAME: NvAPI_GPU_GetQuadroStatus
2602//
2617__nvapi_deprecated_function("Do not use this function - it is deprecated in release 460.")
2618NVAPI_INTERFACE NvAPI_GPU_GetQuadroStatus(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pStatus);
2619
2620
2622typedef struct _NV_BOARD_INFO
2623{
2624 NvU32 version;
2625 NvU8 BoardNum[16];
2626
2628
2629#define NV_BOARD_INFO_VER1 MAKE_NVAPI_VERSION(NV_BOARD_INFO_V1,1)
2630#ifndef NV_BOARD_INFO_VER
2635#define NV_BOARD_INFO_VER NV_BOARD_INFO_VER1
2636#endif
2637
2641//
2642// FUNCTION NAME: NvAPI_GPU_GetBoardInfo
2643//
2660NVAPI_INTERFACE NvAPI_GPU_GetBoardInfo(NvPhysicalGpuHandle hPhysicalGpu, NV_BOARD_INFO *pBoardInfo);
2661
2662
2663
2664
2666//
2667// FUNCTION NAME: NvAPI_GPU_GetRamBusWidth
2668//
2681NVAPI_INTERFACE NvAPI_GPU_GetRamBusWidth(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusWidth);
2682
2683
2684
2686typedef struct
2687{
2688 NvU32 version;
2689
2690 NvU32 architecture;
2691 NvU32 implementation;
2692 NvU32 revision;
2693
2695
2698{
2699
2700 NV_GPU_ARCHITECTURE_T2X = 0xE0000020,
2701 NV_GPU_ARCHITECTURE_T3X = 0xE0000030,
2702 NV_GPU_ARCHITECTURE_T4X = 0xE0000040,
2703 NV_GPU_ARCHITECTURE_T12X = 0xE0000040,
2704 NV_GPU_ARCHITECTURE_NV40 = 0x00000040,
2705 NV_GPU_ARCHITECTURE_NV50 = 0x00000050,
2706 NV_GPU_ARCHITECTURE_G78 = 0x00000060,
2707 NV_GPU_ARCHITECTURE_G80 = 0x00000080,
2708 NV_GPU_ARCHITECTURE_G90 = 0x00000090,
2709 NV_GPU_ARCHITECTURE_GT200 = 0x000000A0,
2710 NV_GPU_ARCHITECTURE_GF100 = 0x000000C0,
2711 NV_GPU_ARCHITECTURE_GF110 = 0x000000D0,
2712 NV_GPU_ARCHITECTURE_GK100 = 0x000000E0,
2713 NV_GPU_ARCHITECTURE_GK110 = 0x000000F0,
2714 NV_GPU_ARCHITECTURE_GK200 = 0x00000100,
2715 NV_GPU_ARCHITECTURE_GM000 = 0x00000110,
2716 NV_GPU_ARCHITECTURE_GM200 = 0x00000120,
2717 NV_GPU_ARCHITECTURE_GP100 = 0x00000130,
2718 NV_GPU_ARCHITECTURE_GV100 = 0x00000140,
2719 NV_GPU_ARCHITECTURE_GV110 = 0x00000150,
2720 NV_GPU_ARCHITECTURE_TU100 = 0x00000160,
2721 NV_GPU_ARCHITECTURE_GA100 = 0x00000170,
2722 NV_GPU_ARCHITECTURE_AD100 = 0x00000190,
2723
2725
2728{
2729
2730 NV_GPU_ARCH_IMPLEMENTATION_T20 = 0x00000000,
2731
2732 NV_GPU_ARCH_IMPLEMENTATION_T30 = 0x00000000,
2733 NV_GPU_ARCH_IMPLEMENTATION_T35 = 0x00000005,
2734
2735 NV_GPU_ARCH_IMPLEMENTATION_T40 = 0x00000000,
2736 NV_GPU_ARCH_IMPLEMENTATION_T124 = 0x00000000,
2737
2738 NV_GPU_ARCH_IMPLEMENTATION_NV40 = 0x00000000,
2739 NV_GPU_ARCH_IMPLEMENTATION_NV41 = 0x00000001,
2740 NV_GPU_ARCH_IMPLEMENTATION_NV42 = 0x00000002,
2741 NV_GPU_ARCH_IMPLEMENTATION_NV43 = 0x00000003,
2742 NV_GPU_ARCH_IMPLEMENTATION_NV44 = 0x00000004,
2743 NV_GPU_ARCH_IMPLEMENTATION_NV44A = 0x0000000A,
2744 NV_GPU_ARCH_IMPLEMENTATION_NV46 = 0x00000006,
2745 NV_GPU_ARCH_IMPLEMENTATION_NV47 = 0x00000007,
2746 NV_GPU_ARCH_IMPLEMENTATION_NV49 = 0x00000009,
2747 NV_GPU_ARCH_IMPLEMENTATION_NV4B = 0x0000000B,
2748 NV_GPU_ARCH_IMPLEMENTATION_NV4C = 0x0000000C,
2749 NV_GPU_ARCH_IMPLEMENTATION_NV4E = 0x0000000E,
2750
2751 NV_GPU_ARCH_IMPLEMENTATION_NV50 = 0x00000000,
2752
2753 NV_GPU_ARCH_IMPLEMENTATION_NV63 = 0x00000003,
2754 NV_GPU_ARCH_IMPLEMENTATION_NV67 = 0x00000007,
2755
2756 NV_GPU_ARCH_IMPLEMENTATION_G84 = 0x00000004,
2757 NV_GPU_ARCH_IMPLEMENTATION_G86 = 0x00000006,
2758
2759 NV_GPU_ARCH_IMPLEMENTATION_G92 = 0x00000002,
2760 NV_GPU_ARCH_IMPLEMENTATION_G94 = 0x00000004,
2761 NV_GPU_ARCH_IMPLEMENTATION_G96 = 0x00000006,
2762 NV_GPU_ARCH_IMPLEMENTATION_G98 = 0x00000008,
2763
2764 NV_GPU_ARCH_IMPLEMENTATION_GT200 = 0x00000000,
2765 NV_GPU_ARCH_IMPLEMENTATION_GT212 = 0x00000002,
2766 NV_GPU_ARCH_IMPLEMENTATION_GT214 = 0x00000004,
2767 NV_GPU_ARCH_IMPLEMENTATION_GT215 = 0x00000003,
2768 NV_GPU_ARCH_IMPLEMENTATION_GT216 = 0x00000005,
2769 NV_GPU_ARCH_IMPLEMENTATION_GT218 = 0x00000008,
2770 NV_GPU_ARCH_IMPLEMENTATION_MCP77 = 0x0000000A,
2771 NV_GPU_ARCH_IMPLEMENTATION_GT21C = 0x0000000B,
2772 NV_GPU_ARCH_IMPLEMENTATION_MCP79 = 0x0000000C,
2773 NV_GPU_ARCH_IMPLEMENTATION_GT21A = 0x0000000D,
2774 NV_GPU_ARCH_IMPLEMENTATION_MCP89 = 0x0000000F,
2775
2776 NV_GPU_ARCH_IMPLEMENTATION_GF100 = 0x00000000,
2777 NV_GPU_ARCH_IMPLEMENTATION_GF104 = 0x00000004,
2778 NV_GPU_ARCH_IMPLEMENTATION_GF106 = 0x00000003,
2779 NV_GPU_ARCH_IMPLEMENTATION_GF108 = 0x00000001,
2780
2781 NV_GPU_ARCH_IMPLEMENTATION_GF110 = 0x00000000,
2782 NV_GPU_ARCH_IMPLEMENTATION_GF116 = 0x00000006,
2783 NV_GPU_ARCH_IMPLEMENTATION_GF117 = 0x00000007,
2784 NV_GPU_ARCH_IMPLEMENTATION_GF118 = 0x00000008,
2785 NV_GPU_ARCH_IMPLEMENTATION_GF119 = 0x00000009,
2786
2787 NV_GPU_ARCH_IMPLEMENTATION_GK104 = 0x00000004,
2788 NV_GPU_ARCH_IMPLEMENTATION_GK106 = 0x00000006,
2789 NV_GPU_ARCH_IMPLEMENTATION_GK107 = 0x00000007,
2790 NV_GPU_ARCH_IMPLEMENTATION_GK20A = 0x0000000A,
2791 NV_GPU_ARCH_IMPLEMENTATION_GK110 = 0x00000000,
2792
2793 NV_GPU_ARCH_IMPLEMENTATION_GK208 = 0x00000008,
2794
2795 NV_GPU_ARCH_IMPLEMENTATION_GM204 = 0x00000004,
2796 NV_GPU_ARCH_IMPLEMENTATION_GM206 = 0x00000006,
2797
2798 NV_GPU_ARCH_IMPLEMENTATION_GP100 = 0x00000000,
2799 NV_GPU_ARCH_IMPLEMENTATION_GP000 = 0x00000001,
2800 NV_GPU_ARCH_IMPLEMENTATION_GP102 = 0x00000002,
2801 NV_GPU_ARCH_IMPLEMENTATION_GP104 = 0x00000004,
2802 NV_GPU_ARCH_IMPLEMENTATION_GP106 = 0x00000006,
2803 NV_GPU_ARCH_IMPLEMENTATION_GP107 = 0x00000007,
2804 NV_GPU_ARCH_IMPLEMENTATION_GP108 = 0x00000008,
2805
2806 NV_GPU_ARCH_IMPLEMENTATION_GV100 = 0x00000000,
2807 NV_GPU_ARCH_IMPLEMENTATION_GV10B = 0x0000000B,
2808
2809 NV_GPU_ARCH_IMPLEMENTATION_TU100 = 0x00000000,
2810 NV_GPU_ARCH_IMPLEMENTATION_TU102 = 0x00000002,
2811 NV_GPU_ARCH_IMPLEMENTATION_TU104 = 0x00000004,
2812 NV_GPU_ARCH_IMPLEMENTATION_TU106 = 0x00000006,
2813 NV_GPU_ARCH_IMPLEMENTATION_TU116 = 0x00000008,
2814 NV_GPU_ARCH_IMPLEMENTATION_TU117 = 0x00000007,
2815 NV_GPU_ARCH_IMPLEMENTATION_TU000 = 0x00000001,
2816
2817 NV_GPU_ARCH_IMPLEMENTATION_GA100 = 0x00000000,
2818 NV_GPU_ARCH_IMPLEMENTATION_GA102 = 0x00000002,
2819 NV_GPU_ARCH_IMPLEMENTATION_GA104 = 0x00000004,
2820
2821 NV_GPU_ARCH_IMPLEMENTATION_AD102 = 0x00000002,
2822 NV_GPU_ARCH_IMPLEMENTATION_AD103 = 0x00000003,
2823 NV_GPU_ARCH_IMPLEMENTATION_AD104 = 0x00000004,
2824
2826
2828{
2831 NV_GPU_CHIP_REV_A01 = 0x00000011,
2832 NV_GPU_CHIP_REV_A02 = 0x00000012,
2833 NV_GPU_CHIP_REV_A03 = 0x00000013,
2835}NV_GPU_CHIP_REVISION;
2836
2839typedef struct
2840{
2841 NvU32 version;
2842
2843 union
2844 {
2847 };
2848 union
2849 {
2852 };
2853 union
2854 {
2855 NvU32 revision;
2856 NV_GPU_CHIP_REVISION revision_id;
2857 };
2858
2860
2863
2865#define NV_GPU_ARCH_INFO_VER_1 MAKE_NVAPI_VERSION(NV_GPU_ARCH_INFO_V1,1)
2866#define NV_GPU_ARCH_INFO_VER_2 MAKE_NVAPI_VERSION(NV_GPU_ARCH_INFO_V2,2)
2867#define NV_GPU_ARCH_INFO_VER NV_GPU_ARCH_INFO_VER_2
2868
2870//
2871// FUNCTION NAME: NvAPI_GPU_GetArchInfo
2872//
2886//
2888
2890NVAPI_INTERFACE NvAPI_GPU_GetArchInfo(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_ARCH_INFO *pGpuArchInfo);
2891
2892
2893
2895// I2C API
2896// Provides ability to read or write data using I2C protocol.
2897// These APIs allow I2C access only to DDC monitors
2898
2899
2902#define NVAPI_MAX_SIZEOF_I2C_DATA_BUFFER 4096
2903#define NVAPI_MAX_SIZEOF_I2C_REG_ADDRESS 4
2904#define NVAPI_DISPLAY_DEVICE_MASK_MAX 24
2905#define NVAPI_I2C_SPEED_DEPRECATED 0xFFFF
2906
2907typedef enum
2908{
2910 NVAPI_I2C_SPEED_3KHZ,
2911 NVAPI_I2C_SPEED_10KHZ,
2912 NVAPI_I2C_SPEED_33KHZ,
2913 NVAPI_I2C_SPEED_100KHZ,
2914 NVAPI_I2C_SPEED_200KHZ,
2915 NVAPI_I2C_SPEED_400KHZ,
2916} NV_I2C_SPEED;
2917
2937
2958
2982
2984
2985#define NV_I2C_INFO_VER3 MAKE_NVAPI_VERSION(NV_I2C_INFO_V3,3)
2986#define NV_I2C_INFO_VER2 MAKE_NVAPI_VERSION(NV_I2C_INFO_V2,2)
2987#define NV_I2C_INFO_VER1 MAKE_NVAPI_VERSION(NV_I2C_INFO_V1,1)
2988
2989#define NV_I2C_INFO_VER NV_I2C_INFO_VER3
2991
2992/***********************************************************************************/
2993
2994
2996//
2997// FUNCTION NAME: NvAPI_I2CRead
2998//
3027NVAPI_INTERFACE NvAPI_I2CRead(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo);
3028
3030//
3031// FUNCTION NAME: NvAPI_I2CWrite
3032//
3061NVAPI_INTERFACE NvAPI_I2CWrite(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo);
3062
3063
3065//
3066// FUNCTION NAME: NvAPI_GPU_WorkstationFeatureSetup
3067//
3090//
3092
3094typedef enum
3095{
3096 NVAPI_GPU_WORKSTATION_FEATURE_MASK_SWAPGROUP = 0x00000001,
3097 NVAPI_GPU_WORKSTATION_FEATURE_MASK_STEREO = 0x00000010,
3098 NVAPI_GPU_WORKSTATION_FEATURE_MASK_WARPING = 0x00000100,
3099 NVAPI_GPU_WORKSTATION_FEATURE_MASK_PIXINTENSITY = 0x00000200,
3100 NVAPI_GPU_WORKSTATION_FEATURE_MASK_GRAYSCALE = 0x00000400,
3101 NVAPI_GPU_WORKSTATION_FEATURE_MASK_BPC10 = 0x00001000
3102} NVAPI_GPU_WORKSTATION_FEATURE_MASK;
3103
3105NVAPI_INTERFACE NvAPI_GPU_WorkstationFeatureSetup(__in NvPhysicalGpuHandle hPhysicalGpu, __in NvU32 featureEnableMask, __in NvU32 featureDisableMask);
3106
3108//
3109// FUNCTION NAME: NvAPI_GPU_WorkstationFeatureQuery
3110//
3126//
3128
3130NVAPI_INTERFACE NvAPI_GPU_WorkstationFeatureQuery(__in NvPhysicalGpuHandle hPhysicalGpu, __out_opt NvU32 *pConfiguredFeatureMask, __out_opt NvU32 *pConsistentFeatureMask);
3131
3133//
3134// FUNCTION NAME: NvAPI_GPU_GetHDCPSupportStatus
3135//
3152//
3154
3155
3158
3159
3162{
3163 NV_GPU_HDCP_FUSE_STATE_UNKNOWN = 0,
3164 NV_GPU_HDCP_FUSE_STATE_DISABLED = 1,
3165 NV_GPU_HDCP_FUSE_STATE_ENABLED = 2,
3167
3168
3171{
3172 NV_GPU_HDCP_KEY_SOURCE_UNKNOWN = 0,
3173 NV_GPU_HDCP_KEY_SOURCE_NONE = 1,
3174 NV_GPU_HDCP_KEY_SOURCE_CRYPTO_ROM = 2,
3175 NV_GPU_HDCP_KEY_SOURCE_SBIOS = 3,
3176 NV_GPU_HDCP_KEY_SOURCE_I2C_ROM = 4,
3177 NV_GPU_HDCP_KEY_SOURCE_FUSES = 5,
3179
3180
3183{
3184 NV_GPU_HDCP_KEY_SOURCE_STATE_UNKNOWN = 0,
3185 NV_GPU_HDCP_KEY_SOURCE_STATE_ABSENT = 1,
3186 NV_GPU_HDCP_KEY_SOURCE_STATE_PRESENT = 2,
3188
3189
3198
3199
3201#define NV_GPU_GET_HDCP_SUPPORT_STATUS_VER MAKE_NVAPI_VERSION(NV_GPU_GET_HDCP_SUPPORT_STATUS,1)
3202
3203
3205
3206
3208NVAPI_INTERFACE NvAPI_GPU_GetHDCPSupportStatus(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_GET_HDCP_SUPPORT_STATUS *pGetHDCPSupportStatus);
3209
3210
3211
3212
3215
3218
3219#define NV_COMPUTE_GPU_TOPOLOGY_PHYSICS_CAPABLE NV_BIT(0)
3220#define NV_COMPUTE_GPU_TOPOLOGY_PHYSICS_ENABLE NV_BIT(1)
3221#define NV_COMPUTE_GPU_TOPOLOGY_PHYSICS_DEDICATED NV_BIT(2)
3223#define NV_COMPUTE_GPU_TOPOLOGY_PHYSICS_RECOMMENDED NV_BIT(3)
3224#define NV_COMPUTE_GPU_TOPOLOGY_CUDA_AVAILABLE NV_BIT(4)
3225#define NV_COMPUTE_GPU_TOPOLOGY_CUDA_CAPABLE NV_BIT(16)
3226#define NV_COMPUTE_GPU_TOPOLOGY_CUDA_DISABLED NV_BIT(17)
3227#define NV_COMPUTE_GPU_TOPOLOGY_PHYSICS_AVAILABLE NV_BIT(21)
3228
3230
3231typedef struct
3232{
3233 NvU32 version;
3234 NvU32 gpuCount;
3235
3236 struct
3237 {
3238 NvPhysicalGpuHandle hPhysicalGpu;
3239 NvU32 flags;
3240
3241 } computeGpus[NVAPI_MAX_GPU_PER_TOPOLOGY];
3242
3244
3245
3246typedef struct _NV_COMPUTE_GPU
3247{
3248 NvPhysicalGpuHandle hPhysicalGpu;
3249 NvU32 flags;
3250
3252
3260
3262#define NV_COMPUTE_GPU_TOPOLOGY_VER1 MAKE_NVAPI_VERSION(NV_COMPUTE_GPU_TOPOLOGY_V1,1)
3263
3264#define NV_COMPUTE_GPU_TOPOLOGY_VER MAKE_NVAPI_VERSION(NV_COMPUTE_GPU_TOPOLOGY_V2,2)
3266
3268
3270//
3271// FUNCTION NAME: NvAPI_GPU_CudaEnumComputeCapableGpus
3272//
3291__nvapi_deprecated_function("Do not use this function - it is deprecated in release 319.")
3292NVAPI_INTERFACE NvAPI_GPU_CudaEnumComputeCapableGpus(__inout NV_COMPUTE_GPU_TOPOLOGY *pComputeTopo);
3293
3295//
3296// FUNCTION NAME: NvAPI_GPU_GetTachReading
3297//
3324NVAPI_INTERFACE NvAPI_GPU_GetTachReading(NvPhysicalGpuHandle hPhysicalGPU, NvU32 *pValue);
3325
3326
3327
3328
3330//
3331// FUNCTION NAME: NvAPI_GPU_GetECCStatusInfo
3332//
3354//
3356
3360{
3361 NV_ECC_CONFIGURATION_NOT_SUPPORTED = 0,
3364} NV_ECC_CONFIGURATION;
3365
3368typedef struct
3369{
3370 NvU32 version;
3371 NvU32 isSupported : 1;
3372 NV_ECC_CONFIGURATION configurationOptions;
3373 NvU32 isEnabled : 1;
3375
3378#define NV_GPU_ECC_STATUS_INFO_VER MAKE_NVAPI_VERSION(NV_GPU_ECC_STATUS_INFO,1)
3379
3381NVAPI_INTERFACE NvAPI_GPU_GetECCStatusInfo(NvPhysicalGpuHandle hPhysicalGpu,
3382 NV_GPU_ECC_STATUS_INFO *pECCStatusInfo);
3383
3386typedef struct
3387{
3388 NvU32 version;
3389 struct
3390 {
3393 } current;
3394 struct
3395 {
3398 } aggregate;
3400
3403#define NV_GPU_ECC_ERROR_INFO_VER MAKE_NVAPI_VERSION(NV_GPU_ECC_ERROR_INFO,1)
3404
3406//
3407// FUNCTION NAME: NvAPI_GPU_GetECCErrorInfo
3408//
3433//
3436
3437NVAPI_INTERFACE NvAPI_GPU_GetECCErrorInfo(NvPhysicalGpuHandle hPhysicalGpu,
3438 NV_GPU_ECC_ERROR_INFO *pECCErrorInfo);
3439
3440
3442//
3443// FUNCTION NAME: NvAPI_GPU_ResetECCErrorInfo
3444//
3468NVAPI_INTERFACE NvAPI_GPU_ResetECCErrorInfo(NvPhysicalGpuHandle hPhysicalGpu, NvU8 bResetCurrent,
3469 NvU8 bResetAggregate);
3470
3472//
3473// FUNCTION NAME: NvAPI_GPU_GetECCConfigurationInfo
3474//
3498//
3500
3503typedef struct
3504{
3505 NvU32 version;
3506 NvU32 isEnabled : 1;
3509
3512#define NV_GPU_ECC_CONFIGURATION_INFO_VER MAKE_NVAPI_VERSION(NV_GPU_ECC_CONFIGURATION_INFO,1)
3513
3515NVAPI_INTERFACE NvAPI_GPU_GetECCConfigurationInfo(NvPhysicalGpuHandle hPhysicalGpu,
3516 NV_GPU_ECC_CONFIGURATION_INFO *pECCConfigurationInfo);
3517
3518
3520//
3521// FUNCTION NAME: NvAPI_GPU_SetECCConfiguration
3522//
3547NVAPI_INTERFACE NvAPI_GPU_SetECCConfiguration(NvPhysicalGpuHandle hPhysicalGpu, NvU8 bEnable,
3548 NvU8 bEnableImmediately);
3549
3550
3551
3552// The following enum is providing definitions for events signaled by a Quadro Sync (QSYNC) device.
3553// QSYNC event broadcast is supported for Windows 10 and later OS.
3554typedef enum
3555{
3556 NV_QSYNC_EVENT_NONE = 0,
3557 NV_QSYNC_EVENT_SYNC_LOSS = 1, // Frame Lock sync loss event
3558 NV_QSYNC_EVENT_SYNC_GAIN = 2, // Frame Lock sync gain event
3559 NV_QSYNC_EVENT_HOUSESYNC_GAIN = 3, // House cable gain(plug in) event
3560 NV_QSYNC_EVENT_HOUSESYNC_LOSS = 4, // House cable loss(plug out) event
3561 NV_QSYNC_EVENT_RJ45_GAIN = 5, // RJ45 cable gain(plug in) event
3562 NV_QSYNC_EVENT_RJ45_LOSS = 6, // RJ45 cable loss(plug out) event
3563} NV_QSYNC_EVENT;
3564
3565typedef struct
3566{
3567 NV_QSYNC_EVENT qsyncEvent; // One of the value of the enum NV_QSYNC_EVENT
3568 NvU32 reserved[7]; // Reserved for future use. Do not use this.
3570
3572typedef void(__cdecl *NVAPI_CALLBACK_QSYNCEVENT)(NV_QSYNC_EVENT_DATA qyncEventData, void *callbackParam);
3573
3574
3576typedef enum
3577{
3578 NV_EVENT_TYPE_NONE = 0,
3579 NV_EVENT_TYPE_QSYNC = 6,
3581
3594
3596#define NV_EVENT_REGISTER_CALLBACK_VERSION MAKE_NVAPI_VERSION(NV_EVENT_REGISTER_CALLBACK,1)
3597
3598
3606
3607
3609// FUNCTION NAME: NvAPI_GPU_QueryWorkstationFeatureSupport
3610//
3635NVAPI_INTERFACE NvAPI_GPU_QueryWorkstationFeatureSupport(NvPhysicalGpuHandle physicalGpu, NV_GPU_WORKSTATION_FEATURE_TYPE gpuWorkstationFeature);
3636
3637
3638
3640typedef struct
3641{
3642 NvU32 version;
3643 NvU32 width;
3644 NvU32 height;
3647
3658
3660
3662#define NV_SCANOUT_INTENSITY_DATA_VER1 MAKE_NVAPI_VERSION(NV_SCANOUT_INTENSITY_DATA_V1, 1)
3663#define NV_SCANOUT_INTENSITY_DATA_VER2 MAKE_NVAPI_VERSION(NV_SCANOUT_INTENSITY_DATA_V2, 2)
3664#define NV_SCANOUT_INTENSITY_DATA_VER NV_SCANOUT_INTENSITY_DATA_VER2
3665
3667// FUNCTION NAME: NvAPI_GPU_SetScanoutIntensity
3668//
3688NVAPI_INTERFACE NvAPI_GPU_SetScanoutIntensity(NvU32 displayId, NV_SCANOUT_INTENSITY_DATA* scanoutIntensityData, int *pbSticky);
3689
3690
3697
3699#define NV_SCANOUT_INTENSITY_STATE_VER MAKE_NVAPI_VERSION(NV_SCANOUT_INTENSITY_STATE_DATA, 1)
3700
3702// FUNCTION NAME: NvAPI_GPU_GetScanoutIntensityState
3703//
3723NVAPI_INTERFACE NvAPI_GPU_GetScanoutIntensityState(__in NvU32 displayId, __inout NV_SCANOUT_INTENSITY_STATE_DATA* scanoutIntensityStateData);
3724
3725
3727typedef enum
3728{
3729 NV_GPU_WARPING_VERTICE_FORMAT_TRIANGLESTRIP_XYUVRQ = 0,
3730 NV_GPU_WARPING_VERTICE_FORMAT_TRIANGLES_XYUVRQ = 1,
3731} NV_GPU_WARPING_VERTICE_FORMAT;
3732
3734typedef struct
3735{
3736 NvU32 version;
3737 float* vertices;
3738 NV_GPU_WARPING_VERTICE_FORMAT vertexFormat;
3742
3744#define NV_SCANOUT_WARPING_VER MAKE_NVAPI_VERSION(NV_SCANOUT_WARPING_DATA, 1)
3745
3746
3748// FUNCTION NAME: NvAPI_GPU_SetScanoutWarping
3749//
3769
3770NVAPI_INTERFACE NvAPI_GPU_SetScanoutWarping(NvU32 displayId, NV_SCANOUT_WARPING_DATA* scanoutWarpingData, int* piMaxNumVertices, int* pbSticky);
3771
3772
3779
3781#define NV_SCANOUT_WARPING_STATE_VER MAKE_NVAPI_VERSION(NV_SCANOUT_WARPING_STATE_DATA, 1)
3782
3784// FUNCTION NAME: NvAPI_GPU_GetScanoutWarpingState
3785//
3805NVAPI_INTERFACE NvAPI_GPU_GetScanoutWarpingState(__in NvU32 displayId, __inout NV_SCANOUT_WARPING_STATE_DATA* scanoutWarpingStateData);
3806
3807typedef enum
3808{
3809 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_WARPING_RESAMPLING_METHOD = 0
3810} NV_GPU_SCANOUT_COMPOSITION_PARAMETER;
3811
3814typedef enum
3815{
3816 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_SET_TO_DEFAULT = 0, // Set parameter to default value.
3817 // WARPING_RESAMPLING_METHOD section:
3818 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BILINEAR = 0x100,
3819 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_TRIANGULAR = 0x101,
3820 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_BELL_SHAPED = 0x102,
3821 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_BSPLINE = 0x103,
3822 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_TRIANGULAR = 0x104,
3823 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BELL_SHAPED = 0x105,
3824 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE_WARPING_RESAMPLING_METHOD_BICUBIC_ADAPTIVE_BSPLINE = 0x106
3826
3828// FUNCTION NAME: NvAPI_GPU_SetScanoutCompositionParameter
3829//
3851
3852NVAPI_INTERFACE NvAPI_GPU_SetScanoutCompositionParameter(NvU32 displayId, NV_GPU_SCANOUT_COMPOSITION_PARAMETER parameter,
3853 NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE parameterValue, float *pContainer);
3854
3855
3857// FUNCTION NAME: NvAPI_GPU_GetScanoutCompositionParameter
3858//
3880NVAPI_INTERFACE NvAPI_GPU_GetScanoutCompositionParameter(__in NvU32 displayId, __in NV_GPU_SCANOUT_COMPOSITION_PARAMETER parameter,
3881 __out NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE *parameterData, __out float *pContainer);
3882
3883
3885// FUNCTION NAME: NvAPI_GPU_GetScanoutConfiguration
3886//
3904NVAPI_INTERFACE NvAPI_GPU_GetScanoutConfiguration(NvU32 displayId, NvSBox* desktopRect, NvSBox* scanoutRect);
3905
3906
3907
3922
3923#define NV_SCANOUT_INFORMATION_VER MAKE_NVAPI_VERSION(NV_SCANOUT_INFORMATION,1)
3924
3926// FUNCTION NAME: NvAPI_GPU_GetScanoutConfigurationEx
3927//
3941NVAPI_INTERFACE NvAPI_GPU_GetScanoutConfigurationEx(__in NvU32 displayId, __inout NV_SCANOUT_INFORMATION *pScanoutInformation);
3942
3944//
3945// FUNCTION NAME: NvAPI_GPU_GetAdapterIdFromPhysicalGpu
3946//
3966__nvapi_deprecated_function("Do not use this function - it is deprecated in release 520. Instead, use NvAPI_GPU_GetLogicalGpuInfo.")
3967NVAPI_INTERFACE NvAPI_GPU_GetAdapterIdFromPhysicalGpu(NvPhysicalGpuHandle hPhysicalGpu, void *pOSAdapterId);
3968
3969
3970
3971
3980
3983{
3984 NvU32 version;
3985
3986 NV_VIRTUALIZATION_MODE virtualizationMode;
3987 NvU32 reserved;
3989
3992
3994#define NV_GPU_VIRTUALIZATION_INFO_VER1 MAKE_NVAPI_VERSION(NV_GPU_VIRTUALIZATION_INFO_V1,1)
3995
3997#define NV_GPU_VIRTUALIZATION_INFO_VER NV_GPU_VIRTUALIZATION_INFO_VER1
3998
3999
4020NVAPI_INTERFACE NvAPI_GPU_GetVirtualizationInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_VIRTUALIZATION_INFO *pVirtualizationInfo);
4021
4022
4025{
4026 NvU32 version;
4029
4030 NvPhysicalGpuHandle physicalGpuHandles[NVAPI_MAX_PHYSICAL_GPUS];
4036 NvU32 reserved[8];
4038
4041#define NV_LOGICAL_GPU_DATA_VER1 MAKE_NVAPI_VERSION(NV_LOGICAL_GPU_DATA_V1,1)
4042#define NV_LOGICAL_GPU_DATA_VER NV_LOGICAL_GPU_DATA_VER1
4043
4045//
4046// FUNCTION NAME: NvAPI_GPU_GetLogicalGpuInfo
4047//
4063NVAPI_INTERFACE NvAPI_GPU_GetLogicalGpuInfo(__in NvLogicalGpuHandle hLogicalGpu, __inout NV_LOGICAL_GPU_DATA *pLogicalGpuData);
4064
4065
4068
4070#define NV_LICENSE_MAX_COUNT 3
4071
4073#define NV_LICENSE_SIGNATURE_SIZE (128)
4074
4076#define NV_LICENSE_INFO_MAX_LENGTH (128)
4077
4080
4083{
4084 NV_LICENSE_FEATURE_UNKNOWN = 0,
4085 NV_LICENSE_FEATURE_VGPU = 1,
4086 NV_LICENSE_FEATURE_NVIDIA_RTX = 2,
4087 NV_LICENSE_FEATURE_QUADRO = NV_LICENSE_FEATURE_NVIDIA_RTX,
4088 NV_LICENSE_FEATURE_GAMING = 3,
4089 NV_LICENSE_FEATURE_COMPUTE = 4,
4091
4101{
4102 NvU32 year;
4103 NvU16 month;
4104 NvU16 day;
4105 NvU16 hour;
4106 NvU16 min;
4107 NvU16 sec;
4108
4109 NvU8 status;
4111
4121
4131
4142
4154
4156
4157#define NV_LICENSE_FEATURE_DETAILS_VER1 MAKE_NVAPI_VERSION(NV_LICENSE_FEATURE_DETAILS_V1, 1)
4158#define NV_LICENSE_FEATURE_DETAILS_VER NV_LICENSE_FEATURE_DETAILS_VER1
4159
4171
4182
4193
4204
4206
4207#define NV_LICENSABLE_FEATURES_VER1 MAKE_NVAPI_VERSION(NV_LICENSABLE_FEATURES_V1, 1)
4208#define NV_LICENSABLE_FEATURES_VER2 MAKE_NVAPI_VERSION(NV_LICENSABLE_FEATURES_V2, 2)
4209#define NV_LICENSABLE_FEATURES_VER3 MAKE_NVAPI_VERSION(NV_LICENSABLE_FEATURES_V3, 3)
4210#define NV_LICENSABLE_FEATURES_VER4 MAKE_NVAPI_VERSION(NV_LICENSABLE_FEATURES_V4, 4)
4211#define NV_LICENSABLE_FEATURES_VER NV_LICENSABLE_FEATURES_VER4
4212
4214
4216//
4217// FUNCTION NAME: NvAPI_GPU_GetLicensableFeatures
4218//
4235NVAPI_INTERFACE NvAPI_GPU_GetLicensableFeatures(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_LICENSABLE_FEATURES *pLicensableFeatures);
4236
4237
4238#define NVAPI_NVLINK_COUNTER_MAX_TYPES 32
4239#define NVAPI_NVLINK_MAX_LINKS 32
4240
4244
4245/* caps format is byte_index:bit_mask */
4246#define NVAPI_NVLINK_CAPS_SUPPORTED 0x00000001
4247#define NVAPI_NVLINK_CAPS_P2P_SUPPORTED 0x00000002
4248#define NVAPI_NVLINK_CAPS_SYSMEM_ACCESS 0x00000004
4249#define NVAPI_NVLINK_CAPS_P2P_ATOMICS 0x00000008
4250#define NVAPI_NVLINK_CAPS_SYSMEM_ATOMICS 0x00000010
4251#define NVAPI_NVLINK_CAPS_PEX_TUNNELING 0x00000020
4252#define NVAPI_NVLINK_CAPS_SLI_BRIDGE 0x00000040
4253#define NVAPI_NVLINK_CAPS_SLI_BRIDGE_SENSABLE 0x00000080
4254#define NVAPI_NVLINK_CAPS_POWER_STATE_L0 0x00000100
4255#define NVAPI_NVLINK_CAPS_POWER_STATE_L1 0x00000200
4256#define NVAPI_NVLINK_CAPS_POWER_STATE_L2 0x00000400
4257#define NVAPI_NVLINK_CAPS_POWER_STATE_L3 0x00000800
4258
4259#define NVAPI_NVLINK_CAPS_VALID 0x00001000
4260
4261#define NVAPI_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000)
4262#define NVAPI_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001)
4263#define NVAPI_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002)
4264
4265#define NVAPI_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000)
4266#define NVAPI_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001)
4267#define NVAPI_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002)
4268
4279
4281#define NVLINK_GET_CAPS_VER1 MAKE_NVAPI_VERSION(NVLINK_GET_CAPS_V1, 1)
4282
4283#define NVLINK_GET_CAPS_VER NVLINK_GET_CAPS_VER1
4286//
4287// FUNCTION NAME: NvAPI_GPU_NVLINK_GetCaps
4288//
4308NVAPI_INTERFACE NvAPI_GPU_NVLINK_GetCaps(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NVLINK_GET_CAPS *capsParams);
4309
4310
4314
4315#define NVAPI_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000)
4316#define NVAPI_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001)
4317#define NVAPI_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002)
4318
4319typedef enum _NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE
4320{
4321 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE,
4322 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU,
4323 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU,
4324 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH,
4325 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA,
4326 NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE,
4327 NVAPI_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID,
4328} NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE;
4329
4330typedef struct
4331{
4335 NvU16 domain;
4336 NvU16 bus;
4337 NvU16 device;
4338 NvU16 function;
4339 NvU32 pciDeviceId;
4341 NvU8 deviceUUID[16];
4343
4344typedef enum _NVAPI_NVLINK_STATUS_LINK_STATE
4345{
4346 NVAPI_NVLINK_STATUS_LINK_STATE_UNKNOWN,
4347 NVAPI_NVLINK_STATUS_LINK_STATE_INIT,
4348 NVAPI_NVLINK_STATUS_LINK_STATE_HWCFG,
4349 NVAPI_NVLINK_STATUS_LINK_STATE_SWCFG,
4350 NVAPI_NVLINK_STATUS_LINK_STATE_ACTIVE,
4351 NVAPI_NVLINK_STATUS_LINK_STATE_FAULT,
4352 NVAPI_NVLINK_STATUS_LINK_STATE_RECOVERY,
4353 NVAPI_NVLINK_STATUS_LINK_STATE_RECOVERY_AC,
4354 NVAPI_NVLINK_STATUS_LINK_STATE_RECOVERY_AX,
4355 NVAPI_NVLINK_STATUS_LINK_STATE_INVALID = 0xFFFFFFFF,
4356}NVAPI_NVLINK_STATUS_LINK_STATE;
4357
4358typedef enum _NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE
4359{
4360 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_UNKNOWN,
4361 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1,
4362 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_LOW_POWER,
4363 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING,
4364 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE,
4365 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_OFF,
4366 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_TEST,
4367 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_FAULT,
4368 NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID = 0xFF,
4369}NVAPI_NVLINK_STATUS_SUBLINK_RX_STATE;
4370
4371typedef enum _NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE
4372{
4373 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_UNKNOWN,
4374 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1,
4375 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_LOW_POWER,
4376 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING,
4377 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE,
4378 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_OFF,
4379 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_TEST,
4380 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_FAULT,
4381
4382 NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID= 0xFF,
4383} NVAPI_NVLINK_STATUS_SUBLINK_TX_STATE;
4384
4385
4386#define NVAPI_NVLINK_STATUS_PHY_NVHS (0x00000001)
4387#define NVAPI_NVLINK_STATUS_PHY_GRS (0x00000002)
4388#define NVAPI_NVLINK_STATUS_PHY_INVALID (0x000000FF)
4389
4390#define NVAPI_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001)
4391#define NVAPI_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002)
4392#define NVAPI_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FF)
4393
4394#define NVAPI_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001)
4395#define NVAPI_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002)
4396#define NVAPI_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FF)
4397
4398#define NVAPI_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001)
4399#define NVAPI_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FF)
4400
4401#define NVAPI_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001)
4402#define NVAPI_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FF)
4403
4404#define NVAPI_NVLINK_STATUS_CONNECTED_TRUE (0x00000001)
4405#define NVAPI_NVLINK_STATUS_CONNECTED_FALSE (0x00000000)
4406
4407#define NVAPI_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001)
4408#define NVAPI_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002)
4409#define NVAPI_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000)
4410
4411#define NVAPI_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FF)
4412
4413#define NVAPI_NVLINK_REFCLK_TYPE_INVALID (0x00)
4414#define NVAPI_NVLINK_REFCLK_TYPE_NVHS (0x01)
4415#define NVAPI_NVLINK_REFCLK_TYPE_PEX (0x02)
4416
4417
4439
4465
4466typedef struct
4467{
4468 NvU32 version;
4469 NvU32 linkMask;
4470 NVLINK_LINK_STATUS_INFO_V1 linkInfo[NVAPI_NVLINK_MAX_LINKS];
4472
4473typedef struct
4474{
4475 NvU32 version;
4476 NvU32 linkMask;
4477 NVLINK_LINK_STATUS_INFO_V2 linkInfo[NVAPI_NVLINK_MAX_LINKS];
4479
4480
4482#define NVLINK_GET_STATUS_VER1 MAKE_NVAPI_VERSION(NVLINK_GET_STATUS_V1, 1)
4483#define NVLINK_GET_STATUS_VER2 MAKE_NVAPI_VERSION(NVLINK_GET_STATUS_V2, 2)
4484
4485#define NVLINK_GET_STATUS_VER NVLINK_GET_STATUS_VER2
4488//
4489// FUNCTION NAME: NvAPI_GPU_NVLINK_GetStatus
4490//
4511NVAPI_INTERFACE NvAPI_GPU_NVLINK_GetStatus(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NVLINK_GET_STATUS* statusParams);
4512
4513
4514typedef struct _NV_GPU_INFO_V1
4515{
4516 NvU32 version;
4518 NvU32 reserved:31;
4520
4531
4532#define NV_GPU_INFO_VER1 MAKE_NVAPI_VERSION(NV_GPU_INFO_V1, 1)
4533#define NV_GPU_INFO_VER2 MAKE_NVAPI_VERSION(NV_GPU_INFO_V2, 2)
4534#define NV_GPU_INFO_VER NV_GPU_INFO_VER2
4536
4538//
4539// FUNCTION NAME: NvAPI_GPU_GetGPUInfo
4540//
4558NVAPI_INTERFACE NvAPI_GPU_GetGPUInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_INFO *pGpuInfo);
4559
4560
4561
4563{
4564 NvU32 version;
4565 NvU32 isVRReady : 1;
4566 NvU32 reserved : 31;
4568
4569#define NV_GPU_VR_READY_VER1 MAKE_NVAPI_VERSION(NV_GPU_VR_READY_V1, 1)
4570#define NV_GPU_VR_READY_VER NV_GPU_VR_READY_VER1
4572
4574//
4575// FUNCTION NAME: NvAPI_GPU_GetVRReadyData
4576//
4594NVAPI_INTERFACE NvAPI_GPU_GetVRReadyData(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_VR_READY *pGpuVrReadyData);
4595
4608
4609
4611//
4612// FUNCTION NAME: NvAPI_GPU_GetPerfDecreaseInfo
4613//
4625NVAPI_INTERFACE NvAPI_GPU_GetPerfDecreaseInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NvU32 *pPerfDecrInfo);
4626
4627
4630typedef struct
4631{
4632 NvU32 version;
4633 NvU32 flags;
4639 struct
4640 {
4641 NV_GPU_PERF_PSTATE_ID pstateId;
4642 NvU32 flags;
4646 struct
4647 {
4648 NV_GPU_PUBLIC_CLOCK_ID domainId;
4649 NvU32 flags;
4650 NvU32 freq;
4651
4652 } clocks[NVAPI_MAX_GPU_PERF_CLOCKS];
4653 } pstates[NVAPI_MAX_GPU_PERF_PSTATES];
4654
4656
4657
4659typedef struct
4660{
4661 NvU32 version;
4662 NvU32 flags;
4668 NvU32 numVoltages;
4669 struct
4670 {
4671 NV_GPU_PERF_PSTATE_ID pstateId;
4672 NvU32 flags;
4676 struct
4677 {
4678 NV_GPU_PUBLIC_CLOCK_ID domainId;
4679 NvU32 flags;
4681 NvU32 freq;
4682
4683 } clocks[NVAPI_MAX_GPU_PERF_CLOCKS];
4684 struct
4685 {
4686 NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId;
4687 NvU32 flags;
4688 NvU32 mvolt;
4689
4690 } voltages[NVAPI_MAX_GPU_PERF_VOLTAGES];
4691
4692 } pstates[NVAPI_MAX_GPU_PERF_PSTATES];
4693
4695
4698
4699
4702
4704#define NV_GPU_PERF_PSTATES_INFO_VER1 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES_INFO_V1,1)
4705
4707#define NV_GPU_PERF_PSTATES_INFO_VER2 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES_INFO_V2,2)
4708
4710#define NV_GPU_PERF_PSTATES_INFO_VER3 MAKE_NVAPI_VERSION(NV_GPU_PERF_PSTATES_INFO_V2,3)
4711
4713#define NV_GPU_PERF_PSTATES_INFO_VER NV_GPU_PERF_PSTATES_INFO_VER3
4714
4716
4718//
4719// FUNCTION NAME: NvAPI_GPU_GetPstatesInfoEx
4720//
4779__nvapi_deprecated_function("Do not use this function - it is deprecated in release 304. Instead, use NvAPI_GPU_GetPstates20.")
4780NVAPI_INTERFACE NvAPI_GPU_GetPstatesInfoEx(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_PERF_PSTATES_INFO *pPerfPstatesInfo, NvU32 inputFlags);
4781
4782
4784//
4785// FUNCTION NAME: NvAPI_GPU_GetPstates20
4786//
4816NVAPI_INTERFACE NvAPI_GPU_GetPstates20(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_PERF_PSTATES20_INFO *pPstatesInfo);
4817
4819//
4820// FUNCTION NAME: NvAPI_GPU_GetCurrentPstate
4821//
4842NVAPI_INTERFACE NvAPI_GPU_GetCurrentPstate(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_PERF_PSTATE_ID *pCurrentPstate);
4843
4844
4845
4846
4848#define NVAPI_MAX_GPU_UTILIZATIONS 8
4849
4850
4851
4854typedef struct
4855{
4856 NvU32 version;
4857 NvU32 flags;
4858 struct
4859 {
4860 NvU32 bIsPresent:1;
4862 } utilization[NVAPI_MAX_GPU_UTILIZATIONS];
4864
4867#define NV_GPU_DYNAMIC_PSTATES_INFO_EX_VER MAKE_NVAPI_VERSION(NV_GPU_DYNAMIC_PSTATES_INFO_EX,1)
4868
4870//
4871// FUNCTION NAME: NvAPI_GPU_GetDynamicPstatesInfoEx
4872//
4895NVAPI_INTERFACE NvAPI_GPU_GetDynamicPstatesInfoEx(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx);
4897// Thermal API
4898// Provides ability to get temperature levels from the various thermal sensors associated with the GPU
4899
4901#define NVAPI_MAX_THERMAL_SENSORS_PER_GPU 3
4902
4905typedef enum
4906{
4907 NVAPI_THERMAL_TARGET_NONE = 0,
4915
4916 NVAPI_THERMAL_TARGET_ALL = 15,
4917 NVAPI_THERMAL_TARGET_UNKNOWN = -1,
4919
4922typedef enum
4923{
4924 NVAPI_THERMAL_CONTROLLER_NONE = 0,
4925 NVAPI_THERMAL_CONTROLLER_GPU_INTERNAL,
4926 NVAPI_THERMAL_CONTROLLER_ADM1032,
4927 NVAPI_THERMAL_CONTROLLER_MAX6649,
4928 NVAPI_THERMAL_CONTROLLER_MAX1617,
4929 NVAPI_THERMAL_CONTROLLER_LM99,
4930 NVAPI_THERMAL_CONTROLLER_LM89,
4931 NVAPI_THERMAL_CONTROLLER_LM64,
4932 NVAPI_THERMAL_CONTROLLER_ADT7473,
4933 NVAPI_THERMAL_CONTROLLER_SBMAX6649,
4934 NVAPI_THERMAL_CONTROLLER_VBIOSEVT,
4935 NVAPI_THERMAL_CONTROLLER_OS,
4936 NVAPI_THERMAL_CONTROLLER_UNKNOWN = -1,
4938
4941typedef struct
4942{
4943 NvU32 version;
4944 NvU32 count;
4945 struct
4946 {
4952 } sensor[NVAPI_MAX_THERMAL_SENSORS_PER_GPU];
4953
4955
4957typedef struct
4958{
4959 NvU32 version;
4960 NvU32 count;
4961 struct
4962 {
4968 } sensor[NVAPI_MAX_THERMAL_SENSORS_PER_GPU];
4969
4971
4974
4977
4979#define NV_GPU_THERMAL_SETTINGS_VER_1 MAKE_NVAPI_VERSION(NV_GPU_THERMAL_SETTINGS_V1,1)
4980
4982#define NV_GPU_THERMAL_SETTINGS_VER_2 MAKE_NVAPI_VERSION(NV_GPU_THERMAL_SETTINGS_V2,2)
4983
4985#define NV_GPU_THERMAL_SETTINGS_VER NV_GPU_THERMAL_SETTINGS_VER_2
4987
4988
4990//
4991// FUNCTION NAME: NvAPI_GPU_GetThermalSettings
4992//
5018NVAPI_INTERFACE NvAPI_GPU_GetThermalSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 sensorIndex, NV_GPU_THERMAL_SETTINGS *pThermalSettings);
5019
5020
5021
5024typedef struct
5025{
5026 NvU32 version;
5027 NvU32 reserved;
5028 struct
5029 {
5030 NvU32 bIsPresent:1;
5031 NvU32 reserved:31;
5033 }domain[NVAPI_MAX_GPU_PUBLIC_CLOCKS];
5035
5036#ifndef NV_GPU_MAX_CLOCK_FREQUENCIES
5037 #define NV_GPU_MAX_CLOCK_FREQUENCIES 3
5038#endif
5039
5042typedef enum
5043{
5044 NV_GPU_CLOCK_FREQUENCIES_CURRENT_FREQ = 0,
5045 NV_GPU_CLOCK_FREQUENCIES_BASE_CLOCK = 1,
5046 NV_GPU_CLOCK_FREQUENCIES_BOOST_CLOCK = 2,
5047 NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE_NUM = NV_GPU_MAX_CLOCK_FREQUENCIES
5049
5052typedef struct
5053{
5054 NvU32 version;
5055 NvU32 ClockType:4;
5056 NvU32 reserved:20;
5057 NvU32 reserved1:8;
5058 struct
5059 {
5060 NvU32 bIsPresent:1;
5061 NvU32 reserved:31;
5063 }domain[NVAPI_MAX_GPU_PUBLIC_CLOCKS];
5065
5069
5072#define NV_GPU_CLOCK_FREQUENCIES_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V1,1)
5073#define NV_GPU_CLOCK_FREQUENCIES_VER_2 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V2,2)
5074#define NV_GPU_CLOCK_FREQUENCIES_VER_3 MAKE_NVAPI_VERSION(NV_GPU_CLOCK_FREQUENCIES_V2,3)
5075#define NV_GPU_CLOCK_FREQUENCIES_VER NV_GPU_CLOCK_FREQUENCIES_VER_3
5077
5079//
5080// FUNCTION NAME: NvAPI_GPU_GetAllClockFrequencies
5081//
5104NVAPI_INTERFACE NvAPI_GPU_GetAllClockFrequencies(__in NvPhysicalGpuHandle hPhysicalGPU, __inout NV_GPU_CLOCK_FREQUENCIES *pClkFreqs);
5105
5106
5131//
5133
5135typedef enum _NV_GPU_ILLUMINATION_ATTRIB
5136{
5137 NV_GPU_IA_LOGO_BRIGHTNESS = 0,
5138 NV_GPU_IA_SLI_BRIGHTNESS = 1,
5139} NV_GPU_ILLUMINATION_ATTRIB;
5140
5143
5144 // IN
5145 NvU32 version;
5146 NvPhysicalGpuHandle hPhysicalGpu;
5153 NV_GPU_ILLUMINATION_ATTRIB Attribute;
5155
5156 // OUT
5158
5160
5164#define NV_GPU_QUERY_ILLUMINATION_SUPPORT_PARM_VER_1 MAKE_NVAPI_VERSION(NV_GPU_QUERY_ILLUMINATION_SUPPORT_PARM_V1,1)
5166#define NV_GPU_QUERY_ILLUMINATION_SUPPORT_PARM_VER NV_GPU_QUERY_ILLUMINATION_SUPPORT_PARM_VER_1
5167
5169NVAPI_INTERFACE NvAPI_GPU_QueryIlluminationSupport(__inout NV_GPU_QUERY_ILLUMINATION_SUPPORT_PARM *pIlluminationSupportInfo);
5170
5171
5172
5173
5203//
5205
5208
5209 // IN
5210 NvU32 version;
5211 NvPhysicalGpuHandle hPhysicalGpu;
5218 NV_GPU_ILLUMINATION_ATTRIB Attribute;
5220
5221 // OUT
5222 NvU32 Value;
5225
5227
5231#define NV_GPU_GET_ILLUMINATION_PARM_VER_1 MAKE_NVAPI_VERSION(NV_GPU_GET_ILLUMINATION_PARM_V1,1)
5233#define NV_GPU_GET_ILLUMINATION_PARM_VER NV_GPU_GET_ILLUMINATION_PARM_VER_1
5234
5236NVAPI_INTERFACE NvAPI_GPU_GetIllumination(NV_GPU_GET_ILLUMINATION_PARM *pIlluminationInfo);
5237
5238
5239
5240
5271//
5273
5276
5277 // IN
5278 NvU32 version;
5279 NvPhysicalGpuHandle hPhysicalGpu;
5286 NV_GPU_ILLUMINATION_ATTRIB Attribute;
5288 NvU32 Value;
5292
5293 // OUT
5294
5296
5300#define NV_GPU_SET_ILLUMINATION_PARM_VER_1 MAKE_NVAPI_VERSION(NV_GPU_SET_ILLUMINATION_PARM_V1,1)
5302#define NV_GPU_SET_ILLUMINATION_PARM_VER NV_GPU_SET_ILLUMINATION_PARM_VER_1
5303
5305NVAPI_INTERFACE NvAPI_GPU_SetIllumination(NV_GPU_SET_ILLUMINATION_PARM *pIlluminationInfo);
5306
5307
5308
5312typedef enum
5313{
5314 NV_GPU_CLIENT_ILLUM_CTRL_MODE_MANUAL_RGB = 0, // deprecated
5315 NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_RGB, // deprecated
5316
5317 NV_GPU_CLIENT_ILLUM_CTRL_MODE_MANUAL = 0,
5318 NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR,
5319
5320 // Strictly add new control modes above this.
5321 NV_GPU_CLIENT_ILLUM_CTRL_MODE_INVALID = 0xFF,
5323
5331typedef enum
5332{
5333 NV_GPU_CLIENT_ILLUM_ZONE_LOCATION_GPU_TOP_0 = 0x00,
5334 NV_GPU_CLIENT_ILLUM_ZONE_LOCATION_GPU_FRONT_0 = 0x08,
5335 NV_GPU_CLIENT_ILLUM_ZONE_LOCATION_GPU_BACK_0 = 0x0C,
5336 NV_GPU_CLIENT_ILLUM_ZONE_LOCATION_SLI_TOP_0 = 0x20,
5337 NV_GPU_CLIENT_ILLUM_ZONE_LOCATION_INVALID = 0xFFFFFFFF,
5339
5343typedef enum
5344{
5345 NV_GPU_CLIENT_ILLUM_DEVICE_TYPE_INVALID = 0,
5346 NV_GPU_CLIENT_ILLUM_DEVICE_TYPE_MCUV10,
5347 NV_GPU_CLIENT_ILLUM_DEVICE_TYPE_GPIO_PWM_RGBW_V10,
5348 NV_GPU_CLIENT_ILLUM_DEVICE_TYPE_GPIO_PWM_SINGLE_COLOR_V10,
5350
5354typedef enum
5355{
5356 NV_GPU_CLIENT_ILLUM_ZONE_TYPE_INVALID = 0,
5357 NV_GPU_CLIENT_ILLUM_ZONE_TYPE_RGB,
5358 NV_GPU_CLIENT_ILLUM_ZONE_TYPE_COLOR_FIXED,
5359 NV_GPU_CLIENT_ILLUM_ZONE_TYPE_RGBW,
5360 NV_GPU_CLIENT_ILLUM_ZONE_TYPE_SINGLE_COLOR,
5362
5366#define NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS 2
5367
5371typedef enum
5372{
5373 NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_HALF_HALT = 0,
5374 NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_FULL_HALT,
5375 NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_FULL_REPEAT,
5376 NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_INVALID = 0xFF,
5378
5379#define NV_GPU_CLIENT_ILLUM_DEVICE_NUM_DEVICES_MAX 32
5380
5392
5430
5434{
5439
5444
5449 union
5450 {
5451 //
5452 // Need to be careful when add/expanding types in this union. If any type
5453 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
5454 //
5458
5462 NvU8 rsvd[64];
5464
5468 NvU8 rsvd[64];
5470
5474{
5478 NvU32 version;
5479
5484
5488 NvU8 rsvd[64];
5489
5492 NV_GPU_CLIENT_ILLUM_DEVICE_INFO_V1 devices[NV_GPU_CLIENT_ILLUM_DEVICE_NUM_DEVICES_MAX];
5494
5495#define NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS_V1, 1)
5496#define NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS_VER NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS_VER_1
5498
5505//
5519NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesGetInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS *pIllumDevicesInfo);
5520
5521
5525typedef struct
5526{
5530 NvBool bSync;
5531
5536
5540 NvU8 rsvd[64];
5542
5563
5565
5569typedef struct
5570{
5574 NvU32 version;
5575
5580
5584 NvU8 rsvd[64];
5585
5588 NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_V1 devices[NV_GPU_CLIENT_ILLUM_DEVICE_NUM_DEVICES_MAX];
5590
5591#define NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS_V1, 1)
5592#define NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS_VER NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS_VER_1
5594
5601//
5615NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesGetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS *pClientIllumDevicesControl);
5616
5623//
5637NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesSetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS *pClientIllumDevicesControl);
5638
5639
5640#define NV_GPU_CLIENT_ILLUM_ZONE_NUM_ZONES_MAX 32
5641
5646
5655
5664
5666{
5668
5673
5678
5683
5684 union
5685 {
5686 //
5687 // Need to be careful when add/expanding types in this union. If any type
5688 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
5689 //
5693
5697 NvU8 rsvd[64];
5698 } data;
5699
5700 NvU8 rsvd[64];
5702
5704{
5708 NvU32 version;
5709
5714
5718 NvU8 rsvd[64];
5719 NV_GPU_CLIENT_ILLUM_ZONE_INFO_V1 zones[NV_GPU_CLIENT_ILLUM_ZONE_NUM_ZONES_MAX];
5721
5722#define NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS_V1, 1)
5723#define NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS_VER NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS_VER_1
5725
5732//
5746NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesGetInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS *pIllumZonesInfo);
5747
5748
5776
5790
5838
5854
5861{
5866 union
5867 {
5868 //
5869 // Need to be careful when add/expanding types in this union. If any type
5870 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
5871 //
5874
5878 NvU8 rsvd[64];
5880
5884 NvU8 rsvd[64];
5886
5899
5913
5929
5936{
5941 union
5942 {
5943 //
5944 // Need to be careful when add/expanding types in this union. If any type
5945 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
5946 //
5952 NvU8 rsvd[64];
5954
5958 NvU8 rsvd[64];
5960
5993
6007
6023
6030{
6035 union
6036 {
6037 //
6038 // Need to be careful when add/expanding types in this union. If any type
6039 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
6040 //
6046 NvU8 rsvd[64];
6048
6052 NvU8 rsvd[64];
6054
6067
6081
6097
6104{
6109 union
6110 {
6111 //
6112 // Need to be careful when add/expanding types in this union. If any type
6113 // exceeds sizeof(rsvd) then rsvd has failed its purpose.
6114 //
6120 NvU8 rsvd[64];
6122
6126 NvU8 rsvd[64];
6128
6143
6145{
6146 NvU32 version;
6147
6153 NvU32 bDefault : 1;
6154 NvU32 rsvdField : 31;
6155
6160
6164 NvU8 rsvd[64];
6165
6166 NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_V1 zones[NV_GPU_CLIENT_ILLUM_ZONE_NUM_ZONES_MAX];
6168
6169#define NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS_V1, 1)
6170#define NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS_VER NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS_VER_1
6172
6179//
6193NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesGetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS *pIllumZonesControl);
6194
6201//
6215NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesSetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS *pIllumZonesControl);
6216
6218//
6219// FUNCTION NAME: NvAPI_Event_RegisterCallback
6220//
6240 NvEventHandle* phClient);
6241
6243//
6244// FUNCTION NAME: NvAPI_Event_UnregisterCallback
6245//
6263NVAPI_INTERFACE NvAPI_Event_UnregisterCallback(NvEventHandle hClient);
6265//
6266// FUNCTION NAME: NvAPI_EnumNvidiaDisplayHandle
6267//
6289NVAPI_INTERFACE NvAPI_EnumNvidiaDisplayHandle(NvU32 thisEnum, NvDisplayHandle *pNvDispHandle);
6290
6291
6292
6293
6294
6296//
6297// FUNCTION NAME: NvAPI_EnumNvidiaUnAttachedDisplayHandle
6298//
6319NVAPI_INTERFACE NvAPI_EnumNvidiaUnAttachedDisplayHandle(NvU32 thisEnum, NvUnAttachedDisplayHandle *pNvUnAttachedDispHandle);
6320
6321
6322
6324//
6325// FUNCTION NAME: NvAPI_CreateDisplayFromUnAttachedDisplay
6326//
6341NVAPI_INTERFACE NvAPI_CreateDisplayFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvDisplayHandle *pNvDisplay);
6342
6344//
6345// FUNCTION NAME: NvAPI_GetAssociatedNVidiaDisplayHandle
6346//
6360NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayHandle(const char *szDisplayName, NvDisplayHandle *pNvDispHandle);
6361
6362
6364//
6365// FUNCTION NAME: NvAPI_DISP_GetAssociatedUnAttachedNvidiaDisplayHandle
6366//
6381NVAPI_INTERFACE NvAPI_DISP_GetAssociatedUnAttachedNvidiaDisplayHandle(const char *szDisplayName, NvUnAttachedDisplayHandle *pNvUnAttachedDispHandle);
6382
6383
6384
6386//
6387// FUNCTION NAME: NvAPI_GetAssociatedNVidiaDisplayName
6388//
6401NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayName(NvDisplayHandle NvDispHandle, NvAPI_ShortString szDisplayName);
6402
6404//
6405// FUNCTION NAME: NvAPI_GetUnAttachedAssociatedDisplayName
6406//
6419NVAPI_INTERFACE NvAPI_GetUnAttachedAssociatedDisplayName(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvAPI_ShortString szDisplayName);
6420
6421
6423//
6424// FUNCTION NAME: NvAPI_EnableHWCursor
6425//
6437NVAPI_INTERFACE NvAPI_EnableHWCursor(NvDisplayHandle hNvDisplay);
6438
6440//
6441// FUNCTION NAME: NvAPI_DisableHWCursor
6442//
6453NVAPI_INTERFACE NvAPI_DisableHWCursor(NvDisplayHandle hNvDisplay);
6454
6456//
6457// FUNCTION NAME: NvAPI_GetVBlankCounter
6458//
6469NVAPI_INTERFACE NvAPI_GetVBlankCounter(NvDisplayHandle hNvDisplay, NvU32 *pCounter);
6470
6472// FUNCTION NAME: NvAPI_SetRefreshRateOverride
6473//
6499NVAPI_INTERFACE NvAPI_SetRefreshRateOverride(NvDisplayHandle hNvDisplay, NvU32 outputsMask, float refreshRate, NvU32 bSetDeferred);
6500
6502//
6503// FUNCTION NAME: NvAPI_GetAssociatedDisplayOutputId
6504//
6522NVAPI_INTERFACE NvAPI_GetAssociatedDisplayOutputId(NvDisplayHandle hNvDisplay, NvU32 *pOutputId);
6523
6524
6528{
6529 NvU32 version;
6530 NvU32 dpcd_ver;
6539 NvU32 isDp : 1;
6540 NvU32 isInternalDp : 1;
6554 NvU32 is6BPCSupportedOnCurrentMode : 1; // if 6 bpc is supported On Current Mode
6555 NvU32 is8BPCSupportedOnCurrentMode : 1; // if 8 bpc is supported On Current Mode
6556 NvU32 is10BPCSupportedOnCurrentMode : 1; // if 10 bpc is supported On Current Mode
6557 NvU32 is12BPCSupportedOnCurrentMode : 1; // if 12 bpc is supported On Current Mode
6558 NvU32 is16BPCSupportedOnCurrentMode : 1; // if 16 bpc is supported On Current Mode
6559 NvU32 isMonxvYCC601Capable : 1; // if xvYCC 601 extended colorimetry is supported
6560 NvU32 isMonxvYCC709Capable : 1; // if xvYCC 709 extended colorimetry is supported
6561 NvU32 isMonsYCC601Capable : 1; // if sYCC601 extended colorimetry is supported
6562 NvU32 isMonAdobeYCC601Capable : 1; // if AdobeYCC601 extended colorimetry is supported
6563 NvU32 isMonAdobeRGBCapable : 1; // if AdobeRGB extended colorimetry is supported
6564 NvU32 isMonBT2020RGBCapable : 1; // if BT2020 RGB extended colorimetry is supported
6565 NvU32 isMonBT2020YCCCapable : 1; // if BT2020 Y'CbCr extended colorimetry is supported
6566 NvU32 isMonBT2020cYCCCapable : 1; // if BT2020 cYCbCr (constant luminance) extended colorimetry is supported
6567
6568 NvU32 reserved : 4;
6570
6572
6574#define NV_DISPLAY_PORT_INFO_VER1 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_INFO,1)
6575#define NV_DISPLAY_PORT_INFO_VER2 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_INFO,2)
6576#define NV_DISPLAY_PORT_INFO_VER NV_DISPLAY_PORT_INFO_VER2
6577
6579// FUNCTION NAME: NvAPI_GetDisplayPortInfo
6580//
6599//
6602NVAPI_INTERFACE NvAPI_GetDisplayPortInfo(__in_opt NvDisplayHandle hNvDisplay, __in NvU32 outputId, __inout NV_DISPLAY_PORT_INFO *pInfo);
6603
6605// FUNCTION NAME: NvAPI_SetDisplayPort
6606//
6625
6626
6646
6650#define NV_DISPLAY_PORT_CONFIG_VER MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,2)
6652#define NV_DISPLAY_PORT_CONFIG_VER_1 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,1)
6654#define NV_DISPLAY_PORT_CONFIG_VER_2 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,2)
6656
6657
6659NVAPI_INTERFACE NvAPI_SetDisplayPort(NvDisplayHandle hNvDisplay, NvU32 outputId, NV_DISPLAY_PORT_CONFIG *pCfg);
6660
6661
6662
6663
6682
6702
6703#define NV_HDMI_SUPPORT_INFO_VER1 MAKE_NVAPI_VERSION(NV_HDMI_SUPPORT_INFO_V1, 1)
6704#define NV_HDMI_SUPPORT_INFO_VER2 MAKE_NVAPI_VERSION(NV_HDMI_SUPPORT_INFO_V2, 2)
6705
6706
6707
6708#ifndef NV_HDMI_SUPPORT_INFO_VER
6709
6711#define NV_HDMI_SUPPORT_INFO_VER NV_HDMI_SUPPORT_INFO_VER2
6712
6713#endif
6714
6715
6719// FUNCTION NAME: NvAPI_GetHDMISupportInfo
6720//
6737
6738
6740NVAPI_INTERFACE NvAPI_GetHDMISupportInfo(__in_opt NvDisplayHandle hNvDisplay, __in NvU32 outputId, __inout NV_HDMI_SUPPORT_INFO *pInfo);
6741
6742
6744
6756
6757
6765
6766
6768typedef enum
6769{
6770 NV_INFOFRAME_PROPERTY_BLACKLIST_FALSE = 0,
6771 NV_INFOFRAME_PROPERTY_BLACKLIST_TRUE,
6773
6774typedef struct
6775{
6776 NvU32 mode : 4;
6777 NvU32 blackList : 2;
6778 NvU32 reserved : 10;
6779 NvU32 version : 8;
6780 NvU32 length : 8;
6782
6784typedef enum
6785{
6786 NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO_NODATA = 0,
6787 NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO_OVERSCAN,
6788 NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO_UNDERSCAN,
6789 NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO_FUTURE,
6790 NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO_AUTO = 7
6792
6793
6794typedef enum
6795{
6796 NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA_NOT_PRESENT = 0,
6797 NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA_VERTICAL_PRESENT,
6798 NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA_HORIZONTAL_PRESENT,
6799 NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA_BOTH_PRESENT,
6800 NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA_AUTO = 7
6801} NV_INFOFRAME_FIELD_VALUE_AVI_BARDATA;
6802
6803typedef enum
6804{
6805 NV_INFOFRAME_FIELD_VALUE_AVI_AFI_ABSENT = 0,
6806 NV_INFOFRAME_FIELD_VALUE_AVI_AFI_PRESENT,
6807 NV_INFOFRAME_FIELD_VALUE_AVI_AFI_AUTO = 3
6808} NV_INFOFRAME_FIELD_VALUE_AVI_ACTIVEFORMATINFO;
6809
6810
6811typedef enum
6812{
6813 NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT_RGB = 0,
6814 NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT_YCbCr422,
6815 NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT_YCbCr444,
6816 NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT_FUTURE,
6817 NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT_AUTO = 7
6818} NV_INFOFRAME_FIELD_VALUE_AVI_COLORFORMAT;
6819
6820typedef enum
6821{
6822 NV_INFOFRAME_FIELD_VALUE_AVI_F17_FALSE = 0,
6823 NV_INFOFRAME_FIELD_VALUE_AVI_F17_TRUE,
6824 NV_INFOFRAME_FIELD_VALUE_AVI_F17_AUTO = 3
6825} NV_INFOFRAME_FIELD_VALUE_AVI_F17;
6826
6828typedef enum
6829{
6830 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_NO_AFD = 0,
6831 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE01,
6832 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE02,
6833 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE03,
6834 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_LETTERBOX_GT16x9,
6835 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE05,
6836 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE06,
6837 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE07,
6838 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_EQUAL_CODEDFRAME = 8,
6839 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_CENTER_4x3,
6840 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_CENTER_16x9,
6841 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_CENTER_14x9,
6842 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_RESERVE12,
6843 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_4x3_ON_14x9,
6844 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_16x9_ON_14x9,
6845 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_16x9_ON_4x3,
6846 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION_AUTO = 31,
6848
6849
6850typedef enum
6851{
6852 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME_NO_DATA = 0,
6853 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME_4x3,
6854 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME_16x9,
6855 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME_FUTURE,
6856 NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME_AUTO = 7
6857} NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOCODEDFRAME;
6858
6859typedef enum
6860{
6861 NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY_NO_DATA = 0,
6862 NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY_SMPTE_170M,
6863 NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY_ITUR_BT709,
6864 NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY_USE_EXTENDED_COLORIMETRY,
6865 NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY_AUTO = 7
6866} NV_INFOFRAME_FIELD_VALUE_AVI_COLORIMETRY;
6867
6869typedef enum
6870{
6871 NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING_NO_DATA = 0,
6872 NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING_HORIZONTAL,
6873 NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING_VERTICAL,
6874 NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING_BOTH,
6875 NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING_AUTO = 7
6877
6878typedef enum
6879{
6880 NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION_DEFAULT = 0,
6881 NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION_LIMITED_RANGE,
6882 NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION_FULL_RANGE,
6883 NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION_RESERVED,
6884 NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION_AUTO = 7
6885} NV_INFOFRAME_FIELD_VALUE_AVI_RGBQUANTIZATION;
6886
6887typedef enum
6888{
6889 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_XVYCC601 = 0,
6890 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_XVYCC709,
6891 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_SYCC601,
6892 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_ADOBEYCC601,
6893 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_ADOBERGB,
6894 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_RESERVED05,
6895 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_RESERVED06,
6896 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_RESERVED07,
6897 NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY_AUTO = 15
6898} NV_INFOFRAME_FIELD_VALUE_AVI_EXTENDEDCOLORIMETRY;
6899
6900typedef enum
6901{
6902 NV_INFOFRAME_FIELD_VALUE_AVI_ITC_VIDEO_CONTENT = 0,
6903 NV_INFOFRAME_FIELD_VALUE_AVI_ITC_ITCONTENT,
6904 NV_INFOFRAME_FIELD_VALUE_AVI_ITC_AUTO = 3
6905} NV_INFOFRAME_FIELD_VALUE_AVI_ITC;
6906
6908typedef enum
6909{
6910 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_NONE = 0,
6911 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X02,
6912 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X03,
6913 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X04,
6914 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X05,
6915 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X06,
6916 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X07,
6917 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X08,
6918 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X09,
6919 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_X10,
6920 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED10,
6921 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED11,
6922 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED12,
6923 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED13,
6924 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED14,
6925 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_RESERVED15,
6926 NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION_AUTO = 31
6928
6929
6930typedef enum
6931{
6932 NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE_GRAPHICS = 0,
6933 NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE_PHOTO,
6934 NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE_CINEMA,
6935 NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE_GAME,
6936 NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE_AUTO = 7
6937} NV_INFOFRAME_FIELD_VALUE_AVI_CONTENTTYPE;
6938
6939typedef enum
6940{
6941 NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION_LIMITED_RANGE = 0,
6942 NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION_FULL_RANGE,
6943 NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION_RESERVED02,
6944 NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION_RESERVED03,
6945 NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION_AUTO = 7
6946} NV_INFOFRAME_FIELD_VALUE_AVI_YCCQUANTIZATION;
6947
6949typedef struct
6950{
6951 NvU32 vic : 8;
6952 NvU32 pixelRepeat : 5;
6953 NvU32 colorSpace : 3;
6954 NvU32 colorimetry : 3;
6955 NvU32 extendedColorimetry : 4;
6956 NvU32 rgbQuantizationRange : 3;
6957 NvU32 yccQuantizationRange : 3;
6958 NvU32 itContent : 2;
6959 NvU32 contentTypes : 3;
6960 NvU32 scanInfo : 3;
6961 NvU32 activeFormatInfoPresent : 2;
6962 NvU32 activeFormatAspectRatio : 5;
6963 NvU32 picAspectRatio : 3;
6964 NvU32 nonuniformScaling : 3;
6965 NvU32 barInfo : 3;
6966 NvU32 top_bar : 17;
6967 NvU32 bottom_bar : 17;
6968 NvU32 left_bar : 17;
6969 NvU32 right_bar : 17;
6970 NvU32 Future17 : 2;
6971 NvU32 Future47 : 2;
6973
6975typedef enum
6976{
6977 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_IN_HEADER = 0,
6978 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_2,
6979 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_3,
6980 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_4,
6981 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_5,
6982 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_6,
6983 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_7,
6984 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_8,
6985 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT_AUTO = 15
6987
6988typedef enum
6989{
6990 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_IN_HEADER = 0,
6991 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_PCM,
6992 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_AC3,
6993 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_MPEG1,
6994 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_MP3,
6995 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_MPEG2,
6996 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_AACLC,
6997 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_DTS,
6998 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_ATRAC,
6999 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_DSD,
7000 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_EAC3,
7001 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_DTSHD,
7002 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_MLP,
7003 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_DST,
7004 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_WMAPRO,
7005 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_USE_CODING_EXTENSION_TYPE,
7006 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE_AUTO = 31
7007} NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGTYPE;
7008
7010typedef enum
7011{
7012 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE_IN_HEADER = 0,
7013 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE_16BITS,
7014 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE_20BITS,
7015 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE_24BITS,
7016 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE_AUTO = 7
7018
7019typedef enum
7020{
7021 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_IN_HEADER = 0,
7022 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_32000HZ,
7023 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_44100HZ,
7024 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_48000HZ,
7025 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_88200KHZ,
7026 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_96000KHZ,
7027 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_176400KHZ,
7028 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_192000KHZ,
7029 NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY_AUTO = 15
7030} NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLEFREQUENCY;
7031
7032
7033
7035typedef enum
7036{
7037 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_USE_CODING_TYPE = 0,
7038 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_HEAAC,
7039 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_HEAACV2,
7040 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_MPEGSURROUND,
7041 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE04,
7042 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE05,
7043 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE06,
7044 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE07,
7045 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE08,
7046 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE09,
7047 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE10,
7048 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE11,
7049 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE12,
7050 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE13,
7051 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE14,
7052 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE15,
7053 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE16,
7054 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE17,
7055 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE18,
7056 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE19,
7057 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE20,
7058 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE21,
7059 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE22,
7060 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE23,
7061 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE24,
7062 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE25,
7063 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE26,
7064 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE27,
7065 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE28,
7066 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE29,
7067 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE30,
7068 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_RESERVE31,
7069 NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE_AUTO = 63
7071
7072
7074typedef enum
7075{
7076 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_X_X_X_FR_FL =0,
7077 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_X_X_LFE_FR_FL,
7078 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_X_FC_X_FR_FL,
7079 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_X_FC_LFE_FR_FL,
7080 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_RC_X_X_FR_FL,
7081 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_RC_X_LFE_FR_FL,
7082 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_RC_FC_X_FR_FL,
7083 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_X_RC_FC_LFE_FR_FL,
7084 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_RR_RL_X_X_FR_FL,
7085 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_RR_RL_X_LFE_FR_FL,
7086 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_RR_RL_FC_X_FR_FL,
7087 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_X_RR_RL_FC_LFE_FR_FL,
7088 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_RC_RR_RL_X_X_FR_FL,
7089 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_RC_RR_RL_X_LFE_FR_FL,
7090 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_RC_RR_RL_FC_X_FR_FL,
7091 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_RC_RR_RL_FC_LFE_FR_FL,
7092 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_RRC_RLC_RR_RL_X_X_FR_FL,
7093 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_RRC_RLC_RR_RL_X_LFE_FR_FL,
7094 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_RRC_RLC_RR_RL_FC_X_FR_FL,
7095 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_RRC_RLC_RR_RL_FC_LFE_FR_FL,
7096 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_X_X_X_FR_FL,
7097 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_X_X_LFE_FR_FL,
7098 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_X_FC_X_FR_FL,
7099 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_X_FC_LFE_FR_FL,
7100 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_RC_X_X_FR_FL,
7101 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_RC_X_LFE_FR_FL,
7102 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_RC_FC_X_FR_FL,
7103 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_X_RC_FC_LFE_FR_FL,
7104 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_RR_RL_X_X_FR_FL,
7105 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_RR_RL_X_LFE_FR_FL,
7106 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_RR_RL_FC_X_FR_FL,
7107 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRC_FLC_RR_RL_FC_LFE_FR_FL,
7108 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_FCH_RR_RL_FC_X_FR_FL,
7109 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_X_FCH_RR_RL_FC_LFE_FR_FL,
7110 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_X_RR_RL_FC_X_FR_FL,
7111 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_X_RR_RL_FC_LFE_FR_FL,
7112 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRH_FLH_RR_RL_X_X_FR_FL,
7113 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRH_FLH_RR_RL_X_LFE_FR_FL,
7114 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRW_FLW_RR_RL_X_X_FR_FL,
7115 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRW_FLW_RR_RL_X_LFE_FR_FL,
7116 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_RC_RR_RL_FC_X_FR_FL,
7117 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_RC_RR_RL_FC_LFE_FR_FL,
7118 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FCH_RC_RR_RL_FC_X_FR_FL,
7119 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FCH_RC_RR_RL_FC_LFE_FR_FL,
7120 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_FCH_RR_RL_FC_X_FR_FL,
7121 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_TC_FCH_RR_RL_FC_LFE_FR_FL,
7122 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRH_FLH_RR_RL_FC_X_FR_FL,
7123 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRH_FLH_RR_RL_FC_LFE_FR_FL,
7124 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRW_FLW_RR_RL_FC_X_FR_FL,
7125 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_FRW_FLW_RR_RL_FC_LFE_FR_FL = 0X31,
7126 // all other values should default to auto
7127 NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION_AUTO = 0x1FF
7129
7131typedef enum
7132{
7133 NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL_NO_DATA = 0,
7134 NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL_0DB,
7135 NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL_PLUS10DB,
7136 NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL_RESERVED03,
7137 NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL_AUTO = 7
7139
7140typedef enum
7141{
7142 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_0DB = 0,
7143 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_1DB,
7144 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_2DB,
7145 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_3DB,
7146 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_4DB,
7147 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_5DB,
7148 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_6DB,
7149 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_7DB,
7150 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_8DB,
7151 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_9DB,
7152 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_10DB,
7153 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_11DB,
7154 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_12DB,
7155 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_13DB,
7156 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_14DB,
7157 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_15DB,
7158 NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES_AUTO = 31
7159} NV_INFOFRAME_FIELD_VALUE_AUDIO_LEVELSHIFTVALUES;
7160
7161
7162typedef enum
7163{
7164 NV_INFOFRAME_FIELD_VALUE_AUDIO_DOWNMIX_PERMITTED = 0,
7165 NV_INFOFRAME_FIELD_VALUE_AUDIO_DOWNMIX_PROHIBITED,
7166 NV_INFOFRAME_FIELD_VALUE_AUDIO_DOWNMIX_AUTO = 3
7167} NV_INFOFRAME_FIELD_VALUE_AUDIO_DOWNMIX;
7168
7169typedef struct
7170{
7171 NvU32 codingType : 5;
7172 NvU32 codingExtensionType : 6;
7173 NvU32 sampleSize : 3;
7174 NvU32 sampleRate : 4;
7175 NvU32 channelCount : 4;
7176 NvU32 speakerPlacement : 9;
7177 NvU32 downmixInhibit : 2;
7178 NvU32 lfePlaybackLevel : 3;
7179 NvU32 levelShift : 5;
7180 NvU32 Future12 : 2;
7181 NvU32 Future2x : 4;
7182 NvU32 Future3x : 4;
7183 NvU32 Future52 : 2;
7184 NvU32 Future6 : 9;
7185 NvU32 Future7 : 9;
7186 NvU32 Future8 : 9;
7187 NvU32 Future9 : 9;
7188 NvU32 Future10 : 9;
7190
7191typedef struct
7192{
7193 NvU32 version;
7194 NvU16 size;
7195 NvU8 cmd;
7196 NvU8 type;
7197
7198 union
7199 {
7201 NV_INFOFRAME_AUDIO audio;
7202 NV_INFOFRAME_VIDEO video;
7203 } infoframe;
7205
7207#define NV_INFOFRAME_DATA_VER MAKE_NVAPI_VERSION(NV_INFOFRAME_DATA,1)
7208
7210// FUNCTION NAME: NvAPI_Disp_InfoFrameControl
7211//
7225NVAPI_INTERFACE NvAPI_Disp_InfoFrameControl(__in NvU32 displayId, __inout NV_INFOFRAME_DATA *pInfoframeData);
7226
7227
7228
7229
7230
7231
7235// FUNCTION NAME: NvAPI_Disp_ColorControl
7236//
7250//
7252
7253typedef enum
7254{
7255 NV_COLOR_CMD_GET = 1,
7256 NV_COLOR_CMD_SET,
7257 NV_COLOR_CMD_IS_SUPPORTED_COLOR,
7258 NV_COLOR_CMD_GET_DEFAULT
7259} NV_COLOR_CMD;
7260
7262typedef enum
7263{
7264 NV_COLOR_FORMAT_RGB = 0,
7265 NV_COLOR_FORMAT_YUV422,
7266 NV_COLOR_FORMAT_YUV444,
7267 NV_COLOR_FORMAT_YUV420,
7268
7269 NV_COLOR_FORMAT_DEFAULT = 0xFE,
7270 NV_COLOR_FORMAT_AUTO = 0xFF
7272
7273
7274
7275typedef enum
7276{
7277 NV_COLOR_COLORIMETRY_RGB = 0,
7278 NV_COLOR_COLORIMETRY_YCC601,
7279 NV_COLOR_COLORIMETRY_YCC709,
7280 NV_COLOR_COLORIMETRY_XVYCC601,
7281 NV_COLOR_COLORIMETRY_XVYCC709,
7282 NV_COLOR_COLORIMETRY_SYCC601,
7283 NV_COLOR_COLORIMETRY_ADOBEYCC601,
7284 NV_COLOR_COLORIMETRY_ADOBERGB,
7285 NV_COLOR_COLORIMETRY_BT2020RGB,
7286 NV_COLOR_COLORIMETRY_BT2020YCC,
7287 NV_COLOR_COLORIMETRY_BT2020cYCC,
7288
7289 NV_COLOR_COLORIMETRY_DEFAULT = 0xFE,
7290 NV_COLOR_COLORIMETRY_AUTO = 0xFF
7291} NV_COLOR_COLORIMETRY;
7292
7293typedef enum _NV_DYNAMIC_RANGE
7294{
7295 NV_DYNAMIC_RANGE_VESA = 0x0,
7296 NV_DYNAMIC_RANGE_CEA = 0x1,
7297
7298 NV_DYNAMIC_RANGE_AUTO = 0xFF
7299} NV_DYNAMIC_RANGE;
7300
7301typedef enum _NV_BPC
7302{
7303 NV_BPC_DEFAULT = 0,
7304 NV_BPC_6 = 1,
7305 NV_BPC_8 = 2,
7306 NV_BPC_10 = 3,
7307 NV_BPC_12 = 4,
7308 NV_BPC_16 = 5,
7309} NV_BPC;
7310
7312{
7315 NV_COLOR_SELECTION_POLICY_DEFAULT = NV_COLOR_SELECTION_POLICY_BEST_QUALITY,
7316 NV_COLOR_SELECTION_POLICY_UNKNOWN = 0xFF,
7317} NV_COLOR_SELECTION_POLICY;
7318
7319typedef enum _NV_DESKTOP_COLOR_DEPTH
7320{
7321 NV_DESKTOP_COLOR_DEPTH_DEFAULT = 0x0, // set if the current setting should be kept
7322 NV_DESKTOP_COLOR_DEPTH_8BPC = 0x1, //8 bit int per color component (8 bit int alpha)
7323 NV_DESKTOP_COLOR_DEPTH_10BPC = 0x2, //10 bit int per color component (2 bit int alpha)
7324 NV_DESKTOP_COLOR_DEPTH_16BPC_FLOAT = 0x3, //16 bit float per color component (16 bit float alpha)
7325 NV_DESKTOP_COLOR_DEPTH_16BPC_FLOAT_WCG = 0x4, //16 bit float per color component (16 bit float alpha) wide color gamut
7326 NV_DESKTOP_COLOR_DEPTH_16BPC_FLOAT_HDR = 0x5, //16 bit float per color component (16 bit float alpha) HDR
7327 NV_DESKTOP_COLOR_DEPTH_MAX_VALUE = NV_DESKTOP_COLOR_DEPTH_16BPC_FLOAT_HDR, // must be set to highest enum value
7328} NV_DESKTOP_COLOR_DEPTH;
7329
7330typedef struct _NV_COLOR_DATA_V1
7331{
7332 NvU32 version;
7333 NvU16 size;
7334 NvU8 cmd;
7335 struct
7336 {
7339 } data;
7341
7342typedef struct _NV_COLOR_DATA_V2
7343{
7344 NvU32 version;
7345 NvU16 size;
7346 NvU8 cmd;
7347 struct
7348 {
7352 } data;
7354
7355typedef struct _NV_COLOR_DATA_V3
7356{
7357 NvU32 version;
7358 NvU16 size;
7359 NvU8 cmd;
7360 struct
7361 {
7365 NV_BPC bpc;
7366 } data;
7368
7369typedef struct _NV_COLOR_DATA_V4
7370{
7371 NvU32 version;
7372 NvU16 size;
7373 NvU8 cmd;
7374 struct
7375 {
7379 NV_BPC bpc;
7380 NV_COLOR_SELECTION_POLICY colorSelectionPolicy;
7381 } data;
7383
7384typedef struct _NV_COLOR_DATA_V5
7385{
7386 NvU32 version;
7387 NvU16 size;
7388 NvU8 cmd;
7389 struct
7390 {
7394 NV_BPC bpc;
7395 NV_COLOR_SELECTION_POLICY colorSelectionPolicy;
7396 NV_DESKTOP_COLOR_DEPTH depth;
7397 } data;
7399
7401
7402#define NV_COLOR_DATA_VER1 MAKE_NVAPI_VERSION(NV_COLOR_DATA_V1, 1)
7403#define NV_COLOR_DATA_VER2 MAKE_NVAPI_VERSION(NV_COLOR_DATA_V2, 2)
7404#define NV_COLOR_DATA_VER3 MAKE_NVAPI_VERSION(NV_COLOR_DATA_V3, 3)
7405#define NV_COLOR_DATA_VER4 MAKE_NVAPI_VERSION(NV_COLOR_DATA_V4, 4)
7406#define NV_COLOR_DATA_VER5 MAKE_NVAPI_VERSION(NV_COLOR_DATA_V5, 5)
7407#define NV_COLOR_DATA_VER NV_COLOR_DATA_VER5
7408
7409NVAPI_INTERFACE NvAPI_Disp_ColorControl(NvU32 displayId, NV_COLOR_DATA *pColorData);
7410
7412
7413
7418
7452
7454{
7455 NvU32 version;
7456
7464 NvU32 reserved :26;
7465
7467
7468 struct
7469 {
7472
7475
7478
7481
7485 }display_data;
7486
7487 struct
7488 {
7489 NvU32 VSVDB_version : 3;
7490 NvU32 dm_version : 8;
7494 NvU32 colorimetry : 1;
7499 NvU32 reserved : 9;
7503 NvU16 cc_red_x;
7504 NvU16 cc_red_y;
7511 }dv_static_metadata;
7512
7514
7516{
7517 NvU32 version;
7518
7528 NvU32 reserved :24;
7529
7531
7532 struct
7533 {
7536
7539
7542
7545
7549 }display_data;
7550
7551 struct
7552 {
7553 NvU32 VSVDB_version : 3;
7554 NvU32 dm_version : 8;
7558 NvU32 colorimetry : 1;
7563 NvU32 parity : 1;
7564 NvU32 reserved : 8;
7565
7569 NvU16 cc_red_x;
7570 NvU16 cc_red_y;
7577 }dv_static_metadata;
7578
7579 struct
7580 {
7584 NvU16 reserved : 8;
7585 }hdr10plus_vsvdb;
7586
7588
7589#define NV_HDR_CAPABILITIES_VER1 MAKE_NVAPI_VERSION(NV_HDR_CAPABILITIES_V1, 1)
7590#define NV_HDR_CAPABILITIES_VER2 MAKE_NVAPI_VERSION(NV_HDR_CAPABILITIES_V2, 2)
7591#define NV_HDR_CAPABILITIES_VER3 MAKE_NVAPI_VERSION(NV_HDR_CAPABILITIES_V3, 3)
7592#define NV_HDR_CAPABILITIES_VER NV_HDR_CAPABILITIES_VER3
7594
7598// FUNCTION NAME: NvAPI_Disp_GetHdrCapabilities
7599//
7611//
7613NVAPI_INTERFACE NvAPI_Disp_GetHdrCapabilities(__in NvU32 displayId, __inout NV_HDR_CAPABILITIES *pHdrCapabilities);
7614
7616
7617
7618typedef enum
7619{
7621 NV_HDR_CMD_SET = 1
7623
7624typedef enum
7625{
7626 // Official production-ready HDR modes
7629
7630 // Experimental
7633
7634 // Unsupported/obsolete HDR modes
7639
7641
7670
7706
7707#define NV_HDR_COLOR_DATA_VER1 MAKE_NVAPI_VERSION(NV_HDR_COLOR_DATA_V1, 1)
7708#define NV_HDR_COLOR_DATA_VER2 MAKE_NVAPI_VERSION(NV_HDR_COLOR_DATA_V2, 2)
7709
7710#ifndef NV_HDR_COLOR_DATA_VER
7711#define NV_HDR_COLOR_DATA_VER NV_HDR_COLOR_DATA_VER2
7713#endif
7714
7718// FUNCTION NAME: NvAPI_Disp_HdrColorControl
7719//
7731//
7733NVAPI_INTERFACE NvAPI_Disp_HdrColorControl(__in NvU32 displayId, __inout NV_HDR_COLOR_DATA *pHdrColorData);
7734
7736{
7740} NV_COLORSPACE_TYPE;
7741
7743// FUNCTION NAME: NvAPI_Disp_SetSourceColorSpace
7744//
7758//
7760NVAPI_INTERFACE NvAPI_Disp_SetSourceColorSpace(__in NvU32 displayId, __in NV_COLORSPACE_TYPE colorSpaceType);
7761
7762#define NV_SOURCE_PID_CURRENT 0
7763
7765// FUNCTION NAME: NvAPI_Disp_GetSourceColorSpace
7766//
7781//
7783NVAPI_INTERFACE NvAPI_Disp_GetSourceColorSpace(__in NvU32 displayId, __inout NV_COLORSPACE_TYPE* pColorSpaceType, NvU64 sourcePID);
7784
7807
7808#define NV_HDR_METADATA_VER1 MAKE_NVAPI_VERSION(NV_HDR_METADATA_V1, 1)
7809#define NV_HDR_METADATA_VER NV_HDR_METADATA_VER1
7811
7813// FUNCTION NAME: NvAPI_Disp_SetSourceHdrMetadata
7814//
7828//
7830NVAPI_INTERFACE NvAPI_Disp_SetSourceHdrMetadata(__in NvU32 displayId, __in NV_HDR_METADATA* pMetadata);
7831
7833// FUNCTION NAME: NvAPI_Disp_GetSourceHdrMetadata
7834//
7849//
7851NVAPI_INTERFACE NvAPI_Disp_GetSourceHdrMetadata(__in NvU32 displayId, __inout NV_HDR_METADATA* pMetadata, NvU64 sourcePID);
7852
7853typedef enum _NV_DISPLAY_OUTPUT_MODE
7854{
7855 NV_DISPLAY_OUTPUT_MODE_SDR = 0,
7856 NV_DISPLAY_OUTPUT_MODE_HDR10 = 1,
7857 NV_DISPLAY_OUTPUT_MODE_HDR10PLUS_GAMING = 2
7858} NV_DISPLAY_OUTPUT_MODE;
7859
7861// FUNCTION NAME: NvAPI_Disp_SetOutputMode
7862//
7879//
7881NVAPI_INTERFACE NvAPI_Disp_SetOutputMode(__in NvU32 displayId, __inout NV_DISPLAY_OUTPUT_MODE* pDisplayMode);
7882
7884// FUNCTION NAME: NvAPI_Disp_GetOutputMode
7885//
7899//
7901NVAPI_INTERFACE NvAPI_Disp_GetOutputMode(__in NvU32 displayId, __inout NV_DISPLAY_OUTPUT_MODE* pDisplayMode);
7902
7903typedef enum _NV_HDR_TONEMAPPING_METHOD
7904{
7905 NV_HDR_TONEMAPPING_APP = 0,
7906 NV_HDR_TONEMAPPING_GPU = 1
7907} NV_HDR_TONEMAPPING_METHOD;
7908
7910// FUNCTION NAME: NvAPI_Disp_SetHdrToneMapping
7911//
7925//
7927NVAPI_INTERFACE NvAPI_Disp_SetHdrToneMapping(__in NvU32 displayId, __in NV_HDR_TONEMAPPING_METHOD hdrTonemapping);
7928
7930// FUNCTION NAME: NvAPI_Disp_GetHdrToneMapping
7931//
7945//
7947NVAPI_INTERFACE NvAPI_Disp_GetHdrToneMapping(__in NvU32 displayId, __inout NV_HDR_TONEMAPPING_METHOD* pHdrTonemapping);
7949
7952typedef struct
7953{
7954 NvU32 isInterlaced : 4;
7955 NvU32 reserved0 : 12;
7956 union
7957 {
7958 NvU32 tvFormat : 8;
7960 NvU32 ceaId : 8;
7963 NvU32 nvPsfId : 8;
7965 };
7966 NvU32 scaling : 8;
7968
7983
7984#define NV_TIMING_INPUT_VER MAKE_NVAPI_VERSION(NV_TIMING_INPUT,1)
7985
7987// FUNCTION NAME: NvAPI_DISP_GetTiming
7988//
8006NVAPI_INTERFACE NvAPI_DISP_GetTiming( __in NvU32 displayId,__in NV_TIMING_INPUT *timingInput, __out NV_TIMING *pTiming);
8007
8008
8009
8011// FUNCTION NAME: NvAPI_DISP_GetMonitorCapabilities
8012//
8025//
8027
8030
8031
8033typedef enum
8034{
8035 // hdmi related caps
8036 NV_MONITOR_CAPS_TYPE_HDMI_VSDB = 0x1000,
8037 NV_MONITOR_CAPS_TYPE_HDMI_VCDB = 0x1001,
8038 // backend caps
8039 NV_MONITOR_CAPS_TYPE_GENERIC = 0x1002,
8041
8042
8043
8045{
8046 NvU8 quantizationRangeYcc : 1;
8047 NvU8 quantizationRangeRgb : 1;
8048 NvU8 scanInfoPreferredVideoFormat : 2;
8049 NvU8 scanInfoITVideoFormats : 2;
8050 NvU8 scanInfoCEVideoFormats : 2;
8052
8053
8056{
8057 // byte 1
8060 // byte 2
8063 // byte 3
8065 NvU8 reserved6 : 2;
8070 NvU8 supportAI : 1;
8071 // byte 4
8073 // byte 5
8078 NvU8 reserved8 : 1;
8079 NvU8 hasVicEntries : 1;
8082 // byte 6
8084 // byte 7
8086 // byte 8
8088 // byte 9
8090 // byte 10
8091 NvU8 reserved13 : 7;
8092 NvU8 has3dEntries : 1;
8093 // byte 11
8094 NvU8 hdmi3dLength : 5;
8095 NvU8 hdmiVicLength : 3;
8096 // Remaining bytes
8097 NvU8 hdmi_vic[7];
8098 NvU8 hdmi_3d[31];
8100
8102{
8103 NvU8 supportVRR : 1;
8104 NvU8 supportULMB : 1;
8105 NvU8 isTrueGsync : 1;
8106 NvU8 isRLACapable : 1;
8108 NvU8 reserved : 3;
8110
8113{
8114 NvU32 version;
8115 NvU16 size;
8116 NvU32 infoType;
8118 NvU8 bIsValidInfo : 1;
8119 union {
8123 } data;
8125
8127
8129#define NV_MONITOR_CAPABILITIES_VER1 MAKE_NVAPI_VERSION(NV_MONITOR_CAPABILITIES_V1,1)
8130#define NV_MONITOR_CAPABILITIES_VER NV_MONITOR_CAPABILITIES_VER1
8131
8133
8137NVAPI_INTERFACE NvAPI_DISP_GetMonitorCapabilities(__in NvU32 displayId, __inout NV_MONITOR_CAPABILITIES *pMonitorCapabilities);
8138
8141{
8142 NvU32 version;
8143// We are only supporting DP monitors for now. We need to extend this to HDMI panels as well
8147
8149
8151#define NV_MONITOR_COLOR_CAPS_VER1 MAKE_NVAPI_VERSION(NV_MONITOR_COLOR_CAPS_V1,1)
8152#define NV_MONITOR_COLOR_CAPS_VER NV_MONITOR_COLOR_CAPS_VER1
8153
8155// FUNCTION NAME: NvAPI_DISP_GetMonitorColorCapabilities
8156//
8193NVAPI_INTERFACE NvAPI_DISP_GetMonitorColorCapabilities(__in NvU32 displayId, __inout_ecount_part_opt(*pColorCapsCount, *pColorCapsCount) NV_MONITOR_COLOR_CAPS *pMonitorColorCapabilities, __inout NvU32 *pColorCapsCount);
8194
8197typedef struct
8198{
8199 NvU32 version;
8200
8201 // the source mode information
8202 NvU32 width;
8203 NvU32 height;
8204 NvU32 depth;
8206
8208
8209 float xRatio;
8210 float yRatio;
8211
8213 NvU32 hwModeSetOnly : 1;
8214
8216
8219#define NV_CUSTOM_DISPLAY_VER MAKE_NVAPI_VERSION(NV_CUSTOM_DISPLAY,1)
8220
8222// FUNCTION NAME: NvAPI_DISP_EnumCustomDisplay
8223//
8242NVAPI_INTERFACE NvAPI_DISP_EnumCustomDisplay( __in NvU32 displayId, __in NvU32 index, __inout NV_CUSTOM_DISPLAY *pCustDisp);
8243
8245// FUNCTION NAME: NvAPI_DISP_TryCustomDisplay
8246//
8274NVAPI_INTERFACE NvAPI_DISP_TryCustomDisplay( __in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in_ecount(count) NV_CUSTOM_DISPLAY *pCustDisp);
8275
8277// FUNCTION NAME: NvAPI_DISP_DeleteCustomDisplay
8278//
8297NVAPI_INTERFACE NvAPI_DISP_DeleteCustomDisplay( __in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in NV_CUSTOM_DISPLAY *pCustDisp);
8298
8300// FUNCTION NAME: NvAPI_DISP_SaveCustomDisplay
8301//
8324NVAPI_INTERFACE NvAPI_DISP_SaveCustomDisplay( __in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in NvU32 isThisOutputIdOnly, __in NvU32 isThisMonitorIdOnly);
8325
8327// FUNCTION NAME: NvAPI_DISP_RevertCustomDisplayTrial
8328//
8348NVAPI_INTERFACE NvAPI_DISP_RevertCustomDisplayTrial( __in_ecount(count) NvU32* pDisplayIds, __in NvU32 count);
8349
8351// FUNCTION NAME: NvAPI_GetView
8352//
8375__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_DISP_GetDisplayConfig.")
8376NVAPI_INTERFACE NvAPI_GetView(NvDisplayHandle hNvDisplay, NV_VIEW_TARGET_INFO *pTargets, NvU32 *pTargetMaskCount, NV_TARGET_VIEW_MODE *pTargetView);
8377
8378
8379
8380
8381
8382
8383
8385// FUNCTION NAME: NvAPI_GetViewEx
8386//
8411__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_DISP_GetDisplayConfig.")
8412NVAPI_INTERFACE NvAPI_GetViewEx(NvDisplayHandle hNvDisplay, NV_DISPLAY_PATH_INFO *pPathInfo, NvU32 *pPathCount, NV_TARGET_VIEW_MODE *pTargetViewMode);
8413
8415// FUNCTION NAME: NvAPI_GetSupportedViews
8416//
8434NVAPI_INTERFACE NvAPI_GetSupportedViews(NvDisplayHandle hNvDisplay, NV_TARGET_VIEW_MODE *pTargetViews, NvU32 *pViewCount);
8435
8436
8440//
8441// FUNCTION NAME: NvAPI_DISP_GetDisplayIdByDisplayName
8442//
8460NVAPI_INTERFACE NvAPI_DISP_GetDisplayIdByDisplayName(const char *displayName, NvU32* displayId);
8461
8462
8463
8464
8466// FUNCTION NAME: NvAPI_DISP_GetDisplayConfig
8467//
8493NVAPI_INTERFACE NvAPI_DISP_GetDisplayConfig(__inout NvU32 *pathInfoCount, __out_ecount_full_opt(*pathInfoCount) NV_DISPLAYCONFIG_PATH_INFO *pathInfo);
8494
8495
8496
8497
8499// FUNCTION NAME: NvAPI_DISP_SetDisplayConfig
8500//
8501//
8526NVAPI_INTERFACE NvAPI_DISP_SetDisplayConfig(__in NvU32 pathInfoCount, __in_ecount(pathInfoCount) NV_DISPLAYCONFIG_PATH_INFO* pathInfo, __in NvU32 flags);
8527
8528
8529
8532typedef struct _NV_EDID_DATA_V1
8533{
8534 NvU32 version;
8535 NvU8 *pEDID;
8538
8539typedef struct _NV_EDID_DATA_V2
8540{
8541 NvU32 version;
8542 NvU8 *pEDID;
8544 NvU32 reserved[8];
8546
8548#define NV_EDID_DATA_VER1 MAKE_NVAPI_VERSION(NV_EDID_DATA_V1, 1)
8549#define NV_EDID_DATA_VER2 MAKE_NVAPI_VERSION(NV_EDID_DATA_V2, 2)
8550
8551#define NV_EDID_DATA_VER NV_EDID_DATA_VER2
8553//
8554// FUNCTION NAME: NvAPI_DISP_GetEdidData
8555//
8586NVAPI_INTERFACE NvAPI_DISP_GetEdidData(__in NvU32 displayId, __inout NV_EDID_DATA *pEdidParams, __inout NV_EDID_FLAG *pFlag);
8588
8601
8602#define NV_GET_ADAPTIVE_SYNC_DATA_VER1 MAKE_NVAPI_VERSION(NV_GET_ADAPTIVE_SYNC_DATA_V1,1)
8603#define NV_GET_ADAPTIVE_SYNC_DATA_VER NV_GET_ADAPTIVE_SYNC_DATA_VER1
8604
8606
8608//
8627NVAPI_INTERFACE NvAPI_DISP_GetAdaptiveSyncData(__in NvU32 displayId, __inout NV_GET_ADAPTIVE_SYNC_DATA *pAdaptiveSyncData);
8628
8639
8640#define NV_SET_ADAPTIVE_SYNC_DATA_VER1 MAKE_NVAPI_VERSION(NV_SET_ADAPTIVE_SYNC_DATA_V1,1)
8641#define NV_SET_ADAPTIVE_SYNC_DATA_VER NV_SET_ADAPTIVE_SYNC_DATA_VER1
8642
8644
8646//
8665NVAPI_INTERFACE NvAPI_DISP_SetAdaptiveSyncData(__in NvU32 displayId, __in NV_SET_ADAPTIVE_SYNC_DATA *pAdaptiveSyncData);
8666
8667
8674
8675#define NV_GET_VIRTUAL_REFRESH_RATE_DATA_VER1 MAKE_NVAPI_VERSION(_NV_GET_VIRTUAL_REFRESH_RATE_DATA_V1,1)
8676#define NV_GET_VIRTUAL_REFRESH_RATE_DATA_VER NV_GET_VIRTUAL_REFRESH_RATE_DATA_VER1
8677
8679
8681//
8700NVAPI_INTERFACE NvAPI_DISP_GetVirtualRefreshRateData(__in NvU32 displayId, __inout NV_GET_VIRTUAL_REFRESH_RATE_DATA *pVirtualRefreshRateData);
8701
8708
8709#define NV_SET_VIRTUAL_REFRESH_RATE_DATA_VER1 MAKE_NVAPI_VERSION(_NV_SET_VIRTUAL_REFRESH_RATE_DATA_V1,1)
8710#define NV_SET_VIRTUAL_REFRESH_RATE_DATA_VER NV_SET_VIRTUAL_REFRESH_RATE_DATA_VER1
8711
8713
8715//
8734NVAPI_INTERFACE NvAPI_DISP_SetVirtualRefreshRateData(__in NvU32 displayId, __in NV_SET_VIRTUAL_REFRESH_RATE_DATA *pVirtualRefreshRateData);
8735
8737typedef struct
8738{
8739 NvU32 version;
8741 NvU32 reserved;
8743
8746
8748#define NV_SET_PREFERRED_STEREO_DISPLAY_VER1 MAKE_NVAPI_VERSION(NV_SET_PREFERRED_STEREO_DISPLAY_V1,1)
8749
8751#define NV_SET_PREFERRED_STEREO_DISPLAY_VER NV_SET_PREFERRED_STEREO_DISPLAY_VER1
8752
8754// FUNCTION NAME: NvAPI_DISP_SetPreferredStereoDisplay
8755//
8774NVAPI_INTERFACE NvAPI_DISP_SetPreferredStereoDisplay(__in NV_SET_PREFERRED_STEREO_DISPLAY *pPreferredStereoDisplay);
8775
8777typedef struct
8778{
8779 NvU32 version;
8781 NvU32 reserved;
8783
8786
8788#define NV_GET_PREFERRED_STEREO_DISPLAY_VER1 MAKE_NVAPI_VERSION(NV_GET_PREFERRED_STEREO_DISPLAY_V1,1)
8789
8791#define NV_GET_PREFERRED_STEREO_DISPLAY_VER NV_GET_PREFERRED_STEREO_DISPLAY_VER1
8792
8794// FUNCTION NAME: NvAPI_DISP_GetPreferredStereoDisplay
8795//
8810NVAPI_INTERFACE NvAPI_DISP_GetPreferredStereoDisplay(__inout NV_GET_PREFERRED_STEREO_DISPLAY *pPreferredStereoDisplay);
8811
8814#if defined(__cplusplus)
8815
8816typedef struct _NV_MANAGED_DEDICATED_DISPLAY_INFO
8817{
8818 NvU32 version;
8819 NvU32 displayId;
8820 NvU32 isAcquired : 1;
8821 NvU32 isMosaic : 1;
8822 NvU32 reserved : 30;
8823} NV_MANAGED_DEDICATED_DISPLAY_INFO_V1;
8824
8825#define NV_MANAGED_DEDICATED_DISPLAY_INFO_VER1 MAKE_NVAPI_VERSION(NV_MANAGED_DEDICATED_DISPLAY_INFO_V1,1)
8826#define NV_MANAGED_DEDICATED_DISPLAY_INFO_VER NV_MANAGED_DEDICATED_DISPLAY_INFO_VER1
8827
8828typedef NV_MANAGED_DEDICATED_DISPLAY_INFO_V1 NV_MANAGED_DEDICATED_DISPLAY_INFO;
8829
8831//
8832// FUNCTION NAME: NvAPI_DISP_GetNvManagedDedicatedDisplays
8833//
8858NVAPI_INTERFACE NvAPI_DISP_GetNvManagedDedicatedDisplays(__inout NvU32* pDedicatedDisplayCount, __inout NV_MANAGED_DEDICATED_DISPLAY_INFO* pDedicatedDisplays);
8859#endif // defined(__cplusplus)
8860
8863#if defined(__cplusplus)
8865//
8866// FUNCTION NAME: NvAPI_DISP_AcquireDedicatedDisplay
8867//
8890NVAPI_INTERFACE NvAPI_DISP_AcquireDedicatedDisplay(__in NvU32 displayId, __inout NvU64* pDisplaySourceHandle);
8891#endif // defined(__cplusplus)
8892
8895#if defined(__cplusplus)
8897//
8898// FUNCTION NAME: NvAPI_DISP_ReleaseDedicatedDisplay
8899//
8916NVAPI_INTERFACE NvAPI_DISP_ReleaseDedicatedDisplay(__in NvU32 displayId);
8917#endif // defined(__cplusplus)
8918
8919
8920#if defined (_WINNT_)
8921
8923
8924typedef struct _NV_DISPLAY_ID_INFO_DATA_V1
8925{
8926 NvU32 version;
8927 LUID adapterId;
8928 NvU32 targetId;
8929 NvU32 reserved[4];
8930} NV_DISPLAY_ID_INFO_DATA_V1;
8931
8932#define NV_DISPLAY_ID_INFO_DATA_VER1 MAKE_NVAPI_VERSION(NV_DISPLAY_ID_INFO_DATA_V1,1)
8933#define NV_DISPLAY_ID_INFO_DATA_VER NV_DISPLAY_ID_INFO_DATA_VER1
8934
8935typedef NV_DISPLAY_ID_INFO_DATA_V1 NV_DISPLAY_ID_INFO_DATA;
8936
8938//
8939// FUNCTION NAME: NvAPI_Disp_GetDisplayIdInfo
8940//
8959NVAPI_INTERFACE NvAPI_Disp_GetDisplayIdInfo(__in NvU32 displayId, __inout NV_DISPLAY_ID_INFO_DATA* pDisplayIdInfoData);
8960
8961#endif
8962
8963
8965
8966#if defined (_WINNT_)
8967
8968typedef struct _NV_TARGET_INFO_DATA_V1
8969{
8970 NvU32 version;
8971 LUID adapterId;
8972 NvU32 targetId;
8973 NvU32 displayId[NVAPI_MAX_DISPLAYS];
8978 NvU32 displayIdCount;
8979 NvU32 reserved[4];
8980} NV_TARGET_INFO_DATA_V1;
8981
8982#define NV_TARGET_INFO_DATA_VER1 MAKE_NVAPI_VERSION(NV_TARGET_INFO_DATA_V1,1)
8983#define NV_TARGET_INFO_DATA_VER NV_TARGET_INFO_DATA_VER1
8984
8985typedef NV_TARGET_INFO_DATA_V1 NV_TARGET_INFO_DATA;
8986
8988//
8989// FUNCTION NAME: NvAPI_Disp_GetDisplayIdsFromTarget
8990//
9007NVAPI_INTERFACE NvAPI_Disp_GetDisplayIdsFromTarget(__inout NV_TARGET_INFO_DATA* pTargetInfoData);
9008
9009#endif
9010
9011
9013
9021
9022#define NV_GET_VRR_INFO_VER1 MAKE_NVAPI_VERSION(NV_GET_VRR_INFO_V1,1)
9023#define NV_GET_VRR_INFO_VER NV_GET_VRR_INFO_VER1
9024
9026
9028//
9029// FUNCTION NAME: NvAPI_Disp_GetVRRInfo
9030//
9044NVAPI_INTERFACE NvAPI_Disp_GetVRRInfo(__in NvU32 displayId, __inout NV_GET_VRR_INFO *pVrrInfo);
9045
9046
9047
9049//
9050// MOSAIC allows a multi display target output scanout on a single source.
9051//
9052// SAMPLE of MOSAIC 1x4 topo with 8 pixel horizontal overlap
9053//
9054//+-------------------------++-------------------------++-------------------------++-------------------------+
9055//| || || || |
9056//| || || || |
9057//| || || || |
9058//| DVI1 || DVI2 || DVI3 || DVI4 |
9059//| || || || |
9060//| || || || |
9061//| || || || |
9062//| || || || |
9063//+-------------------------++-------------------------++-------------------------++-------------------------+
9064
9065
9068
9069#define NVAPI_MAX_MOSAIC_DISPLAY_ROWS 8
9070#define NVAPI_MAX_MOSAIC_DISPLAY_COLUMNS 8
9071//
9072// These bits are used to describe the validity of a topo.
9073//
9074#define NV_MOSAIC_TOPO_VALIDITY_VALID 0x00000000
9075#define NV_MOSAIC_TOPO_VALIDITY_MISSING_GPU 0x00000001
9077#define NV_MOSAIC_TOPO_VALIDITY_MISSING_DISPLAY 0x00000002
9079#define NV_MOSAIC_TOPO_VALIDITY_MIXED_DISPLAY_TYPES 0x00000004
9082
9083
9084//
9086typedef struct
9087{
9088 NvU32 version;
9089 NvLogicalGpuHandle hLogicalGPU;
9092 NvU32 rowCount;
9093 NvU32 colCount;
9094
9095 struct
9096 {
9097 NvPhysicalGpuHandle hPhysicalGPU;
9099 NvS32 overlapX;
9100 NvS32 overlapY;
9101
9103
9105
9107#define NVAPI_MOSAIC_TOPO_DETAILS_VER MAKE_NVAPI_VERSION(NV_MOSAIC_TOPO_DETAILS,1)
9108
9109
9110//
9123
9124
9125//
9135typedef enum
9136{
9137 NV_MOSAIC_TOPO_NONE,
9138
9139 // 'BASIC' topos start here
9140 //
9141 // The result of using one of these Mosaic topos is that multiple monitors
9142 // will combine to create a single desktop.
9143 //
9144 NV_MOSAIC_TOPO_BEGIN_BASIC,
9145 NV_MOSAIC_TOPO_1x2_BASIC = NV_MOSAIC_TOPO_BEGIN_BASIC,
9146 NV_MOSAIC_TOPO_2x1_BASIC,
9147 NV_MOSAIC_TOPO_1x3_BASIC,
9148 NV_MOSAIC_TOPO_3x1_BASIC,
9149 NV_MOSAIC_TOPO_1x4_BASIC,
9150 NV_MOSAIC_TOPO_4x1_BASIC,
9151 NV_MOSAIC_TOPO_2x2_BASIC,
9152 NV_MOSAIC_TOPO_2x3_BASIC,
9153 NV_MOSAIC_TOPO_2x4_BASIC,
9154 NV_MOSAIC_TOPO_3x2_BASIC,
9155 NV_MOSAIC_TOPO_4x2_BASIC,
9156 NV_MOSAIC_TOPO_1x5_BASIC,
9157 NV_MOSAIC_TOPO_1x6_BASIC,
9158 NV_MOSAIC_TOPO_7x1_BASIC,
9159
9160 // Add padding for 10 more entries. 6 will be enough room to specify every
9161 // possible topology with 8 or fewer displays, so this gives us a little
9162 // extra should we need it.
9163 NV_MOSAIC_TOPO_END_BASIC = NV_MOSAIC_TOPO_7x1_BASIC + 9,
9164
9165 // 'PASSIVE_STEREO' topos start here
9166 //
9167 // The result of using one of these Mosaic topos is that multiple monitors
9168 // will combine to create a single PASSIVE STEREO desktop. What this means is
9169 // that there will be two topos that combine to create the overall desktop.
9170 // One topo will be used for the left eye, and the other topo (of the
9171 // same rows x cols), will be used for the right eye. The difference between
9172 // the two topos is that different GPUs and displays will be used.
9173 //
9174 NV_MOSAIC_TOPO_BEGIN_PASSIVE_STEREO, // value shadowed in nvEscDef.h
9175 NV_MOSAIC_TOPO_1x2_PASSIVE_STEREO = NV_MOSAIC_TOPO_BEGIN_PASSIVE_STEREO,
9176 NV_MOSAIC_TOPO_2x1_PASSIVE_STEREO,
9177 NV_MOSAIC_TOPO_1x3_PASSIVE_STEREO,
9178 NV_MOSAIC_TOPO_3x1_PASSIVE_STEREO,
9179 NV_MOSAIC_TOPO_1x4_PASSIVE_STEREO,
9180 NV_MOSAIC_TOPO_4x1_PASSIVE_STEREO,
9181 NV_MOSAIC_TOPO_2x2_PASSIVE_STEREO,
9182 NV_MOSAIC_TOPO_END_PASSIVE_STEREO = NV_MOSAIC_TOPO_2x2_PASSIVE_STEREO + 4,
9183
9184
9185 //
9186 // Total number of topos. Always leave this at the end of the enumeration.
9187 //
9189
9191
9192
9193//
9200typedef struct
9201{
9202 NvU32 version;
9204 NvU32 enabled;
9206
9208
9210#define NVAPI_MOSAIC_TOPO_BRIEF_VER MAKE_NVAPI_VERSION(NV_MOSAIC_TOPO_BRIEF,1)
9211
9212
9213//
9223
9233
9235
9237#define NVAPI_MOSAIC_DISPLAY_SETTING_VER1 MAKE_NVAPI_VERSION(NV_MOSAIC_DISPLAY_SETTING_V1,1)
9238#define NVAPI_MOSAIC_DISPLAY_SETTING_VER2 MAKE_NVAPI_VERSION(NV_MOSAIC_DISPLAY_SETTING_V2,2)
9239#define NVAPI_MOSAIC_DISPLAY_SETTING_VER NVAPI_MOSAIC_DISPLAY_SETTING_VER2
9240
9241
9242//
9243// Set a reasonable max number of display settings to support
9244// so arrays are bound.
9245//
9246#define NV_MOSAIC_DISPLAY_SETTINGS_MAX 40
9248
9249
9250//
9262
9272
9274
9276#define NVAPI_MOSAIC_SUPPORTED_TOPO_INFO_VER1 MAKE_NVAPI_VERSION(NV_MOSAIC_SUPPORTED_TOPO_INFO_V1,1)
9277#define NVAPI_MOSAIC_SUPPORTED_TOPO_INFO_VER2 MAKE_NVAPI_VERSION(NV_MOSAIC_SUPPORTED_TOPO_INFO_V2,2)
9278#define NVAPI_MOSAIC_SUPPORTED_TOPO_INFO_VER NVAPI_MOSAIC_SUPPORTED_TOPO_INFO_VER2
9279
9280
9281//
9282// Indices to use to access the topos array within the mosaic topology
9283#define NV_MOSAIC_TOPO_IDX_DEFAULT 0
9284
9285#define NV_MOSAIC_TOPO_IDX_LEFT_EYE 0
9286#define NV_MOSAIC_TOPO_IDX_RIGHT_EYE 1
9287#define NV_MOSAIC_TOPO_NUM_EYES 2
9288
9289
9290//
9297#define NV_MOSAIC_MAX_TOPO_PER_TOPO_GROUP 2
9298
9299
9300//
9325
9327#define NVAPI_MOSAIC_TOPO_GROUP_VER MAKE_NVAPI_VERSION(NV_MOSAIC_TOPO_GROUP,1)
9328
9330
9331
9333//
9334// FUNCTION NAME: NvAPI_Mosaic_GetSupportedTopoInfo
9335//
9385// compatible with this entry point.
9391
9392
9394//
9395// FUNCTION NAME: NvAPI_Mosaic_GetTopoGroup
9396//
9429// compatible with this entry point.
9435
9436
9438//
9439// FUNCTION NAME: NvAPI_Mosaic_GetOverlapLimits
9440//
9471NVAPI_INTERFACE NvAPI_Mosaic_GetOverlapLimits(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 *pMinOverlapX, NvS32 *pMaxOverlapX, NvS32 *pMinOverlapY, NvS32 *pMaxOverlapY);
9472
9473
9475//
9476// FUNCTION NAME: NvAPI_Mosaic_SetCurrentTopo
9477//
9519NVAPI_INTERFACE NvAPI_Mosaic_SetCurrentTopo(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 overlapX, NvS32 overlapY, NvU32 enable);
9520
9521
9523//
9524// FUNCTION NAME: NvAPI_Mosaic_GetCurrentTopo
9525//
9554NVAPI_INTERFACE NvAPI_Mosaic_GetCurrentTopo(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 *pOverlapX, NvS32 *pOverlapY);
9555
9556
9558//
9559// FUNCTION NAME: NvAPI_Mosaic_EnableCurrentTopo
9560//
9589NVAPI_INTERFACE NvAPI_Mosaic_EnableCurrentTopo(NvU32 enable);
9590
9601
9610
9622
9623#ifndef NV_MOSAIC_GRID_TOPO_DISPLAY_VER
9624
9626
9627#endif
9628
9644
9661
9663#define NV_MOSAIC_GRID_TOPO_VER1 MAKE_NVAPI_VERSION(NV_MOSAIC_GRID_TOPO_V1,1)
9664#define NV_MOSAIC_GRID_TOPO_VER2 MAKE_NVAPI_VERSION(NV_MOSAIC_GRID_TOPO_V2,2)
9665#ifndef NV_MOSAIC_GRID_TOPO_VER
9666
9668
9670#define NV_MOSAIC_GRID_TOPO_VER NV_MOSAIC_GRID_TOPO_VER2
9671
9672#endif
9673
9675
9677
9678#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_DISPLAY_ON_INVALID_GPU NV_BIT(0)
9679#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_DISPLAY_ON_WRONG_CONNECTOR NV_BIT(1)
9680#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NO_COMMON_TIMINGS NV_BIT(2)
9681#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NO_EDID_AVAILABLE NV_BIT(3)
9682#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_MISMATCHED_OUTPUT_TYPE NV_BIT(4)
9683#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NO_DISPLAY_CONNECTED NV_BIT(5)
9684#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NO_GPU_TOPOLOGY NV_BIT(6)
9685#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NOT_SUPPORTED NV_BIT(7)
9686#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_NO_SLI_BRIDGE NV_BIT(8)
9687#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_ECC_ENABLED NV_BIT(9)
9688#define NV_MOSAIC_DISPLAYCAPS_PROBLEM_GPU_TOPOLOGY_NOT_SUPPORTED NV_BIT(10)
9689
9690
9691
9692
9693
9694
9695
9698#define NV_MOSAIC_SETDISPLAYTOPO_FLAG_CURRENT_GPU_TOPOLOGY NV_BIT(0)
9699
9702#define NV_MOSAIC_SETDISPLAYTOPO_FLAG_NO_DRIVER_RELOAD NV_BIT(1)
9703
9707#define NV_MOSAIC_SETDISPLAYTOPO_FLAG_MAXIMIZE_PERFORMANCE NV_BIT(2)
9708
9710#define NV_MOSAIC_SETDISPLAYTOPO_FLAG_ALLOW_INVALID NV_BIT(3)
9711
9713//
9714// FUNCTION NAME: NvAPI_Mosaic_SetDisplayGrids
9715//
9743NVAPI_INTERFACE NvAPI_Mosaic_SetDisplayGrids(__in_ecount(gridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies, __in NvU32 gridCount, __in NvU32 setTopoFlags);
9744
9745
9748#define NV_MOSAIC_DISPLAYTOPO_WARNING_DISPLAY_POSITION NV_BIT(0)
9749
9752#define NV_MOSAIC_DISPLAYTOPO_WARNING_DRIVER_RELOAD_REQUIRED NV_BIT(1)
9753
9755typedef struct
9756{
9757 NvU32 version;
9760
9762 struct
9763 {
9767
9769 NvU32 reserved : 31;
9770 } displays[NVAPI_MAX_DISPLAYS];
9772
9774#define NV_MOSAIC_DISPLAY_TOPO_STATUS_VER MAKE_NVAPI_VERSION(NV_MOSAIC_DISPLAY_TOPO_STATUS,1)
9775
9776
9778//
9779// FUNCTION NAME: NvAPI_Mosaic_ValidateDisplayGrids
9780//
9818NVAPI_INTERFACE NvAPI_Mosaic_ValidateDisplayGrids(__in NvU32 setTopoFlags,
9819 __in_ecount(gridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies,
9820 __inout_ecount_full(gridCount) NV_MOSAIC_DISPLAY_TOPO_STATUS *pTopoStatus,
9821 __in NvU32 gridCount);
9822
9823
9824
9826//
9827// FUNCTION NAME: NvAPI_Mosaic_EnumDisplayModes
9828//
9853NVAPI_INTERFACE NvAPI_Mosaic_EnumDisplayModes(__in NV_MOSAIC_GRID_TOPO *pGridTopology,
9854 __inout_ecount_part_opt(*pDisplayCount, *pDisplayCount) NV_MOSAIC_DISPLAY_SETTING *pDisplaySettings,
9855 __inout NvU32 *pDisplayCount);
9856
9857
9861//
9862// FUNCTION NAME: NvAPI_Mosaic_EnumDisplayGrids
9863//
9886NVAPI_INTERFACE NvAPI_Mosaic_EnumDisplayGrids(__inout_ecount_part_opt(*pGridCount, *pGridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies,
9887 __inout NvU32 *pGridCount);
9888
9889
9891//
9892// ###########################################################################
9893// DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS
9894//
9895// Below is the Phase 1 Mosaic stuff, the Phase 2 stuff above is what will remain
9896// once Phase 2 is complete. For a small amount of time, the two will co-exist. As
9897// soon as apps (nvapichk, NvAPITestMosaic, and CPL) are updated to use the Phase 2
9898// entrypoints, the code below will be deleted.
9899//
9900// DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS - DELME_RUSS
9901// ###########################################################################
9902//
9903// Supported topos 1x4, 4x1 and 2x2 to start with.
9904//
9905// Selected scan out targets can be one per GPU or more than one on the same GPU.
9906//
9907// SAMPLE of MOSAIC 1x4 SCAN OUT TOPO with 8 pixel horizontal overlap
9908//
9909//+-------------------------++-------------------------++-------------------------++-------------------------+
9910//| || || || |
9911//| || || || |
9912//| || || || |
9913//| DVI1 || DVI2 || DVI3 || DVI4 |
9914//| || || || |
9915//| || || || |
9916//| || || || |
9917//| || || || |
9918//+-------------------------++-------------------------++-------------------------++-------------------------+
9919
9920
9923
9925#define NVAPI_MAX_MOSAIC_DISPLAY_ROWS 8
9926
9928#define NVAPI_MAX_MOSAIC_DISPLAY_COLUMNS 8
9929
9931#define NVAPI_MAX_MOSAIC_TOPOS 16
9932
9934typedef struct
9935{
9936 NvU32 version;
9937 NvU32 rowCount;
9938 NvU32 colCount;
9939
9940 struct
9941 {
9942 NvPhysicalGpuHandle hPhysicalGPU;
9944 NvS32 overlapX;
9945 NvS32 overlapY;
9946
9948
9950
9952#define NVAPI_MOSAIC_TOPOLOGY_VER MAKE_NVAPI_VERSION(NV_MOSAIC_TOPOLOGY,1)
9953
9955typedef struct
9956{
9957 NvU32 version;
9960
9962
9964#define NVAPI_MOSAIC_SUPPORTED_TOPOLOGIES_VER MAKE_NVAPI_VERSION(NV_MOSAIC_SUPPORTED_TOPOLOGIES,1)
9965
9967
9968
9970//
9971// FUNCTION NAME: NvAPI_GetSupportedMosaicTopologies
9972//
9992
9994//
9995// FUNCTION NAME: NvAPI_GetCurrentMosaicTopology
9996//
10015NVAPI_INTERFACE NvAPI_GetCurrentMosaicTopology(NV_MOSAIC_TOPOLOGY *pMosaicTopo, NvU32 *pEnabled);
10016
10017
10019//
10020// FUNCTION NAME: NvAPI_SetCurrentMosaicTopology
10021//
10041
10043//
10044// FUNCTION NAME: NvAPI_EnableCurrentMosaicTopology
10045//
10067NVAPI_INTERFACE NvAPI_EnableCurrentMosaicTopology(NvU32 enable);
10068
10069
10070#define NVAPI_MAX_GSYNC_DEVICES 4
10071
10072
10073// Sync Display APIs
10074
10076//
10077// FUNCTION NAME: NvAPI_GSync_EnumSyncDevices
10078//
10101NVAPI_INTERFACE NvAPI_GSync_EnumSyncDevices(__out NvGSyncDeviceHandle nvGSyncHandles[NVAPI_MAX_GSYNC_DEVICES], __out NvU32 *gsyncCount);
10102
10103
10104// GSync boardId values
10105#define NVAPI_GSYNC_BOARD_ID_P358 856
10106#define NVAPI_GSYNC_BOARD_ID_P2060 8288
10107
10109#define NVAPI_GSYNC_BOARD_ID_P2061 8289
10110
10111
10120
10129
10142
10144
10145
10148#define NV_GSYNC_CAPABILITIES_VER1 MAKE_NVAPI_VERSION(NV_GSYNC_CAPABILITIES_V1,1)
10149#define NV_GSYNC_CAPABILITIES_VER2 MAKE_NVAPI_VERSION(NV_GSYNC_CAPABILITIES_V2,2)
10150#define NV_GSYNC_CAPABILITIES_VER3 MAKE_NVAPI_VERSION(NV_GSYNC_CAPABILITIES_V3,3)
10151#define NV_GSYNC_CAPABILITIES_VER NV_GSYNC_CAPABILITIES_VER3
10152
10153
10155//
10156// FUNCTION NAME: NvAPI_GSync_QueryCapabilities
10157//
10178NVAPI_INTERFACE NvAPI_GSync_QueryCapabilities(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CAPABILITIES *pNvGSyncCapabilities);
10179
10180
10181
10184{
10185 NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR_NONE = 0,
10186 NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR_PRIMARY = 1,
10187 NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR_SECONDARY = 2,
10188 NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR_TERTIARY = 3,
10189 NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR_QUARTERNARY = 4,
10191
10194{
10195 NVAPI_GSYNC_DISPLAY_SYNC_STATE_UNSYNCED = 0,
10196 NVAPI_GSYNC_DISPLAY_SYNC_STATE_SLAVE = 1,
10197 NVAPI_GSYNC_DISPLAY_SYNC_STATE_MASTER = 2,
10199
10200typedef struct _NV_GSYNC_GPU
10201{
10202 NvU32 version;
10203 NvPhysicalGpuHandle hPhysicalGpu;
10205 NvPhysicalGpuHandle hProxyPhysicalGpu;
10207 NvU32 isSynced : 1;
10208 NvU32 reserved : 31;
10209} NV_GSYNC_GPU;
10210
10220
10221#define NV_GSYNC_DISPLAY_VER MAKE_NVAPI_VERSION(NV_GSYNC_DISPLAY,1)
10222#define NV_GSYNC_GPU_VER MAKE_NVAPI_VERSION(NV_GSYNC_GPU,1)
10223
10224
10226//
10227// FUNCTION NAME: NvAPI_GSync_GetTopology
10228//
10257NVAPI_INTERFACE NvAPI_GSync_GetTopology(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout_opt NvU32 *gsyncGpuCount, __inout_ecount_part_opt(*gsyncGpuCount, *gsyncGpuCount) NV_GSYNC_GPU *gsyncGPUs,
10258 __inout_opt NvU32 *gsyncDisplayCount, __inout_ecount_part_opt(*gsyncDisplayCount, *gsyncDisplayCount) NV_GSYNC_DISPLAY *gsyncDisplays);
10259
10261//
10262// FUNCTION NAME: NvAPI_GSync_SetSyncStateSettings
10263//
10291NVAPI_INTERFACE NvAPI_GSync_SetSyncStateSettings(__in NvU32 gsyncDisplayCount, __in_ecount(gsyncDisplayCount) NV_GSYNC_DISPLAY *pGsyncDisplays, __in NvU32 flags);
10292
10293
10295
10298{
10299 NVAPI_GSYNC_POLARITY_RISING_EDGE = 0,
10300 NVAPI_GSYNC_POLARITY_FALLING_EDGE = 1,
10301 NVAPI_GSYNC_POLARITY_BOTH_EDGES = 2,
10303
10306{
10307 NVAPI_GSYNC_VIDEO_MODE_NONE = 0,
10308 NVAPI_GSYNC_VIDEO_MODE_TTL = 1,
10309 NVAPI_GSYNC_VIDEO_MODE_NTSCPALSECAM = 2,
10310 NVAPI_GSYNC_VIDEO_MODE_HDTV = 3,
10311 NVAPI_GSYNC_VIDEO_MODE_COMPOSITE = 4,
10313
10316{
10317 NVAPI_GSYNC_SYNC_SOURCE_VSYNC = 0,
10318 NVAPI_GSYNC_SYNC_SOURCE_HOUSESYNC = 1,
10320
10322typedef struct _NV_GSYNC_DELAY
10323{
10324 NvU32 version;
10325 NvU32 numLines;
10327 NvU32 maxLines;
10330
10331#define NV_GSYNC_DELAY_VER MAKE_NVAPI_VERSION(NV_GSYNC_DELAY,1)
10332
10348
10351{
10352 NVAPI_GSYNC_UNDEFINED_MODE = 0,
10353 NVAPI_GSYNC_MULTIPLY_MODE = 1,
10354 NVAPI_GSYNC_DIVIDE_MODE = 2,
10356
10375
10377#define NV_GSYNC_CONTROL_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_GSYNC_CONTROL_PARAMS_V1,1)
10378#define NV_GSYNC_CONTROL_PARAMS_VER2 MAKE_NVAPI_VERSION(NV_GSYNC_CONTROL_PARAMS_V2,2)
10379#define NV_GSYNC_CONTROL_PARAMS_VER NV_GSYNC_CONTROL_PARAMS_VER2
10380
10381
10383//
10384// FUNCTION NAME: NvAPI_GSync_GetControlParameters
10385//
10403NVAPI_INTERFACE NvAPI_GSync_GetControlParameters(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CONTROL_PARAMS *pGsyncControls);
10404
10405
10406
10408//
10409// FUNCTION NAME: NvAPI_GSync_SetControlParameters
10410//
10430NVAPI_INTERFACE NvAPI_GSync_SetControlParameters(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CONTROL_PARAMS *pGsyncControls);
10431
10432
10433
10434
10437{
10438 NVAPI_GSYNC_DELAY_TYPE_UNKNOWN = 0,
10439 NVAPI_GSYNC_DELAY_TYPE_SYNC_SKEW = 1,
10440 NVAPI_GSYNC_DELAY_TYPE_STARTUP = 2
10442
10444//
10445// FUNCTION NAME: NvAPI_GSync_AdjustSyncDelay
10446//
10464NVAPI_INTERFACE NvAPI_GSync_AdjustSyncDelay(__in NvGSyncDeviceHandle hNvGSyncDevice, __in NVAPI_GSYNC_DELAY_TYPE delayType, __inout NV_GSYNC_DELAY *pGsyncDelay, __out_opt NvU32* syncSteps);
10465
10466
10467
10476
10478#define NV_GSYNC_STATUS_VER MAKE_NVAPI_VERSION(NV_GSYNC_STATUS,1)
10479
10481//
10482// FUNCTION NAME: NvAPI_GSync_GetSyncStatus
10483//
10503NVAPI_INTERFACE NvAPI_GSync_GetSyncStatus(__in NvGSyncDeviceHandle hNvGSyncDevice, __in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GSYNC_STATUS *status);
10504
10505
10507
10508#define NVAPI_MAX_RJ45_PER_GSYNC 2
10509
10512{
10513 NVAPI_GSYNC_RJ45_OUTPUT = 0,
10514 NVAPI_GSYNC_RJ45_INPUT = 1,
10516
10518
10522{
10523 NvU32 version;
10525 NVAPI_GSYNC_RJ45_IO RJ45_IO[NVAPI_MAX_RJ45_PER_GSYNC];
10526 NvU32 RJ45_Ethernet[NVAPI_MAX_RJ45_PER_GSYNC];
10530
10532{
10533 NvU32 version;
10535 NVAPI_GSYNC_RJ45_IO RJ45_IO[NVAPI_MAX_RJ45_PER_GSYNC];
10536 NvU32 RJ45_Ethernet[NVAPI_MAX_RJ45_PER_GSYNC];
10539 NvU32 bInternalSlave : 1;
10541 NvU32 reserved : 31;
10543
10544
10546
10549#define NV_GSYNC_STATUS_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_GSYNC_STATUS_PARAMS_V1,1)
10550#define NV_GSYNC_STATUS_PARAMS_VER2 MAKE_NVAPI_VERSION(NV_GSYNC_STATUS_PARAMS_V2,2)
10551#define NV_GSYNC_STATUS_PARAMS_VER NV_GSYNC_STATUS_PARAMS_VER2
10552
10554//
10555// FUNCTION NAME: NvAPI_GSync_GetStatusParameters
10556//
10575NVAPI_INTERFACE NvAPI_GSync_GetStatusParameters(NvGSyncDeviceHandle hNvGSyncDevice, NV_GSYNC_STATUS_PARAMS *pStatusParams);
10576
10578
10579
10580
10581
10582
10583
10584
10585
10586#if defined(_D3D9_H_)
10588//
10589// FUNCTION NAME: NvAPI_D3D9_RegisterResource
10590//
10602NVAPI_INTERFACE NvAPI_D3D9_RegisterResource(IDirect3DResource9* pResource);
10603#endif //defined(_D3D9_H_)
10604
10605#if defined(_D3D9_H_)
10607//
10608// FUNCTION NAME: NvAPI_D3D9_UnregisterResource
10609//
10621NVAPI_INTERFACE NvAPI_D3D9_UnregisterResource(IDirect3DResource9* pResource);
10622
10623#endif //defined(_D3D9_H_)
10624
10625
10626
10627
10628#if defined(_D3D9_H_)
10630//
10631// FUNCTION NAME: NvAPI_D3D9_AliasSurfaceAsTexture
10632//
10658//
10660
10661
10664typedef enum {
10665 NVAPI_ALIAS_SURFACE_FLAG_NONE = 0x00000000,
10666 NVAPI_ALIAS_SURFACE_FLAG_USE_SUPER = 0x00000001,
10667 NVAPI_ALIAS_SURFACE_FLAG_MASK = 0x00000001
10668} NVAPI_ALIAS_SURFACE_FLAG;
10669
10670
10672NVAPI_INTERFACE NvAPI_D3D9_AliasSurfaceAsTexture(IDirect3DDevice9* pDev,
10673 IDirect3DSurface9* pSurface,
10674 IDirect3DTexture9 **ppTexture,
10675 DWORD dwFlag);
10676#endif //defined(_D3D9_H_)
10677
10678#if defined(_D3D9_H_)
10680//
10681// FUNCTION NAME: NvAPI_D3D9_StretchRectEx
10682//
10710NVAPI_INTERFACE NvAPI_D3D9_StretchRectEx(IDirect3DDevice9 * pDevice,
10711 IDirect3DResource9 * pSourceResource,
10712 CONST RECT * pSourceRect,
10713 IDirect3DResource9 * pDestResource,
10714 CONST RECT * pDestRect,
10715 D3DTEXTUREFILTERTYPE Filter);
10716
10717#endif //defined(_D3D9_H_)
10718
10719#if defined(_D3D9_H_)
10721//
10722// FUNCTION NAME: NvAPI_D3D9_ClearRT
10723//
10743NVAPI_INTERFACE NvAPI_D3D9_ClearRT(IDirect3DDevice9 * pDevice,
10744 NvU32 dwNumRects,
10745 CONST RECT * pRects,
10746 float r, float g, float b, float a);
10747#endif //if defined(_D3D9_H_)
10748
10749
10750
10751
10752
10753
10754
10755
10756
10757
10758#if defined(_D3D9_H_) && defined(__cplusplus)
10761
10763//
10764// FUNCTION NAME: NvAPI_D3D9_GetSurfaceHandle
10765//
10778NVAPI_INTERFACE NvAPI_D3D9_GetSurfaceHandle(IDirect3DSurface9 *pSurface,
10779 NVDX_ObjectHandle *pHandle);
10780
10781#endif //defined(_D3D9_H_) && defined(__cplusplus)
10782
10783#if defined(_D3D9_H_) && defined(__cplusplus)
10788
10790//
10791// FUNCTION_NAME: NvAPI_D3D9_VideoSetStereoInfo
10792//
10809
10810#ifndef NV_STEREO_VIDEO_FORMAT_DEFINE
10811#define NV_STEREO_VIDEO_FORMAT_DEFINE
10812
10813
10814typedef enum _NV_STEREO_VIDEO_FORMAT
10815{
10816 NV_STEREO_VIDEO_FORMAT_NOT_STEREO = 0,
10817
10818 NV_STEREO_VIDEO_FORMAT_SIDE_BY_SIDE_LR = 1,
10819 NV_STEREO_VIDEO_FORMAT_SIDE_BY_SIDE_RL = 2,
10820 NV_STEREO_VIDEO_FORMAT_TOP_BOTTOM_LR = 3,
10821 NV_STEREO_VIDEO_FORMAT_TOP_BOTTOM_RL = 4,
10822 NV_STEREO_VIDEO_FORMAT_ROW_INTERLEAVE_LR = 5,
10823 NV_STEREO_VIDEO_FORMAT_ROW_INTERLEAVE_RL = 6,
10824 NV_STEREO_VIDEO_FORMAT_TWO_FRAMES_LR = 7,
10825 NV_STEREO_VIDEO_FORMAT_MONO_PLUS_OFFSET = 8,
10826
10827 NV_STEREO_VIDEO_FORMAT_LAST = 9,
10828} NV_STEREO_VIDEO_FORMAT;
10829
10830#endif // NV_STEREO_VIDEO_FORMAT_DEFINE
10831
10832
10833typedef struct _NV_DX_VIDEO_STEREO_INFO {
10834 NvU32 dwVersion;
10835 NVDX_ObjectHandle hSurface;
10836 NVDX_ObjectHandle hLinkedSurface;
10837 NV_STEREO_VIDEO_FORMAT eFormat;
10838 NvS32 sViewOffset;
10839 BOOL bStereoEnable;
10840} NV_DX_VIDEO_STEREO_INFO;
10841
10843#define NV_DX_VIDEO_STEREO_INFO_VER MAKE_NVAPI_VERSION(NV_DX_VIDEO_STEREO_INFO,1)
10844
10845NVAPI_INTERFACE NvAPI_D3D9_VideoSetStereoInfo(IDirect3DDevice9 *pDev,
10846 NV_DX_VIDEO_STEREO_INFO *pStereoInfo);
10847
10849#endif //defined(_D3D9_H_) && defined(__cplusplus)
10850
10851
10852#if defined(__cplusplus) && defined(__d3d10_h__)
10854//
10855// FUNCTION NAME: NvAPI_D3D10_SetDepthBoundsTest
10856//
10874NVAPI_INTERFACE NvAPI_D3D10_SetDepthBoundsTest(ID3D10Device *pDev,
10875 NvU32 bEnable,
10876 float fMinDepth,
10877 float fMaxDepth);
10878
10879#endif //defined(__cplusplus) && defined(__d3d10_h__)
10880
10881
10882
10883
10884
10885#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
10886
10888//
10889// FUNCTION NAME: NvAPI_D3D11_IsNvShaderExtnOpCodeSupported
10890//
10912NVAPI_INTERFACE NvAPI_D3D11_IsNvShaderExtnOpCodeSupported(__in IUnknown *pDev,
10913 __in NvU32 opCode,
10914 __out bool *pSupported);
10915
10916#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
10917
10918#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
10919
10921//
10922// FUNCTION NAME: NvAPI_D3D11_SetNvShaderExtnSlot
10923//
10948NVAPI_INTERFACE NvAPI_D3D11_SetNvShaderExtnSlot(__in IUnknown *pDev,
10949 __in NvU32 uavSlot);
10950
10951#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
10952
10953#if defined (__cplusplus) && defined (__d3d12_h__)
10954
10956//
10957// FUNCTION NAME: NvAPI_D3D12_SetNvShaderExtnSlotSpace
10958//
10986NVAPI_INTERFACE NvAPI_D3D12_SetNvShaderExtnSlotSpace(__in IUnknown *pDev,
10987 __in NvU32 uavSlot,
10988 __in NvU32 uavSpace);
10989
10991//
10992// FUNCTION NAME: NvAPI_D3D12_SetNvShaderExtnSlotSpaceLocalThread
10993//
11025NVAPI_INTERFACE NvAPI_D3D12_SetNvShaderExtnSlotSpaceLocalThread(__in IUnknown *pDev,
11026 __in NvU32 uavSlot,
11027 __in NvU32 uavSpace);
11028
11029#endif //defined (__cplusplus) && defined (__d3d12_h__)
11030
11031#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11032
11034//
11035// FUNCTION NAME: NvAPI_D3D11_SetNvShaderExtnSlotLocalThread
11036//
11064NVAPI_INTERFACE NvAPI_D3D11_SetNvShaderExtnSlotLocalThread(__in IUnknown *pDev,
11065 __in NvU32 uavSlot);
11066
11067#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11068
11069#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11070
11072//
11073// FUNCTION NAME: NvAPI_D3D11_BeginUAVOverlapEx
11074//
11090typedef enum _NVAPI_D3D11_INSERTWFI_FLAG
11091{
11092 NVAPI_D3D_BEGIN_UAV_OVERLAP_NO_WFI = 0x00000000,
11093 NVAPI_D3D_BEGIN_UAV_OVERLAP_GFX_WFI = 0x00000001,
11094 NVAPI_D3D_BEGIN_UAV_OVERLAP_COMP_WFI = 0x00000002,
11095} NVAPI_D3D11_INSERTWFI_FLAG;
11096
11097NVAPI_INTERFACE NvAPI_D3D11_BeginUAVOverlapEx(__in IUnknown *pDeviceOrContext, __in NvU32 insertWFIFlags);
11098
11099#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11100
11101#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11102
11104//
11105// FUNCTION NAME: NvAPI_D3D11_BeginUAVOverlap
11106//
11121NVAPI_INTERFACE NvAPI_D3D11_BeginUAVOverlap(__in IUnknown *pDeviceOrContext);
11122
11123#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11124
11125#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11126
11128//
11129// FUNCTION NAME: NvAPI_D3D11_EndUAVOverlap
11130//
11144NVAPI_INTERFACE NvAPI_D3D11_EndUAVOverlap(__in IUnknown *pDeviceOrContext);
11145
11146#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11147
11148#if defined(__cplusplus) && defined(__d3d11_h__)
11150//
11151// FUNCTION NAME: NvAPI_D3D11_GetResourceHandle
11152//
11171NVAPI_INTERFACE NvAPI_D3D11_GetResourceHandle(ID3D11Device *pDev,
11172 ID3D11Resource* pResource,
11173 NVDX_ObjectHandle* phObject);
11174
11175#endif //defined(__cplusplus) && defined(__d3d11_h__)
11176
11177#if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
11179//
11180// FUNCTION NAME: NvAPI_D3D_SetFPSIndicatorState
11181//
11195NVAPI_INTERFACE NvAPI_D3D_SetFPSIndicatorState(IUnknown *pDev, NvU8 doEnable);
11196
11197#endif //if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
11198
11199#if defined(_D3D9_H_)
11201//
11202// FUNCTION NAME: NvAPI_D3D9_Present
11203//
11239NVAPI_INTERFACE NvAPI_D3D9_Present(IDirect3DDevice9 *pDevice,
11240 IDirect3DSwapChain9 *pSwapChain,
11241 const RECT *pSourceRect,
11242 const RECT *pDestRect,
11243 HWND hDestWindowOverride,
11244 const RGNDATA *pDirtyRegion);
11245#endif //if defined(_D3D9_H_)
11246
11247#if defined(_D3D9_H_)
11249//
11250// FUNCTION NAME: NvAPI_D3D9_QueryFrameCount
11251//
11267NVAPI_INTERFACE NvAPI_D3D9_QueryFrameCount(IDirect3DDevice9 *pDevice,
11268 NvU32 *pFrameCount);
11269#endif //if defined(_D3D9_H_)
11270
11271#if defined(_D3D9_H_)
11273//
11274// FUNCTION NAME: NvAPI_D3D9_ResetFrameCount
11275//
11290NVAPI_INTERFACE NvAPI_D3D9_ResetFrameCount(IDirect3DDevice9 *pDevice);
11291#endif //if defined(_D3D9_H_)
11292
11293#if defined(_D3D9_H_)
11295//
11296// FUNCTION NAME: NvAPI_D3D9_QueryMaxSwapGroup
11297//
11314NVAPI_INTERFACE NvAPI_D3D9_QueryMaxSwapGroup(IDirect3DDevice9 *pDevice,
11315 NvU32 *pMaxGroups,
11316 NvU32 *pMaxBarriers);
11317#endif //if defined(_D3D9_H_)
11318
11319#if defined(_D3D9_H_)
11321//
11322// FUNCTION NAME: NvAPI_D3D9_QuerySwapGroup
11323//
11342NVAPI_INTERFACE NvAPI_D3D9_QuerySwapGroup(IDirect3DDevice9 *pDevice,
11343 IDirect3DSwapChain9 *pSwapChain,
11344 NvU32 *pSwapGroup,
11345 NvU32 *pSwapBarrier);
11346#endif //if defined(_D3D9_H_)
11347
11348#if defined(_D3D9_H_)
11350//
11351// FUNCTION NAME: NvAPI_D3D9_JoinSwapGroup
11352//
11377NVAPI_INTERFACE NvAPI_D3D9_JoinSwapGroup(IDirect3DDevice9 *pDevice,
11378 IDirect3DSwapChain9 *pSwapChain,
11379 NvU32 group,
11380 BOOL blocking);
11381#endif //if defined(_D3D9_H_)
11382
11383#if defined(_D3D9_H_)
11385//
11386// FUNCTION NAME: NvAPI_D3D9_BindSwapBarrier
11387//
11407NVAPI_INTERFACE NvAPI_D3D9_BindSwapBarrier(IDirect3DDevice9 *pDevice,
11408 NvU32 group,
11409 NvU32 barrier);
11410#endif //if defined(_D3D9_H_)
11411
11413typedef enum
11414{
11420 NVAPI_VSYNC_ADAPTIVE_HALF_REFRESH_RATE
11421
11422} NVAPI_VSYNC_MODE;
11423
11424
11425#if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11427//
11428// FUNCTION NAME: NvAPI_D3D_SetVerticalSyncMode
11429//
11443NVAPI_INTERFACE NvAPI_D3D_SetVerticalSyncMode(__in IUnknown *pDevice, __in NVAPI_VSYNC_MODE vsyncMode);
11444
11445#endif //if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11446
11447#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11449//
11450// FUNCTION NAME: NvAPI_D3D1x_Present
11451//
11477// DXGI_STATUS_OCCLUDED, or D3DDDIERR_DEVICEREMOVED.
11483NVAPI_INTERFACE NvAPI_D3D1x_Present(IUnknown *pDevice,
11484 IDXGISwapChain *pSwapChain,
11485 UINT SyncInterval,
11486 UINT Flags);
11487#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11488
11489#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11491//
11492// FUNCTION NAME: NvAPI_D3D1x_QueryFrameCount
11493//
11510NVAPI_INTERFACE NvAPI_D3D1x_QueryFrameCount(IUnknown *pDevice,
11511 NvU32 *pFrameCount);
11512#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11513
11514#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11516//
11517// FUNCTION NAME: NvAPI_D3D1x_ResetFrameCount
11518//
11534NVAPI_INTERFACE NvAPI_D3D1x_ResetFrameCount(IUnknown *pDevice);
11535#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11536
11537#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11539//
11540// FUNCTION NAME: NvAPI_D3D1x_QueryMaxSwapGroup
11541//
11559NVAPI_INTERFACE NvAPI_D3D1x_QueryMaxSwapGroup(IUnknown *pDevice,
11560 NvU32 *pMaxGroups,
11561 NvU32 *pMaxBarriers);
11562#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11563
11564#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11566//
11567// FUNCTION NAME: NvAPI_D3D1x_QuerySwapGroup
11568//
11588NVAPI_INTERFACE NvAPI_D3D1x_QuerySwapGroup(IUnknown *pDevice,
11589 IDXGISwapChain *pSwapChain,
11590 NvU32 *pSwapGroup,
11591 NvU32 *pSwapBarrier);
11592#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11593
11594#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11596//
11597// FUNCTION NAME: NvAPI_D3D1x_JoinSwapGroup
11598//
11623NVAPI_INTERFACE NvAPI_D3D1x_JoinSwapGroup(IUnknown *pDevice,
11624 IDXGISwapChain *pSwapChain,
11625 NvU32 group,
11626 BOOL blocking);
11627#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11628
11629#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11631//
11632// FUNCTION NAME: NvAPI_D3D1x_BindSwapBarrier
11633//
11653NVAPI_INTERFACE NvAPI_D3D1x_BindSwapBarrier(IUnknown *pDevice,
11654 NvU32 group,
11655 NvU32 barrier);
11656#endif // defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__)
11657
11660#if defined(__cplusplus) && defined(__d3d12_h__)
11662//
11663// FUNCTION NAME: NvAPI_D3D12_QueryPresentBarrierSupport
11664//
11680NVAPI_INTERFACE NvAPI_D3D12_QueryPresentBarrierSupport(__in ID3D12Device *pDevice, __out bool *pSupported);
11681#endif // defined(__cplusplus) && defined(__d3d12_h__)
11682
11685#if defined(__cplusplus) && defined(__d3d12_h__)
11687//
11688// FUNCTION NAME: NvAPI_D3D12_CreatePresentBarrierClient
11689//
11709NVAPI_INTERFACE NvAPI_D3D12_CreatePresentBarrierClient(__in ID3D12Device *pDevice,
11710 __in IDXGISwapChain *pSwapChain,
11711 __out NvPresentBarrierClientHandle *pPresentBarrierClient);
11712#endif // defined(__cplusplus) && defined(__d3d12_h__)
11713
11716#if defined(__cplusplus) && defined(__d3d12_h__)
11718//
11719// FUNCTION NAME: NvAPI_D3D12_RegisterPresentBarrierResources
11720//
11753NVAPI_INTERFACE NvAPI_D3D12_RegisterPresentBarrierResources(__in NvPresentBarrierClientHandle presentBarrierClient,
11754 __in ID3D12Fence *pFence,
11755 __in ID3D12Resource **ppResources,
11756 __in NvU32 numResources);
11757#endif // defined(__cplusplus) && defined(__d3d12_h__)
11758
11761#if defined(__cplusplus)
11763//
11764// FUNCTION NAME: NvAPI_DestroyPresentBarrierClient
11765//
11780NVAPI_INTERFACE NvAPI_DestroyPresentBarrierClient(__in NvPresentBarrierClientHandle presentBarrierClient);
11781#endif // defined(__cplusplus)
11782
11785#if defined(__cplusplus)
11786typedef struct _NV_JOIN_PRESENT_BARRIER_PARAMS
11787{
11788 NvU32 dwVersion;
11789} NV_JOIN_PRESENT_BARRIER_PARAMS;
11790
11792#define NV_JOIN_PRESENT_BARRIER_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_JOIN_PRESENT_BARRIER_PARAMS, 1)
11794//
11795// FUNCTION NAME: NvAPI_JoinPresentBarrier
11796//
11816NVAPI_INTERFACE NvAPI_JoinPresentBarrier(__in NvPresentBarrierClientHandle presentBarrierClient, __in NV_JOIN_PRESENT_BARRIER_PARAMS *pParams);
11817#endif // defined(__cplusplus)
11818
11821#if defined(__cplusplus)
11823//
11824// FUNCTION NAME: NvAPI_LeavePresentBarrier
11825//
11841NVAPI_INTERFACE NvAPI_LeavePresentBarrier(__in NvPresentBarrierClientHandle presentBarrierClient);
11842#endif // defined(__cplusplus)
11843
11846#if defined(__cplusplus)
11847
11848#define NV_PRESENT_BARRIER_FRAME_STATICS_VER1 MAKE_NVAPI_VERSION(NV_PRESENT_BARRIER_FRAME_STATISTICS,1)
11849
11850typedef enum _NV_PRESENT_BARRIER_SYNC_MODE
11851{
11852 PRESENT_BARRIER_NOT_JOINED = 0x00000000,
11853 PRESENT_BARRIER_SYNC_CLIENT = 0x00000001,
11856 PRESENT_BARRIER_SYNC_SYSTEM = 0x00000002,
11858 PRESENT_BARRIER_SYNC_CLUSTER = 0x00000003,
11860} NV_PRESENT_BARRIER_SYNC_MODE;
11861
11862typedef struct _NV_PRESENT_BARRIER_FRAME_STATISTICS
11863{
11864 NvU32 dwVersion;
11865 NV_PRESENT_BARRIER_SYNC_MODE SyncMode;
11866 NvU32 PresentCount;
11868 NvU32 PresentInSyncCount;
11874 NvU32 FlipInSyncCount;
11879 NvU32 RefreshCount;
11884} NV_PRESENT_BARRIER_FRAME_STATISTICS;
11885
11887//
11888// FUNCTION NAME: NvAPI_QueryPresentBarrierFrameStatistics
11889//
11911NVAPI_INTERFACE NvAPI_QueryPresentBarrierFrameStatistics(__in NvPresentBarrierClientHandle presentBarrierClient,
11912 __out NV_PRESENT_BARRIER_FRAME_STATISTICS *pFrameStats);
11913#endif // defined(__cplusplus)
11914
11917#if defined(__cplusplus) && defined(__d3d12_h__)
11919//
11920// FUNCTION NAME: NvAPI_D3D12_CreateDDisplayPresentBarrierClient
11921//
11941NVAPI_INTERFACE NvAPI_D3D12_CreateDDisplayPresentBarrierClient(__in ID3D12Device *pDevice, __in NvU32 sourceId, __out NvPresentBarrierClientHandle *pPresentBarrierClient);
11942#endif // defined(__cplusplus) && defined(__d3d12_h__)
11943
11946#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__) || defined(__d3d12_h__))
11947
11948enum NVAPI_QUAD_FILLMODE
11949{
11950 NVAPI_QUAD_FILLMODE_DISABLED = 0,
11951 NVAPI_QUAD_FILLMODE_BBOX = 1,
11952 NVAPI_QUAD_FILLMODE_FULL_VIEWPORT = 2,
11953};
11954
11955#endif //defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__) || defined(__d3d12_h__))
11956
11959#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
11960
11961typedef struct NvAPI_D3D11_RASTERIZER_DESC_EX
11962{
11963 // D3D11_RASTERIZER_DESC member variables
11964 D3D11_FILL_MODE FillMode;
11965 D3D11_CULL_MODE CullMode;
11966 BOOL FrontCounterClockwise;
11967 INT DepthBias;
11968 FLOAT DepthBiasClamp;
11969 FLOAT SlopeScaledDepthBias;
11970 BOOL DepthClipEnable;
11971 BOOL ScissorEnable;
11972 BOOL MultisampleEnable;
11973 BOOL AntialiasedLineEnable;
11974
11975 // NvAPI_D3D11_RASTERIZER_DESC_EX specific member variables
11976 NvU32 ForcedSampleCount; //<! Added DX 11.1, part of _DESC1 version of this struct.
11977 bool ProgrammableSamplePositionsEnable; //<! enable Programmable Samples feature
11978 bool InterleavedSamplingEnable; //<! when jitter is enabled, an app need to fill the whole arrays below, otherwise only as much entries as samples
11979 NvU8 SampleCount; //<! number of samples. In TIR N->1 it needs to match N, in non-TIR it needs to match RT sample count. Ignored if ForcePerSampleInterlock is set
11980 NvU8 SamplePositionsX[16]; //<! x positions in API sample order
11981 NvU8 SamplePositionsY[16]; //<! y positions in API sample order
11982 bool ConservativeRasterEnable; //<! rasterize all pixels a primitive touches in any way instead of just those with the centroid covered.
11983 NVAPI_QUAD_FILLMODE QuadFillMode; //<! Fill a triangle outside its bounds as a screen-aligned quad, matching the tri's bounding-box or filling the full viewport.
11984 bool PostZCoverageEnable; //<! Enable pixel-shader input SV_COVERAGE to account for z-test in early-z mode.
11985 bool CoverageToColorEnable; //<! Enable output of coverage to a color render-target.
11986 NvU8 CoverageToColorRTIndex; //<! Index of RT for coverage-to-color.
11987 bool TargetIndepentRasterWithDepth; //<! TargetIndepentRasterWithDepth = TRUE enables rasterezation mode where sample count of both raster and depth-stencil buffer are equal and do not match RT sample count.
11988 NvU8 reserved[63]; //<! reserved for expansion, set to zero.
11989} NvAPI_D3D11_RASTERIZER_DESC_EX;
11990
11992//
11993// FUNCTION NAME: NvAPI_D3D11_CreateRasterizerState
11994//
12013NVAPI_INTERFACE NvAPI_D3D11_CreateRasterizerState(__in ID3D11Device *pDevice,
12014 __in const NvAPI_D3D11_RASTERIZER_DESC_EX *pRasterizerDesc,
12015 __out ID3D11RasterizerState **ppRasterizerState);
12016
12017#endif //defined(__cplusplus) && defined(__d3d11_h__)
12018
12021
12022#if defined (__cplusplus) && (defined(_D3D9_H_) || defined(__d3d11_h__) || defined(__d3d11_1_h__) || defined(__d3d12_h__))
12023
12025//
12026// FUNCTION NAME: NvAPI_D3D_ConfigureAnsel
12027//
12039
12040typedef enum _NVAPI_ANSEL_FEATURE
12041{
12042 NVAPI_ANSEL_FEATURE_UNKNOWN = 0,
12043 NVAPI_ANSEL_FEATURE_BLACK_AND_WHITE = 1,
12044 NVAPI_ANSEL_FEATURE_HUDLESS = 2
12045} NVAPI_ANSEL_FEATURE;
12046
12047typedef enum _NVAPI_ANSEL_FEATURE_STATE
12048{
12049 NVAPI_ANSEL_FEATURE_STATE_UNKNOWN = 0,
12050 NVAPI_ANSEL_FEATURE_STATE_ENABLE = 1,
12051 NVAPI_ANSEL_FEATURE_STATE_DISABLE = 2
12052} NVAPI_ANSEL_FEATURE_STATE;
12053
12054typedef enum _NVAPI_ANSEL_HOTKEY_MODIFIER
12055{
12056 NVAPI_ANSEL_HOTKEY_MODIFIER_UNKNOWN = 0,
12057 NVAPI_ANSEL_HOTKEY_MODIFIER_CTRL = 1,
12058 NVAPI_ANSEL_HOTKEY_MODIFIER_SHIFT = 2,
12059 NVAPI_ANSEL_HOTKEY_MODIFIER_ALT = 3
12060} NVAPI_ANSEL_HOTKEY_MODIFIER;
12061
12062typedef struct NVAPI_ANSEL_FEATURE_CONFIGURATION_STRUCT {
12063 NVAPI_ANSEL_FEATURE featureId;
12064 NVAPI_ANSEL_FEATURE_STATE featureState;
12065 UINT hotkey;
12066} NVAPI_ANSEL_FEATURE_CONFIGURATION_STRUCT;
12067
12068typedef struct NVAPI_ANSEL_CONFIGURATION_STRUCT_V1 {
12069 NvU32 version;
12070 NVAPI_ANSEL_HOTKEY_MODIFIER hotkeyModifier;
12071 UINT keyEnable;
12072 UINT numAnselFeatures;
12073 NVAPI_ANSEL_FEATURE_CONFIGURATION_STRUCT * pAnselFeatures;
12074} NVAPI_ANSEL_CONFIGURATION_STRUCT_V1;
12075
12076typedef NVAPI_ANSEL_CONFIGURATION_STRUCT_V1 NVAPI_ANSEL_CONFIGURATION_STRUCT;
12077
12078#define NVAPI_ANSEL_CONFIGURATION_STRUCT_VER1 MAKE_NVAPI_VERSION(NVAPI_ANSEL_CONFIGURATION_STRUCT_V1,1)
12079#define NVAPI_ANSEL_CONFIGURATION_STRUCT_VER NVAPI_ANSEL_CONFIGURATION_STRUCT_VER1
12080
12081NVAPI_INTERFACE NvAPI_D3D_ConfigureAnsel(__in IUnknown *pDevice,
12082 __in NVAPI_ANSEL_CONFIGURATION_STRUCT *pNLSConfig);
12083
12084#endif //defined (__cplusplus) && (defined(_D3D9_H_) || defined(__d3d11_h__) || defined(__d3d11_1_h__) || defined(__d3d12_h__))
12085
12088
12089#if defined (__cplusplus) && defined(__d3d11_2_h__)
12090
12092//
12093// FUNCTION NAME: NvAPI_D3D11_CreateTiledTexture2DArray
12094//
12096//
12117
12127NVAPI_INTERFACE NvAPI_D3D11_CreateTiledTexture2DArray(__in ID3D11Device *pDevice,
12128 __in const D3D11_TEXTURE2D_DESC *pDesc,
12129 __in const D3D11_SUBRESOURCE_DATA *pInitialData,
12130 __out ID3D11Texture2D **ppTexture2D);
12131
12132#endif //defined(__cplusplus) && defined(__d3d11_2_h__)
12133
12136
12137#if defined (__cplusplus) && defined(__d3d11_h__)
12138
12139typedef enum _NV_D3D11_FEATURE
12140{
12141 NV_D3D11_FEATURE_RASTERIZER,
12142} NV_D3D11_FEATURE;
12143
12144typedef struct _NV_D3D11_FEATURE_DATA_RASTERIZER_SUPPORT
12145{
12146 BOOL TargetIndependentRasterWithDepth;
12147 BOOL ProgrammableSamplePositions;
12148 BOOL InterleavedSampling;
12149 BOOL ConservativeRaster;
12150 BOOL PostZCoverage;
12151 BOOL CoverageToColor;
12152} NV_D3D11_FEATURE_DATA_RASTERIZER_SUPPORT;
12153
12155//
12156// FUNCTION NAME: NvAPI_D3D11_CheckFeatureSupport
12157//
12175NVAPI_INTERFACE NvAPI_D3D11_CheckFeatureSupport(__in ID3D11Device *pDevice,
12176 __in NV_D3D11_FEATURE Feature,
12177 __out void *pFeatureSupportData,
12178 __in UINT FeatureSupportDataSize);
12179
12180#endif //defined(__cplusplus) && defined(__d3d11_h__)
12181
12184
12185#if defined (__cplusplus) && defined(__d3d11_h__)
12186
12188//
12189// FUNCTION NAME: NvAPI_D3D11_CreateImplicitMSAATexture2D
12190//
12192//
12214NVAPI_INTERFACE NvAPI_D3D11_CreateImplicitMSAATexture2D(__in ID3D11Device *pDevice,
12215 __in const D3D11_TEXTURE2D_DESC *pDesc,
12216 __out ID3D11Texture2D **ppTexture2D);
12217
12218#endif //defined(__cplusplus) && defined(__d3d11_h__)
12219
12222
12223#if defined (__cplusplus) && defined(__d3d12_h__)
12224
12226//
12227// FUNCTION NAME: NvAPI_D3D12_CreateImplicitMSAATexture2D
12228//
12230//
12252NVAPI_INTERFACE NvAPI_D3D12_CreateCommittedImplicitMSAATexture2D(
12253 __in ID3D12Device* pDevice,
12254 __in const D3D12_HEAP_PROPERTIES *pHeapProperties,
12255 D3D12_HEAP_FLAGS HeapFlags,
12256 __in const D3D12_RESOURCE_DESC *pDesc,
12257 D3D12_RESOURCE_STATES InitialResourceState,
12258 __in_opt const D3D12_CLEAR_VALUE *pOptimizedClearValue,
12259 REFIID riidResource,
12260 __out void **ppvResource);
12261
12262#endif //defined(__cplusplus) && defined(__d3d12_h__)
12263
12264
12267
12270typedef enum _NV_RESOLVE_MODE {
12271 NV_RESOLVE_MODE_SAMPLE_0,
12272} NV_RESOLVE_MODE;
12273
12274#if defined (__cplusplus) && defined(__d3d11_h__)
12275
12277//
12278// FUNCTION NAME: NvAPI_D3D11_ResolveSubresourceRegion
12279//
12281//
12308NVAPI_INTERFACE NvAPI_D3D11_ResolveSubresourceRegion(
12309 __in ID3D11Device *pDevice,
12310 __in ID3D11Texture2D *pDstResource,
12311 __in UINT DstSubresource,
12312 __in UINT DstX,
12313 __in UINT DstY,
12314 __in ID3D11Texture2D *pSrcResource,
12315 __in UINT SrcSubresource,
12316 __in_opt const RECT *pSrcRect,
12317 __in DXGI_FORMAT Format,
12318 __in NV_RESOLVE_MODE ResolveMode);
12319
12320#endif //defined(__cplusplus) && defined(__d3d11_h__)
12321
12324
12325#if defined (__cplusplus) && defined(__d3d12_h__)
12326
12328//
12329// FUNCTION NAME: NvAPI_D3D12_ResolveSubresourceRegion
12330//
12332//
12359NVAPI_INTERFACE NvAPI_D3D12_ResolveSubresourceRegion(
12360 __in ID3D12GraphicsCommandList1*pCommandList,
12361 __in ID3D12Resource *pDstResource,
12362 __in UINT DstSubresource,
12363 __in UINT DstX,
12364 __in UINT DstY,
12365 __in ID3D12Resource *pSrcResource,
12366 __in UINT SrcSubresource,
12367 __in_opt RECT *pSrcRect,
12368 __in DXGI_FORMAT Format,
12369 __in NV_RESOLVE_MODE ResolveMode);
12370
12371#endif //defined(__cplusplus) && defined(__d3d12_h__)
12372
12375
12376#if defined (__cplusplus) && defined(__d3d11_2_h__)
12377
12379//
12380// FUNCTION NAME: NvAPI_D3D11_TiledTexture2DArrayGetDesc
12381//
12383//
12393
12403NVAPI_INTERFACE NvAPI_D3D11_TiledTexture2DArrayGetDesc(__in ID3D11Texture2D *pTiledTexture2DArray,
12404 __out D3D11_TEXTURE2D_DESC *pDesc);
12405
12406#endif //defined(__cplusplus) && defined(__d3d11_2_h__)
12407
12410
12411#if defined (__cplusplus) && defined(__d3d11_2_h__)
12412
12414//
12415// FUNCTION NAME: NvAPI_D3D11_UpdateTileMappings
12416//
12418//
12434
12444NVAPI_INTERFACE NvAPI_D3D11_UpdateTileMappings(
12445 __in ID3D11DeviceContext2 *pDeviceContext,
12446 __in ID3D11Resource *pTiledResource,
12447 __in UINT NumTiledResourceRegions,
12448 __in const D3D11_TILED_RESOURCE_COORDINATE *pTiledResourceRegionStartCoordinates,
12449 __in const D3D11_TILE_REGION_SIZE *pTiledResourceRegionSizes,
12450 __in ID3D11Buffer *pTilePool,
12451 __in UINT NumRanges,
12452 __in const UINT *pRangeFlags,
12453 __in const UINT *pTilePoolStartOffsets,
12454 __in const UINT *pRangeTileCounts,
12455 __in UINT Flags);
12456
12457#endif //defined(__cplusplus) && defined(__d3d11_2_h__)
12458
12461
12462#if defined (__cplusplus) && defined(__d3d11_2_h__)
12463
12465//
12466// FUNCTION NAME: NvAPI_D3D11_CopyTileMappings
12467//
12469//
12482
12492NVAPI_INTERFACE NvAPI_D3D11_CopyTileMappings(
12493 __in ID3D11DeviceContext *pDeviceContext,
12494 __in ID3D11Resource *pDestTiledResource,
12495 __in const D3D11_TILED_RESOURCE_COORDINATE *pDestRegionStartCoordinate,
12496 __in ID3D11Resource *pSourceTiledResource,
12497 __in const D3D11_TILED_RESOURCE_COORDINATE *pSourceRegionStartCoordinate,
12498 __in const D3D11_TILE_REGION_SIZE *pTileRegionSize,
12499 __in UINT Flags);
12500
12501#endif //defined(__cplusplus) && defined(__d3d11_2_h__)
12502
12505
12506#if defined (__cplusplus) && defined(__d3d11_2_h__)
12507
12509//
12510// FUNCTION NAME: NvAPI_D3D11_TiledResourceBarrier
12511//
12513//
12522
12532NVAPI_INTERFACE NvAPI_D3D11_TiledResourceBarrier(
12533 __in ID3D11DeviceContext *pDeviceContext,
12534 __in ID3D11Resource *pTiledResourceAccessBeforeBarrier,
12535 __in ID3D11Resource *pTiledResourceAccessAfterBarrier);
12536
12537#endif //defined(__cplusplus) && defined(__d3d11_2_h__)
12538
12541
12542#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
12543
12545//
12546// FUNCTION NAME: NvAPI_D3D11_AliasMSAATexture2DAsNonMSAA
12547//
12569NVAPI_INTERFACE NvAPI_D3D11_AliasMSAATexture2DAsNonMSAA(__in ID3D11Device *pDevice,
12570 __in ID3D11Texture2D *pInputTex,
12571 __out ID3D11Texture2D **ppOutTex);
12572
12573#endif //defined(__cplusplus) && defined(__d3d11_h__)
12574
12575#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
12576typedef UINT NvAPI_D3D11_SWIZZLE_MODE;
12577
12578typedef enum _NV_SWIZZLE_MODE
12579{
12580 NV_SWIZZLE_POS_X = 0,
12581 NV_SWIZZLE_NEG_X = 1,
12582 NV_SWIZZLE_POS_Y = 2,
12583 NV_SWIZZLE_NEG_Y = 3,
12584 NV_SWIZZLE_POS_Z = 4,
12585 NV_SWIZZLE_NEG_Z = 5,
12586 NV_SWIZZLE_POS_W = 6,
12587 NV_SWIZZLE_NEG_W = 7
12588}NV_SWIZZLE_MODE;
12589
12590typedef enum _NV_SWIZZLE_OFFSET
12591{
12592 NV_SWIZZLE_OFFSET_X = 0,
12593 NV_SWIZZLE_OFFSET_Y = 4,
12594 NV_SWIZZLE_OFFSET_Z = 8,
12595 NV_SWIZZLE_OFFSET_W = 12
12596}NV_SWIZZLE_OFFSET;
12597
12598#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
12599
12602
12603#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
12604#define NV_CUSTOM_SEMANTIC_MAX_LIMIT 32
12605
12606typedef enum NV_CUSTOM_SEMANTIC_TYPE
12607{
12608 NV_NONE_SEMANTIC = 0,
12609 NV_X_RIGHT_SEMANTIC = 1,
12610 NV_VIEWPORT_MASK_SEMANTIC = 2,
12611 NV_XYZW_RIGHT_SEMANTIC = 3,
12612 NV_VIEWPORT_MASK_2_SEMANTIC = 4,
12613
12614 NV_POSITION_SEMANTIC = 5,
12615 NV_CLIP_DISTANCE_0_SEMANTIC = 6, // MultiView can accept upto two vec4 values. So the application should not use
12616 NV_CLIP_DISTANCE_1_SEMANTIC = 7, // more than 2 of the below Clip / Cull semantics in a single shader.
12617 NV_CULL_DISTANCE_0_SEMANTIC = 8,
12618 NV_CULL_DISTANCE_1_SEMANTIC = 9,
12619 NV_GENERIC_ATTRIBUTE_SEMANTIC = 10,
12620
12621 NV_PACKED_EYE_INDEX_SEMANTIC = 17,
12622 NV_CUSTOM_SEMANTIC_MAX = NV_CUSTOM_SEMANTIC_MAX_LIMIT,
12623} NV_CUSTOM_SEMANTIC_TYPE;
12624
12625typedef struct _NV_CUSTOM_SEMANTIC
12626{
12627 UINT version; // NV_CUSTOM_SEMANTIC_VERSION
12628
12629 NV_CUSTOM_SEMANTIC_TYPE NVCustomSemanticType; // type of custom semantic (NV_CUSTOM_SEMANTIC_TYPE)
12630 NvAPI_LongString NVCustomSemanticNameString; // name of custom semantic e.g. "NV_X_RIGHT", "NV_VIEWPORT_MASK"
12631 BOOL RegisterSpecified; // (optional) set to TRUE to explicitly provide register number and mask as below
12632 NvU32 RegisterNum; // (optional) output register which has the custom semantic.
12633 NvU32 RegisterMask; // (optional) output register component mask which has the custom semantic (X:1, Y:2, Z:4)
12634 NvU32 Reserved; // reserved
12635} NV_CUSTOM_SEMANTIC;
12636
12637#define NV_CUSTOM_SEMANTIC_VERSION MAKE_NVAPI_VERSION(NV_CUSTOM_SEMANTIC, 1)
12638
12639#endif //defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
12640
12641#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
12642
12643typedef struct NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX_V5
12644{
12645 UINT version;
12646
12647 BOOL UseViewportMask;
12648 BOOL OffsetRtIndexByVpIndex;
12649 BOOL ForceFastGS;
12650 BOOL DontUseViewportOrder;
12651 BOOL UseAttributeSkipMask;
12652 BOOL UseCoordinateSwizzle;
12653 NvAPI_D3D11_SWIZZLE_MODE *pCoordinateSwizzling;
12654
12655 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12656 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12657 BOOL ConvertToFastGS; // reserved
12658 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
12659} NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX_V5;
12660
12661typedef NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX_V5 NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX;
12662#define NVAPI_D3D11_CREATEGEOMETRYSHADEREX_2_VER_5 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX_V5, 5)
12663#define NVAPI_D3D11_CREATEGEOMETRYSHADEREX_2_VERSION NVAPI_D3D11_CREATEGEOMETRYSHADEREX_2_VER_5
12664
12666//
12667// FUNCTION NAME: NvAPI_D3D11_CreateGeometryShaderEx
12668//
12711//
12713
12714NVAPI_INTERFACE NvAPI_D3D11_CreateGeometryShaderEx_2(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
12715 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
12716 __in const NvAPI_D3D11_CREATE_GEOMETRY_SHADER_EX *pCreateGeometryShaderExArgs,
12717 __out ID3D11GeometryShader **ppGeometryShader);
12718
12719#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
12720
12723
12724#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE) )
12725
12726typedef struct NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V1
12727{
12728 UINT version;
12729
12730 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12731 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12732} NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V1;
12733
12734typedef struct NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V2
12735{
12736 UINT version;
12737
12738 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12739 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12740 BOOL UseWithFastGS; // reserved
12741} NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V2;
12742
12743typedef struct NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V3
12744{
12745 UINT version;
12746
12747 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12748 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12749 BOOL UseWithFastGS; // reserved
12750 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
12751} NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V3;
12752
12753typedef NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V3 NvAPI_D3D11_CREATE_VERTEX_SHADER_EX;
12754#define NVAPI_D3D11_CREATEVERTEXSHADEREX_VER_1 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V1, 1)
12755#define NVAPI_D3D11_CREATEVERTEXSHADEREX_VER_2 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V2, 2)
12756#define NVAPI_D3D11_CREATEVERTEXSHADEREX_VER_3 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_VERTEX_SHADER_EX_V2, 3)
12757#define NVAPI_D3D11_CREATEVERTEXSHADEREX_VERSION NVAPI_D3D11_CREATEVERTEXSHADEREX_VER_3
12758
12760//
12761// FUNCTION NAME: NvAPI_D3D11_CreateVertexShaderEx
12762//
12792//
12794
12795NVAPI_INTERFACE NvAPI_D3D11_CreateVertexShaderEx(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
12796 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
12797 __in const NvAPI_D3D11_CREATE_VERTEX_SHADER_EX *pCreateVertexShaderExArgs,
12798 __out ID3D11VertexShader **ppVertexShader);
12799
12800#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
12801
12804
12805#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE) )
12806
12807typedef struct NvAPI_D3D11_CREATE_HULL_SHADER_EX_V1
12808{
12809 UINT version;
12810
12811 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12812 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12813 BOOL UseWithFastGS; // reserved
12814} NvAPI_D3D11_CREATE_HULL_SHADER_EX_V1;
12815
12816typedef struct NvAPI_D3D11_CREATE_HULL_SHADER_EX_V2
12817{
12818 UINT version;
12819
12820 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12821 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12822 BOOL UseWithFastGS; // reserved
12823 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
12824} NvAPI_D3D11_CREATE_HULL_SHADER_EX_V2;
12825
12826typedef NvAPI_D3D11_CREATE_HULL_SHADER_EX_V2 NvAPI_D3D11_CREATE_HULL_SHADER_EX;
12827#define NVAPI_D3D11_CREATEHULLSHADEREX_VER_1 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_HULL_SHADER_EX_V1, 1)
12828#define NVAPI_D3D11_CREATEHULLSHADEREX_VER_2 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_HULL_SHADER_EX_V1, 2)
12829#define NVAPI_D3D11_CREATEHULLSHADEREX_VERSION NVAPI_D3D11_CREATEHULLSHADEREX_VER_2
12830
12832//
12833// FUNCTION NAME: NvAPI_D3D11_CreateHullShaderEx
12834//
12864//
12866
12867NVAPI_INTERFACE NvAPI_D3D11_CreateHullShaderEx(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
12868 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
12869 __in const NvAPI_D3D11_CREATE_HULL_SHADER_EX *pCreateHullShaderExArgs,
12870 __out ID3D11HullShader **ppHullShader);
12871
12872#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
12873
12876
12877#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE) )
12878
12879typedef struct NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V1
12880{
12881 UINT version;
12882
12883 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12884 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12885} NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V1;
12886
12887typedef struct NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V2
12888{
12889 UINT version;
12890
12891 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12892 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12893 BOOL UseWithFastGS; // reserved
12894} NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V2;
12895
12896typedef struct NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V3
12897{
12898 UINT version;
12899
12900 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12901 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12902 BOOL UseWithFastGS; // reserved
12903 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
12904} NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V3;
12905
12906typedef NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V3 NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX;
12907#define NVAPI_D3D11_CREATEDOMAINSHADEREX_VER_1 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V1, 1)
12908#define NVAPI_D3D11_CREATEDOMAINSHADEREX_VER_2 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V2, 2)
12909#define NVAPI_D3D11_CREATEDOMAINSHADEREX_VER_3 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX_V3, 3)
12910#define NVAPI_D3D11_CREATEDOMAINSHADEREX_VERSION NVAPI_D3D11_CREATEDOMAINSHADEREX_VER_3
12911
12913//
12914// FUNCTION NAME: NvAPI_D3D11_CreateDomainShaderEx
12915//
12945//
12947
12948NVAPI_INTERFACE NvAPI_D3D11_CreateDomainShaderEx(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
12949 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
12950 __in const NvAPI_D3D11_CREATE_DOMAIN_SHADER_EX *pCreateDomainShaderExArgs,
12951 __out ID3D11DomainShader **ppDomainShader);
12952
12953#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
12954
12957
12958#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE) )
12959
12960typedef struct NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V1
12961{
12962 UINT version;
12963
12964 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12965 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12966} NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V1;
12967
12968#define NVAPI_D3D11_CREATEPIXELSHADEREX_VER_1 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V1, 1)
12969
12970typedef struct NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V2
12971{
12972 UINT version; // Always use NVAPI_D3D11_CREATEPIXELSHADEREX_VERSION
12973
12974 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
12975 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
12976 NvU32 bEnableSuperSamplingPredicationForVRS : 1; // This enables sampling within a pixel for SuperSampling mode of Variable Rate Shading for relevant attributes tagged with "sample" modifier
12977 NvU32 bEnableSuperSamplingPredicationForVRSAllAttributes : 1; // This enables sampling within a pixel for SuperSampling mode of Variable Rate Shading for all relevant attributes
12978 NvU32 reserved : 30; // Reserved for further use
12979} NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V2;
12980
12981typedef NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V2 NvAPI_D3D11_CREATE_PIXEL_SHADER_EX;
12982#define NVAPI_D3D11_CREATEPIXELSHADEREX_VER_2 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_PIXEL_SHADER_EX_V2, 2)
12983#define NVAPI_D3D11_CREATEPIXELSHADEREX_VERSION NVAPI_D3D11_CREATEPIXELSHADEREX_VER_2
12984
12986//
12987// FUNCTION NAME: NvAPI_D3D11_CreatePixelShaderEx_2
12988//
13016//
13018
13019NVAPI_INTERFACE NvAPI_D3D11_CreatePixelShaderEx_2(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
13020 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
13021 __in const NvAPI_D3D11_CREATE_PIXEL_SHADER_EX *pCreatePixelShaderExArgs,
13022 __out ID3D11PixelShader **ppPixelShader);
13023
13024#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
13025
13028
13029#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
13030
13031typedef enum _NV_FASTGS_FLAGS
13032{
13033 NV_FASTGS_USE_VIEWPORT_MASK = 0x01, // Causes SV_ViewportArrayIndex value to be interpreted as a bitmask of viewports to broadcast to.
13034 NV_FASTGS_OFFSET_RT_INDEX_BY_VP_INDEX = 0x02, // Causes SV_RenderTargetArrayIndex value to be offset by the viewport index when broadcasting.
13035 NV_FASTGS_STRICT_API_ORDER = 0x04, // Causes broadcast primitives to be rendered strictly in API order (slow).
13036 // By default, primitives may be batched per viewport to improve performance.
13037} NV_FASTGS_FLAGS;
13038
13039#endif //defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__)) && (!defined(CINTERFACE))
13040
13041#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
13042
13043struct NvAPI_D3D11_CREATE_FASTGS_EXPLICIT_DESC_V1
13044{
13045 NvU32 version; // ALWAYS == NVAPI_D3D11_CREATEFASTGSEXPLICIT_VER
13046 NvU32 flags; // A combination of flags from NV_FASTGS_FLAGS
13047 NvAPI_D3D11_SWIZZLE_MODE *pCoordinateSwizzling; // [optional] Array of 16 coordinate swizzle modes, one per viewport. NULL if not used.
13048 // The output x, y, z, and w coordinates of all vertices can be set to any of the coordinates or their
13049 // negated versions i.e. {x, y, z, w, -x, -y, -z, -w}. Coordinates are swizzled before any viewport
13050 // operation occurs i.e. before frustum clipping, scaling, and viewport clipping. And after
13051 // last of vertex/tesselation/geometry shader stage, stream-out and viewport broadcast expansion (see NV_FASTGS_USE_VIEWPORT_MASK)
13052 // pCoordinateSwizzling[i] sets the swizzle-mode of each component for viewport i.
13053 // See NV_SWIZZLE_MODE for values of allowed swizzle modes.
13054 // See NV_SWIZZLE_OFFSET for bit offset from where NV_SWIZZLE_MODE to be set for each component.
13055 // For example :
13056 // 1. To set swizzle for viewport 0 such that - w and z are unchanged and values of x and y are swapped :
13057 // pCoordinateSwizzling[0] = (NV_SWIZZLE_POS_W << NV_SWIZZLE_OFFSET_W) |
13058 // (NV_SWIZZLE_POS_Z << NV_SWIZZLE_OFFSET_Z) |
13059 // (NV_SWIZZLE_POS_X << NV_SWIZZLE_OFFSET_Y) |
13060 // (NV_SWIZZLE_POS_Y << NV_SWIZZLE_OFFSET_X);
13061 // 2. To set swizzle for viewport 0 such that - w, z and y are unchanged and value of x is negated :
13062 // pCoordinateSwizzling[0] = (NV_SWIZZLE_POS_W << NV_SWIZZLE_OFFSET_W) |
13063 // (NV_SWIZZLE_POS_Z << NV_SWIZZLE_OFFSET_Z) |
13064 // (NV_SWIZZLE_POS_Y << NV_SWIZZLE_OFFSET_Y) |
13065 // (NV_SWIZZLE_NEG_X << NV_SWIZZLE_OFFSET_X);
13066 // Need to set some valid combination of swizzle-modes for all viewports, irrespective of whether that viewport is set.
13067 // Invalid swizzle-mode for any viewport (even if that viewport is not set) may result in removal of device.
13068};
13069
13070#define NVAPI_D3D11_CREATEFASTGSEXPLICIT_VER1 MAKE_NVAPI_VERSION(NvAPI_D3D11_CREATE_FASTGS_EXPLICIT_DESC_V1, 1)
13071#define NVAPI_D3D11_CREATEFASTGSEXPLICIT_VER NVAPI_D3D11_CREATEFASTGSEXPLICIT_VER1
13072
13073typedef NvAPI_D3D11_CREATE_FASTGS_EXPLICIT_DESC_V1 NvAPI_D3D11_CREATE_FASTGS_EXPLICIT_DESC;
13074
13076//
13077// FUNCTION NAME: NvAPI_D3D11_CreateFastGeometryShaderExplicit
13078//
13111//
13113
13114NVAPI_INTERFACE NvAPI_D3D11_CreateFastGeometryShaderExplicit(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
13115 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
13116 __in const NvAPI_D3D11_CREATE_FASTGS_EXPLICIT_DESC *pCreateFastGSArgs,
13117 __out ID3D11GeometryShader **ppGeometryShader);
13118
13119#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
13120
13123
13124#if defined (__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE) )
13126//
13127// FUNCTION NAME: NvAPI_D3D11_CreateFastGeometryShader
13128//
13156//
13158
13159NVAPI_INTERFACE NvAPI_D3D11_CreateFastGeometryShader(__in ID3D11Device *pDevice, __in const void *pShaderBytecode,
13160 __in SIZE_T BytecodeLength, __in_opt ID3D11ClassLinkage *pClassLinkage,
13161 __out ID3D11GeometryShader **ppGeometryShader);
13162
13163#endif //defined(__cplusplus) && defined(__d3d11_h__) && (!defined(CINTERFACE))
13164
13167
13168#if defined (__cplusplus) && defined(__d3d11_h__)
13169
13171//
13172// FUNCTION NAME: NvAPI_D3D11_DecompressView
13173//
13191NVAPI_INTERFACE NvAPI_D3D11_DecompressView(__in ID3D11Device* pDevice, __in ID3D11DeviceContext *pDeviceContext, __in ID3D11View* pView);
13192
13193#endif //defined(__cplusplus) && defined(__d3d11_h__)
13194
13195
13196#if defined (__cplusplus) && defined(__d3d12_h__)
13197
13201typedef enum _NV_PSO_EXTENSION
13202{
13203 NV_PSO_RASTER_EXTENSION = 0,
13204 NV_PSO_REQUEST_FASTGS_EXTENSION = 1,
13205 NV_PSO_GEOMETRY_SHADER_EXTENSION = 2,
13206 NV_PSO_ENABLE_DEPTH_BOUND_TEST_EXTENSION = 3,
13207 NV_PSO_EXPLICIT_FASTGS_EXTENSION = 4,
13208 NV_PSO_SET_SHADER_EXTNENSION_SLOT_AND_SPACE = 5,
13209 NV_PSO_SET_SHADER_EXTENSION_SLOT_AND_SPACE = 5,
13210 NV_PSO_VERTEX_SHADER_EXTENSION = 6,
13211 NV_PSO_DOMAIN_SHADER_EXTENSION = 7,
13212 NV_PSO_HULL_SHADER_EXTENSION = 9,
13213}NV_PSO_EXTENSION;
13214
13215struct NVAPI_D3D12_PSO_EXTENSION_DESC_V1
13216{
13217 NvU32 baseVersion; //<! Always use NV_PSO_EXTENSION_DESC_VER
13218 NV_PSO_EXTENSION psoExtension;
13219};
13220
13221#define NV_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_EXTENSION_DESC_V1, 1)
13222#define NV_PSO_EXTENSION_DESC_VER NV_PSO_EXTENSION_DESC_VER_1
13223
13224typedef NVAPI_D3D12_PSO_EXTENSION_DESC_V1 NVAPI_D3D12_PSO_EXTENSION_DESC;
13225
13226
13227struct NVAPI_D3D12_PSO_RASTERIZER_STATE_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13228{
13229 NvU32 version; //<! Always use NV_RASTERIZER_PSO_EXTENSION_DESC_VER
13230 // These are additional parameters on the top of D3D12_RASTERIZER_DESC
13231 bool ProgrammableSamplePositionsEnable; //<! enable Programmable Samples feature
13232 bool InterleavedSamplingEnable; //<! when jitter is enabled, an app need to fill the whole arrays below, otherwise only as much entries as samples
13233 NvU8 SampleCount; //<! number of samples. In TIR N->1 it needs to match N, in non-TIR it needs to match RT sample count. Ignored if ForcePerSampleInterlock is set
13234 NvU8 SamplePositionsX[16]; //<! x positions in API sample order
13235 NvU8 SamplePositionsY[16]; //<! y positions in API sample order
13236 NVAPI_QUAD_FILLMODE QuadFillMode; //<! Fill a triangle outside its bounds as a screen-aligned quad, matching the tri's bounding-box or filling the full viewport.
13237 bool PostZCoverageEnable; //<! Enable pixel-shader input SV_COVERAGE to account for z-test in early-z mode.
13238 bool CoverageToColorEnable; //<! Enable output of coverage to a color render-target.
13239 NvU8 CoverageToColorRTIndex; //<! Index of RT for coverage-to-color.
13240
13241 //Added with NV_RASTERIZER_PSO_EXTENSION_DESC_VER_2
13242 bool TargetIndepentRasterWithDepth; //<! TargetIndepentRasterWithDepth = TRUE enables rasterezation mode where sample count of both raster and depth-stencil buffer are equal and do not match RT sample count.
13243 NvU8 ForcedSampleCount; //<! Must be set when TargetIndepentRasterWithDepth is true - refers to SampleDesc.Count for the DSV
13244
13245 //Reserved
13246 NvU8 reserved[62]; //<! reserved for expansion, set to zero.
13247};
13248
13249#define NV_RASTERIZER_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_RASTERIZER_STATE_DESC_V1, 1)
13250#define NV_RASTERIZER_PSO_EXTENSION_DESC_VER_2 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_RASTERIZER_STATE_DESC_V1, 2)
13251#define NV_RASTERIZER_PSO_EXTENSION_DESC_VER NV_RASTERIZER_PSO_EXTENSION_DESC_VER_2
13252
13253typedef NVAPI_D3D12_PSO_RASTERIZER_STATE_DESC_V1 NVAPI_D3D12_PSO_RASTERIZER_STATE_DESC;
13254
13255struct NVAPI_D3D12_PSO_CREATE_FASTGS_EXPLICIT_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13256{
13257 NvU32 version; // ALWAYS == NV_FASTGS_EXPLICIT_PSO_EXTENSION_VER
13258 NvU32 flags; // A combination of flags from NV_FASTGS_FLAGS
13259 NvAPI_D3D11_SWIZZLE_MODE *pCoordinateSwizzling; // [optional] Array of 16 coordinate swizzle modes, one per viewport. NULL if not used.
13260 // The output x, y, z, and w coordinates of all vertices can be set to any of the coordinates or their
13261 // negated versions i.e. {x, y, z, w, -x, -y, -z, -w}. Coordinates are swizzled before any viewport
13262 // operation occurs i.e. before frustum clipping, scaling, and viewport clipping. And after
13263 // last of vertex/tesselation/geometry shader stage, stream-out and viewport broadcast expansion (see NV_FASTGS_USE_VIEWPORT_MASK)
13264 // pCoordinateSwizzling[i] sets the swizzle-mode of each component for viewport i.
13265 // See NV_SWIZZLE_MODE for values of allowed swizzle modes.
13266 // See NV_SWIZZLE_OFFSET for bit offset from where NV_SWIZZLE_MODE to be set for each component.
13267 // For example :
13268 // 1. To set swizzle for viewport 0 such that - w and z are unchanged and values of x and y are swapped :
13269 // pCoordinateSwizzling[0] = (NV_SWIZZLE_POS_W << NV_SWIZZLE_OFFSET_W) |
13270 // (NV_SWIZZLE_POS_Z << NV_SWIZZLE_OFFSET_Z) |
13271 // (NV_SWIZZLE_POS_X << NV_SWIZZLE_OFFSET_Y) |
13272 // (NV_SWIZZLE_POS_Y << NV_SWIZZLE_OFFSET_X);
13273 // 2. To set swizzle for viewport 0 such that - w, z and y are unchanged and value of x is negated :
13274 // pCoordinateSwizzling[0] = (NV_SWIZZLE_POS_W << NV_SWIZZLE_OFFSET_W) |
13275 // (NV_SWIZZLE_POS_Z << NV_SWIZZLE_OFFSET_Z) |
13276 // (NV_SWIZZLE_POS_Y << NV_SWIZZLE_OFFSET_Y) |
13277 // (NV_SWIZZLE_NEG_X << NV_SWIZZLE_OFFSET_X);
13278 // Need to set some valid combination of swizzle-modes for all viewports, irrespective of whether that viewport is set.
13279 // Invalid swizzle-mode for any viewport (even if that viewport is not set) may result in removal of device.
13280};
13281
13282#define NV_FASTGS_EXPLICIT_PSO_EXTENSION_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_CREATE_FASTGS_EXPLICIT_DESC_V1, 1)
13283#define NV_FASTGS_EXPLICIT_PSO_EXTENSION_VER NV_FASTGS_EXPLICIT_PSO_EXTENSION_VER_1
13284
13285typedef NVAPI_D3D12_PSO_CREATE_FASTGS_EXPLICIT_DESC_V1 NVAPI_D3D12_PSO_CREATE_FASTGS_EXPLICIT_DESC;
13286
13287
13288struct NVAPI_D3D12_PSO_REQUEST_FAST_GEOMETRY_SHADER_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13289{
13290 NvU32 version; //<! Always use NV_FAST_GEOMETRY_SHADER_PSO_EXTENSION_VER
13291};
13292
13293#define NV_FAST_GEOMETRY_SHADER_PSO_EXTENSION_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_REQUEST_FAST_GEOMETRY_SHADER_DESC_V1, 1)
13294#define NV_FAST_GEOMETRY_SHADER_PSO_EXTENSION_VER NV_FAST_GEOMETRY_SHADER_PSO_EXTENSION_VER_1
13295
13296typedef NVAPI_D3D12_PSO_REQUEST_FAST_GEOMETRY_SHADER_DESC_V1 NVAPI_D3D12_PSO_REQUEST_FAST_GEOMETRY_SHADER_DESC;
13297
13298
13299struct NVAPI_D3D12_PSO_GEOMETRY_SHADER_DESC_V5 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13300{
13301 NvU32 version; //<! Always use NV_GEOMETRY_SHADER_PSO_EXTENSION_DESC_VER
13302
13303 BOOL UseViewportMask; // Set to FALSE for custom semantic shaders. Tell the driver to create a shader that outputs the viewport mask in lieu of the viewport index. See above description.
13304 BOOL OffsetRtIndexByVpIndex; // Set to FALSE for custom semantic shaders. The Rendertarget index is offset by the viewport index
13305 BOOL ForceFastGS; // If TRUE, GS must be written with maxvertexcount(1) and must pass-through input vertex 0 to the output without modification
13306 BOOL DontUseViewportOrder; // Default FALSE for Primitives batched per viewport to improve performance. Set TRUE for API order (slow).
13307 BOOL UseAttributeSkipMask; // Reserved
13308 BOOL UseCoordinateSwizzle; // Reserved
13309 NvAPI_D3D11_SWIZZLE_MODE *pCoordinateSwizzling; // Reserved
13310
13311 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
13312 NV_CUSTOM_SEMANTIC *pCustomSemantics; // pointer to array of NV_CUSTOM_SEMANTIC
13313
13314 BOOL ConvertToFastGS; // Tell the driver to attempt to create a fast geometry shader
13315
13316 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
13317};
13318
13319#define NV_GEOMETRY_SHADER_PSO_EXTENSION_DESC_VER_5 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_GEOMETRY_SHADER_DESC_V5, 5)
13320#define NV_GEOMETRY_SHADER_PSO_EXTENSION_DESC_VER NV_GEOMETRY_SHADER_PSO_EXTENSION_DESC_VER_5
13321
13322typedef NVAPI_D3D12_PSO_GEOMETRY_SHADER_DESC_V5 NVAPI_D3D12_PSO_GEOMETRY_SHADER_DESC;
13323
13324
13325struct NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13326{
13327 NvU32 version; //<! Always use NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER
13328
13329 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
13330 NV_CUSTOM_SEMANTIC *pCustomSemantics; // Pointer to array of NV_CUSTOM_SEMANTIC
13331};
13332
13333struct NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V2 : public NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V1
13334{
13335 BOOL UseWithFastGS; // Reserved
13336};
13337
13338struct NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V3 : public NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V2
13339{
13340 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with NvAPI shader extensions
13341};
13342
13343#define NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V1, 1)
13344#define NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER_2 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V2, 2)
13345#define NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER_3 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V3, 3)
13346#define NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER NV_VERTEX_SHADER_PSO_EXTENSION_DESC_VER_3
13347
13348typedef NVAPI_D3D12_PSO_VERTEX_SHADER_DESC_V3 NVAPI_D3D12_PSO_VERTEX_SHADER_DESC;
13349
13350
13351struct NVAPI_D3D12_PSO_HULL_SHADER_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13352{
13353 NvU32 version; //<! Always use NV_HULL_SHADER_PSO_EXTENSION_DESC_VER
13354
13355 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
13356 NV_CUSTOM_SEMANTIC *pCustomSemantics; // Pointer to array of NV_CUSTOM_SEMANTIC
13357 BOOL UseWithFastGS; // Reserved
13358};
13359
13360struct NVAPI_D3D12_PSO_HULL_SHADER_DESC_V2 : public NVAPI_D3D12_PSO_HULL_SHADER_DESC_V1
13361{
13362 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with nvapi shader extensions
13363};
13364
13365#define NV_HULL_SHADER_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_HULL_SHADER_DESC_V1, 1)
13366#define NV_HULL_SHADER_PSO_EXTENSION_DESC_VER_2 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_HULL_SHADER_DESC_V2, 2)
13367#define NV_HULL_SHADER_PSO_EXTENSION_DESC_VER NV_HULL_SHADER_PSO_EXTENSION_DESC_VER_2
13368
13369typedef NVAPI_D3D12_PSO_HULL_SHADER_DESC_V2 NVAPI_D3D12_PSO_HULL_SHADER_DESC;
13370
13371
13372struct NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13373{
13374 NvU32 version; //<! Always use NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER
13375
13376 NvU32 NumCustomSemantics; // Number of custom semantics elements (upto NV_CUSTOM_SEMANTIC_MAX) provided in array pointer pCustomSemantics
13377 NV_CUSTOM_SEMANTIC *pCustomSemantics; // Pointer to array of NV_CUSTOM_SEMANTIC
13378};
13379
13380struct NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V2 : public NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V1
13381{
13382 BOOL UseWithFastGS; // Reserved
13383};
13384
13385struct NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V3 : public NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V2
13386{
13387 BOOL UseSpecificShaderExt; // TRUE if creating minimal specific shaders with NvAPI shader extensions
13388};
13389
13390#define NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V1, 1)
13391#define NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER_2 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V2, 2)
13392#define NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER_3 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V3, 3)
13393#define NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER NV_DOMAIN_SHADER_PSO_EXTENSION_DESC_VER_3
13394
13395typedef NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC_V3 NVAPI_D3D12_PSO_DOMAIN_SHADER_DESC;
13396
13397
13398struct NVAPI_D3D12_PSO_ENABLE_DEPTH_BOUND_TEST_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13399{
13400 NvU32 version; //<! Always use NV_ENABLE_DEPTH_BOUND_TEST_PSO_EXTENSION_DESC_VER
13401 bool EnableDBT;
13402};
13403
13404#define NV_ENABLE_DEPTH_BOUND_TEST_PSO_EXTENSION_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_ENABLE_DEPTH_BOUND_TEST_DESC_V1, 1)
13405#define NV_ENABLE_DEPTH_BOUND_TEST_PSO_EXTENSION_DESC_VER NV_ENABLE_DEPTH_BOUND_TEST_PSO_EXTENSION_DESC_VER_1
13406
13407typedef NVAPI_D3D12_PSO_ENABLE_DEPTH_BOUND_TEST_DESC_V1 NVAPI_D3D12_PSO_ENABLE_DEPTH_BOUND_TEST_DESC;
13408
13409
13410struct NVAPI_D3D12_PSO_SET_SHADER_EXTENSION_SLOT_DESC_V1 : public NVAPI_D3D12_PSO_EXTENSION_DESC
13411{
13412 NvU32 version; //<! Always use NV_SET_SHADER_EXTENSION_SLOT_DESC_VER
13413 NvU32 uavSlot;
13414 NvU32 registerSpace;
13415};
13416
13417#define NV_SET_SHADER_EXTENSION_SLOT_DESC_VER_1 MAKE_NVAPI_VERSION(NVAPI_D3D12_PSO_SET_SHADER_EXTENSION_SLOT_DESC_V1, 1)
13418#define NV_SET_SHADER_EXTENSION_SLOT_DESC_VER NV_SET_SHADER_EXTENSION_SLOT_DESC_VER_1
13419
13420typedef NVAPI_D3D12_PSO_SET_SHADER_EXTENSION_SLOT_DESC_V1 NVAPI_D3D12_PSO_SET_SHADER_EXTENSION_SLOT_DESC;
13421
13422
13425typedef enum _NV_COMPUTE_SHADER_DERIVATIVES
13426{
13427 NV_COMPUTE_SHADER_DERIVATIVE_NONE = 0, // No support for compute derivatives
13428
13429 NV_COMPUTE_SHADER_DERIVATIVE_GROUP_LINEAR = 1, // Compute derivatives supported. Quads are defined as groups of four threads with linear thread IDs of the form 4N..4N + 3
13430
13431 NV_COMPUTE_SHADER_DERIVATIVE_GROUP_QUADS = 2, // Compute derivatives supported. Quads are defined as group of 2x2 thread IDs in a 2D (or 3D) CTA. In this mode
13432 // the app must ensure that width and height of the CTA dimension are both multiples of 2
13433} NV_COMPUTE_SHADER_DERIVATIVES;
13434
13436//
13437// FUNCTION NAME: NvAPI_D3D12_CreateGraphicsPipelineState
13438//
13457
13458NVAPI_INTERFACE NvAPI_D3D12_CreateGraphicsPipelineState(__in ID3D12Device *pDevice,
13459 __in const D3D12_GRAPHICS_PIPELINE_STATE_DESC *pPSODesc,
13460 NvU32 numExtensions,
13461 __in const NVAPI_D3D12_PSO_EXTENSION_DESC** ppExtensions,
13462 __out ID3D12PipelineState **ppPSO);
13463
13464#endif //defined(__cplusplus) && defined(__d3d12_h__)
13465
13466
13467#if defined (__cplusplus) && defined(__d3d12_h__)
13469//
13470// FUNCTION NAME: NvAPI_D3D12_CreateComputePipelineState
13471//
13489
13490NVAPI_INTERFACE NvAPI_D3D12_CreateComputePipelineState(__in ID3D12Device *pDevice,
13491 __in const D3D12_COMPUTE_PIPELINE_STATE_DESC *pPSODesc,
13492 NvU32 numExtensions,
13493 __in const NVAPI_D3D12_PSO_EXTENSION_DESC** ppExtensions,
13494 __out ID3D12PipelineState **ppPSO);
13495
13496#endif //defined(__cplusplus) && defined(__d3d12_h__)
13497
13498
13499#if defined (__cplusplus) && defined(__d3d12_h__)
13501//
13502// FUNCTION NAME: NvAPI_D3D12_SetDepthBoundsTestValues
13503//
13521
13522NVAPI_INTERFACE NvAPI_D3D12_SetDepthBoundsTestValues(__in ID3D12GraphicsCommandList *pCommandList,
13523 __in const float minDepth,
13524 __in const float maxDepth);
13525
13526#endif //defined(__cplusplus) && defined(__d3d12_h__)
13527
13528
13529#if defined (__cplusplus) && defined(__d3d12_h__)
13531//
13532// FUNCTION NAME: NvAPI_D3D12_CreateReservedResource
13533//
13535//
13575
13576NVAPI_INTERFACE NvAPI_D3D12_CreateReservedResource(__in ID3D12Device *pDevice,
13577 __in const D3D12_RESOURCE_DESC *pDesc,
13578 __in D3D12_RESOURCE_STATES InitialState,
13579 __in const D3D12_CLEAR_VALUE *pOptimizedClearValue,
13580 __in REFIID riid,
13581 __out void **ppvResource,
13582 __in bool bTexture2DArrayMipPack,
13583 __in ID3D12Heap *pHeap);
13584
13585#endif //defined(__cplusplus) && defined(__d3d12_h__)
13586
13587
13588#if defined (__cplusplus) && defined(__d3d12_h__)
13590//
13591// FUNCTION NAME: NvAPI_D3D12_CreateHeap
13592//
13594//
13614
13615NVAPI_INTERFACE NvAPI_D3D12_CreateHeap(__in ID3D12Device *pDevice,
13616 __in const D3D12_HEAP_DESC *pDesc,
13617 __in REFIID riid,
13618 __out void **ppvHeap);
13619
13620#endif //defined(__cplusplus) && defined(__d3d12_h__)
13621
13622
13623#if defined (__cplusplus) && defined(__d3d12_h__)
13625//
13626// FUNCTION NAME: NvAPI_D3D12_CreateHeap2
13627//
13629//
13652typedef enum {
13653 NV_D3D12_HEAP_FLAG_NONE = 0,
13654 NV_D3D12_HEAP_FLAG_CPUVISIBLE_VIDMEM= 1,
13655} NV_D3D12_HEAP_FLAGS;
13656
13657typedef struct _NV_HEAP_PARAMS_V1
13658{
13659 NvU32 version;
13660 NV_D3D12_HEAP_FLAGS NVHeapFlags;
13661} NV_HEAP_PARAMS_V1;
13662
13663#define NV_HEAP_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_HEAP_PARAMS_V1, 1)
13664
13665#define NV_HEAP_PARAMS_VER NV_HEAP_PARAMS_VER_1
13666typedef NV_HEAP_PARAMS_V1 NV_HEAP_PARAMS;
13667
13668NVAPI_INTERFACE NvAPI_D3D12_CreateHeap2(__in ID3D12Device *pDevice,
13669 __in const D3D12_HEAP_DESC *pDesc,
13670 __in const NV_HEAP_PARAMS *pNVHeapParams,
13671 __in REFIID riid,
13672 __out void **ppvHeap);
13673
13674#endif //defined(__cplusplus) && defined(__d3d12_h__)
13675
13676
13677#if defined (__cplusplus) && defined(__d3d12_h__)
13679//
13680// FUNCTION NAME: NvAPI_D3D12_QueryCpuVisibleVidmem
13681//
13683//
13701NVAPI_INTERFACE NvAPI_D3D12_QueryCpuVisibleVidmem(__in ID3D12Device *pDevice,
13702 __out NvU64 *pTotalBytes,
13703 __out NvU64 *pFreeBytes);
13704
13705#endif //defined(__cplusplus) && defined(__d3d12_h__)
13706
13707
13708#if defined (__cplusplus) && defined(__d3d12_h__)
13710//
13711// FUNCTION NAME: NvAPI_D3D12_ReservedResourceGetDesc
13712//
13714//
13734NVAPI_INTERFACE NvAPI_D3D12_ReservedResourceGetDesc(__in ID3D12Resource *pReservedResource,
13735 __out D3D12_RESOURCE_DESC *pDesc);
13736
13737#endif //defined(__cplusplus) && defined(__d3d12_h__)
13738
13739
13740#if defined (__cplusplus) && defined(__d3d12_h__)
13741
13743//
13744// FUNCTION NAME: NvAPI_D3D12_UpdateTileMappings
13745//
13747//
13775NVAPI_INTERFACE NvAPI_D3D12_UpdateTileMappings(
13776 __in ID3D12CommandQueue *pCommandQueue,
13777 __in ID3D12Resource *pResource,
13778 __in UINT NumResourceRegions,
13779 __in const D3D12_TILED_RESOURCE_COORDINATE *pResourceRegionStartCoordinates,
13780 __in const D3D12_TILE_REGION_SIZE *pResourceRegionSizes,
13781 __in ID3D12Heap *pHeap,
13782 __in UINT NumRanges,
13783 __in const D3D12_TILE_RANGE_FLAGS *pRangeFlags,
13784 __in const UINT *pHeapRangeStartOffsets,
13785 __in const UINT *pRangeTileCounts,
13786 __in D3D12_TILE_MAPPING_FLAGS Flags);
13787
13788#endif //defined(__cplusplus) && defined(__d3d12_h__)
13789
13790
13791#if defined (__cplusplus) && defined(__d3d12_h__)
13792
13794//
13795// FUNCTION NAME: NvAPI_D3D12_CopyTileMappings
13796//
13798//
13821NVAPI_INTERFACE NvAPI_D3D12_CopyTileMappings(
13822 __in ID3D12CommandQueue *pCommandQueue,
13823 __in ID3D12Resource *pDstResource,
13824 __in const D3D12_TILED_RESOURCE_COORDINATE *pDstRegionStartCoordinate,
13825 __in ID3D12Resource *pSrcResource,
13826 __in const D3D12_TILED_RESOURCE_COORDINATE *pSrcRegionStartCoordinate,
13827 __in const D3D12_TILE_REGION_SIZE *pRegionSize,
13828 __in D3D12_TILE_MAPPING_FLAGS Flags);
13829
13830#endif //defined(__cplusplus) && defined(__d3d12_h__)
13831
13832
13833#if defined (__cplusplus) && defined(__d3d12_h__)
13834
13836//
13837// FUNCTION NAME: NvAPI_D3D12_ResourceAliasingBarrier
13838//
13840//
13859NVAPI_INTERFACE NvAPI_D3D12_ResourceAliasingBarrier(
13860 __in ID3D12GraphicsCommandList *pCommandList,
13861 __in UINT NumBarriers,
13862 __in const D3D12_RESOURCE_BARRIER *pBarriers);
13863
13864#endif //defined(__cplusplus) && defined(__d3d12_h__)
13865
13866#if defined(__cplusplus) && defined(__d3d12_h__)
13869// Experimental API for internal use. DO NOT USE!
13870
13871typedef struct
13872{
13873 NvU32 version;
13874 NvU32 surfaceHandle;
13875 NvU64 gpuVAStart;
13876 NvU64 gpuVASize;
13877} NVAPI_UAV_INFO_V1;
13878
13879typedef struct
13880{
13881 NvU32 version;
13882 NvU32 surfaceHandle;
13883 NvU64 gpuVAStart;
13884 NvU64 gpuVASize;
13885 NvU64 outFlags;
13886} NVAPI_UAV_INFO_V2;
13887
13888#define NVAPI_UAV_INFO_VER1 1
13889#define NVAPI_UAV_INFO_VER2 MAKE_NVAPI_VERSION(NVAPI_UAV_INFO_V2, 2)
13890
13891#define NVAPI_UAV_INFO_VER NVAPI_UAV_INFO_VER2
13892typedef NVAPI_UAV_INFO_V2 NVAPI_UAV_INFO;
13893
13894NVAPI_INTERFACE NvAPI_D3D12_CaptureUAVInfo(__in ID3D12Device* pDevice,
13895 __out NVAPI_UAV_INFO *pUAVInfo);
13896
13897#endif //defined(__cplusplus) && defined(__d3d12_h__)
13898
13899
13900#if defined(__cplusplus) && defined(__d3d11_h__)
13901typedef struct
13902{
13903 NvU32 version;
13904 NVDX_ObjectHandle hResource;
13905 NvU64 gpuVAStart;
13906 NvU64 gpuVASize;
13907} NV_GET_GPU_VIRTUAL_ADDRESS_V1;
13908
13909#define NV_GET_GPU_VIRTUAL_ADDRESS_VER1 MAKE_NVAPI_VERSION(NV_GET_GPU_VIRTUAL_ADDRESS_V1, 1)
13910#define NV_GET_GPU_VIRTUAL_ADDRESS_VER NV_GET_GPU_VIRTUAL_ADDRESS_VER1
13911#define NV_GET_GPU_VIRTUAL_ADDRESS NV_GET_GPU_VIRTUAL_ADDRESS_V1
13912
13915// Experimental API for internal use. DO NOT USE!
13916NVAPI_INTERFACE NvAPI_D3D11_GetResourceGPUVirtualAddressEx(__in ID3D11Device *pDevice,
13917 __inout NV_GET_GPU_VIRTUAL_ADDRESS *pParams);
13918
13919
13920#endif //defined(__cplusplus) && defined(__d3d11_h__)
13921
13922
13923
13924#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
13926//
13927// MetaCommands common defines
13928//
13930//
13932#pragma pack(push, 4)
13933
13934enum NV_D3D_GRAPHICS_STATES
13935{
13936 NV_D3D_GRAPHICS_STATE_NONE = 0 ,
13937 NV_D3D_GRAPHICS_STATE_IA_VERTEX_BUFFERS = (1 << 0),
13938 NV_D3D_GRAPHICS_STATE_IA_INDEX_BUFFER = (1 << 1),
13939 NV_D3D_GRAPHICS_STATE_IA_PRIMITIVE_TOPOLOGY = (1 << 2),
13940 NV_D3D_GRAPHICS_STATE_DESCRIPTOR_HEAP = (1 << 3),
13941 NV_D3D_GRAPHICS_STATE_GRAPHICS_ROOT_SIGNATURE = (1 << 4),
13942 NV_D3D_GRAPHICS_STATE_COMPUTE_ROOT_SIGNATURE = (1 << 5),
13943 NV_D3D_GRAPHICS_STATE_RS_VIEWPORTS = (1 << 6),
13944 NV_D3D_GRAPHICS_STATE_RS_SCISSOR_RECTS = (1 << 7),
13945 NV_D3D_GRAPHICS_STATE_PREDICATION = (1 << 8),
13946 NV_D3D_GRAPHICS_STATE_OM_RENDER_TARGETS = (1 << 9),
13947 NV_D3D_GRAPHICS_STATE_OM_STENCIL_REF = (1 << 10),
13948 NV_D3D_GRAPHICS_STATE_OM_BLEND_FACTOR = (1 << 11),
13949 NV_D3D_GRAPHICS_STATE_PIPELINE_STATE = (1 << 12),
13950 NV_D3D_GRAPHICS_STATE_SO_TARGETS = (1 << 13),
13951 NV_D3D_GRAPHICS_STATE_OM_DEPTH_BOUNDS = (1 << 14),
13952 NV_D3D_GRAPHICS_STATE_SAMPLE_POSITIONS = (1 << 15),
13953 NV_D3D_GRAPHICS_STATE_VIEW_INSTANCE_MASK = (1 << 16),
13954};
13955
13956struct NVAPI_META_COMMAND_DESC
13957{
13958 GUID Id;
13959 LPCWSTR Name;
13960
13961 // states that the initialization and execution of the metacommand will dirty
13962 NV_D3D_GRAPHICS_STATES InitializationDirtyState;
13963 NV_D3D_GRAPHICS_STATES ExecutionDirtyState;
13964};
13965
13966typedef NvU64 NV_META_COMMAND_BOOL;
13967
13968#define NV_META_COMMAND_MAX_TENSOR_DIM 5
13969// dimensions (Size and Stride) are always indexed this way, irrespective of NV_META_COMMAND_LAYOUT
13970// For DimensionCount = 5: N, C, D, H, W
13971// For DimensionCount = 4: N, C, H, W
13972
13973
13974#define NV_META_COMMAND_ACTIVATION_MAX_PARAMS 2
13975
13976#if __cplusplus >= 201103L
13977
13978#define compile_time_assert(b) static_assert((b), "Compile time assertion failed: "#b)
13979
13980enum NV_META_COMMAND_TENSOR_DATA_TYPE : NvU64
13981{
13982 NV_META_COMMAND_TENSOR_DATA_TYPE_FLOAT32,
13983 NV_META_COMMAND_TENSOR_DATA_TYPE_FLOAT16,
13984 NV_META_COMMAND_TENSOR_DATA_TYPE_UINT32,
13985
13986 NV_META_COMMAND_TENSOR_DATA_TYPE_COUNT,
13987};
13988
13989
13990enum NV_META_COMMAND_TENSOR_LAYOUT : NvU64
13991{
13992 NV_META_COMMAND_TENSOR_LAYOUT_UNKNOWN, // opaque HW-native layout
13993 NV_META_COMMAND_TENSOR_LAYOUT_STANDARD, // NCDHW - planar / row major layout (width is inner-most dimension, batch-size N is the outermost)
13994 NV_META_COMMAND_TENSOR_LAYOUT_COUNT,
13995};
13996
13997enum NV_META_COMMAND_TENSOR_FLAGS : NvU64
13998{
13999 NV_META_COMMAND_TENSOR_FLAG_NONE = 0,
14000 NV_META_COMMAND_TENSOR_FLAG_DATA_STATIC = 0x1, // data pointed by the tensor is static (i.e, won't be modified after command list recording)
14001};
14002
14003enum NV_META_COMMAND_PRECISION : NvU64
14004{
14005 NV_META_COMMAND_PRECISION_FLOAT32,
14006 NV_META_COMMAND_PRECISION_FLOAT16,
14007 NV_META_COMMAND_PRECISION_MUL_FLOAT16_ADD_FLOAT32,
14008
14009 NV_META_COMMAND_PRECISION_COUNT,
14010};
14011
14012struct NV_META_COMMAND_TENSOR_DESC
14013{
14014 NV_META_COMMAND_TENSOR_DATA_TYPE DataType;
14015 NV_META_COMMAND_TENSOR_LAYOUT Layout;
14016 NV_META_COMMAND_TENSOR_FLAGS Flags;
14017 NvU64 DimensionCount; // 4 or 5
14018 NvU64 Size[NV_META_COMMAND_MAX_TENSOR_DIM];
14019 NvU64 Stride[NV_META_COMMAND_MAX_TENSOR_DIM]; // only used with NV_META_COMMAND_TENSOR_LAYOUT_STANDARD
14020};
14021
14022enum NV_META_COMMAND_ACTIVATION_FUNCTION : NvU64
14023{
14024 NV_META_COMMAND_ACTIVATION_FUNCTION_ELU,
14025 NV_META_COMMAND_ACTIVATION_FUNCTION_HARDMAX,
14026 NV_META_COMMAND_ACTIVATION_FUNCTION_HARD_SIGMOID,
14027 NV_META_COMMAND_ACTIVATION_FUNCTION_IDENTITY,
14028 NV_META_COMMAND_ACTIVATION_FUNCTION_LEAKY_RELU,
14029 NV_META_COMMAND_ACTIVATION_FUNCTION_LINEAR,
14030 NV_META_COMMAND_ACTIVATION_FUNCTION_LOG_SOFTMAX,
14031 NV_META_COMMAND_ACTIVATION_FUNCTION_PARAMETERIZED_RELU,
14032 NV_META_COMMAND_ACTIVATION_FUNCTION_PARAMETRIC_SOFTPLUS,
14033 NV_META_COMMAND_ACTIVATION_FUNCTION_RELU,
14034 NV_META_COMMAND_ACTIVATION_FUNCTION_SCALED_ELU,
14035 NV_META_COMMAND_ACTIVATION_FUNCTION_SCALED_TANH,
14036 NV_META_COMMAND_ACTIVATION_FUNCTION_SIGMOID,
14037 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTMAX,
14038 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTPLUS,
14039 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTSIGN,
14040 NV_META_COMMAND_ACTIVATION_FUNCTION_TANH,
14041 NV_META_COMMAND_ACTIVATION_FUNCTION_THRESHOLDED_RELU,
14042
14043 NV_META_COMMAND_ACTIVATION_FUNCTION_COUNT,
14044};
14045
14046struct NV_META_COMMAND_ACTIVATION_DESC
14047{
14048 NV_META_COMMAND_ACTIVATION_FUNCTION Function;
14049 float Params[NV_META_COMMAND_ACTIVATION_MAX_PARAMS];
14050};
14051
14052#else
14053
14054#define compile_time_assert(b) typedef char compile_time_assertion_failed_in_line_##__LINE__[(b)?1:-1]
14055
14056enum NV_META_COMMAND_TENSOR_DATA_TYPE
14057{
14058 NV_META_COMMAND_TENSOR_DATA_TYPE_FLOAT32,
14059 NV_META_COMMAND_TENSOR_DATA_TYPE_FLOAT16,
14060 NV_META_COMMAND_TENSOR_DATA_TYPE_UINT32,
14061
14062 NV_META_COMMAND_TENSOR_DATA_TYPE_COUNT,
14063};
14064
14065
14066enum NV_META_COMMAND_TENSOR_LAYOUT
14067{
14068 NV_META_COMMAND_TENSOR_LAYOUT_UNKNOWN, // opaque HW-native layout
14069 NV_META_COMMAND_TENSOR_LAYOUT_STANDARD, // NCDHW - planar / row major layout (width is inner-most dimension, batch-size N is the outermost)
14070 NV_META_COMMAND_TENSOR_LAYOUT_COUNT,
14071};
14072
14073enum NV_META_COMMAND_TENSOR_FLAGS
14074{
14075 NV_META_COMMAND_TENSOR_FLAG_NONE = 0,
14076 NV_META_COMMAND_TENSOR_FLAG_DATA_STATIC = 0x1, // data pointed by the tensor is static (i.e, won't be modified after command list recording)
14077};
14078
14079enum NV_META_COMMAND_PRECISION
14080{
14081 NV_META_COMMAND_PRECISION_FLOAT32,
14082 NV_META_COMMAND_PRECISION_FLOAT16,
14083 NV_META_COMMAND_PRECISION_MUL_FLOAT16_ADD_FLOAT32,
14084
14085 NV_META_COMMAND_PRECISION_COUNT,
14086};
14087
14088struct NV_META_COMMAND_TENSOR_DESC
14089{
14090 NvU64 DataType; // NV_META_COMMAND_TENSOR_DATA_TYPE
14091 NvU64 Layout; // NV_META_COMMAND_TENSOR_LAYOUT
14092 NvU64 Flags; // NV_META_COMMAND_TENSOR_FLAGS
14093 NvU64 DimensionCount; // 4 or 5
14094 NvU64 Size[NV_META_COMMAND_MAX_TENSOR_DIM];
14095 NvU64 Stride[NV_META_COMMAND_MAX_TENSOR_DIM]; // only used with NV_META_COMMAND_TENSOR_LAYOUT_STANDARD
14096};
14097
14098enum NV_META_COMMAND_ACTIVATION_FUNCTION
14099{
14100 NV_META_COMMAND_ACTIVATION_FUNCTION_ELU,
14101 NV_META_COMMAND_ACTIVATION_FUNCTION_HARDMAX,
14102 NV_META_COMMAND_ACTIVATION_FUNCTION_HARD_SIGMOID,
14103 NV_META_COMMAND_ACTIVATION_FUNCTION_IDENTITY,
14104 NV_META_COMMAND_ACTIVATION_FUNCTION_LEAKY_RELU,
14105 NV_META_COMMAND_ACTIVATION_FUNCTION_LINEAR,
14106 NV_META_COMMAND_ACTIVATION_FUNCTION_LOG_SOFTMAX,
14107 NV_META_COMMAND_ACTIVATION_FUNCTION_PARAMETERIZED_RELU,
14108 NV_META_COMMAND_ACTIVATION_FUNCTION_PARAMETRIC_SOFTPLUS,
14109 NV_META_COMMAND_ACTIVATION_FUNCTION_RELU,
14110 NV_META_COMMAND_ACTIVATION_FUNCTION_SCALED_ELU,
14111 NV_META_COMMAND_ACTIVATION_FUNCTION_SCALED_TANH,
14112 NV_META_COMMAND_ACTIVATION_FUNCTION_SIGMOID,
14113 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTMAX,
14114 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTPLUS,
14115 NV_META_COMMAND_ACTIVATION_FUNCTION_SOFTSIGN,
14116 NV_META_COMMAND_ACTIVATION_FUNCTION_TANH,
14117 NV_META_COMMAND_ACTIVATION_FUNCTION_THRESHOLDED_RELU,
14118
14119 NV_META_COMMAND_ACTIVATION_FUNCTION_COUNT,
14120};
14121
14122struct NV_META_COMMAND_ACTIVATION_DESC
14123{
14124 NvU64 Function; // NV_META_COMMAND_ACTIVATION_FUNCTION
14125 float Params[NV_META_COMMAND_ACTIVATION_MAX_PARAMS];
14126};
14127
14128#endif
14129
14130struct NV_META_COMMAND_OPTIONAL_TENSOR_DESC : NV_META_COMMAND_TENSOR_DESC
14131{
14132 // true when the tensor isn't needed (e.g, bias is optional)
14133 NV_META_COMMAND_BOOL IsNull;
14134};
14135
14136
14137struct NV_META_COMMAND_OPTIONAL_ACTIVATION_DESC : NV_META_COMMAND_ACTIVATION_DESC
14138{
14139 // true when activation isn't needed
14140 NV_META_COMMAND_BOOL IsNull;
14141};
14142
14143
14144enum NV_META_COMMAND_PADDING_MODE
14145{
14146 NV_META_COMMAND_PADDING_ZEROS,
14147 NV_META_COMMAND_PADDING_MIRROR,
14148 NV_META_COMMAND_PADDING_CLAMP,
14149 NV_META_COMMAND_PADDING_CONSTANT,
14150
14151 NV_META_COMMAND_PADDING_COUNT,
14152};
14153
14154struct NV_META_COMMAND_PADDING_DESC
14155{
14156 NV_META_COMMAND_PADDING_MODE Mode;
14157
14158 // used with NV_META_COMMAND_PADDING_CONSTANT
14159 float ConstantPadVal;
14160};
14161
14162// use this enum to query resource sizes using GetRequiredParameterResourceSize() call
14163enum NV_META_COMMAND_RESOURCE_TYPE
14164{
14165 NV_META_COMMAND_RESOURCE_TYPE_INPUT = 0,
14166 NV_META_COMMAND_RESOURCE_TYPE_OUTPUT = 1,
14167
14168 NV_META_COMMAND_RESOURCE_TYPE_FILTER = 2,
14169 NV_META_COMMAND_RESOURCE_TYPE_WEIGHT = 2,
14170 NV_META_COMMAND_RESOURCE_TYPE_BIAS = 3,
14171
14172 NV_META_COMMAND_RESOURCE_TYPE_MATRIX_A = 0,
14173 NV_META_COMMAND_RESOURCE_TYPE_MATRIX_B = 2,
14174 NV_META_COMMAND_RESOURCE_TYPE_MATRIX_C = 3,
14175
14176 NV_META_COMMAND_RESOURCE_TYPE_PERSISTENT = 4,
14177 NV_META_COMMAND_RESOURCE_TYPE_TEMPORARY = 5,
14178};
14179
14180
14181// Extended version of convolution operation that performs:
14182//
14183// y = act ( alpha1 * conv(x) + alpha2 * z + bias )
14184//
14185// alpha1 and alpha2 are either scalars or if PerChannelScaling is TRUE, they are vectors of
14186// same dimension as the bias tensor (vector of size equal to number of output channels)
14187//
14188// z (SkipConnectionResource) has same dimension as output tensor y (OutputResource).
14189
14190static const GUID MetaCommand_ConvolutionEx =
14191{ 0xa7666f1e, 0x9c55, 0x47ee, { 0x9e, 0xb3, 0xe1, 0x62, 0x0, 0x92, 0xd1, 0xe9 } };
14192
14193#define NV_META_COMMAND_NUM_SPATIAL_DIM 3
14194// D, H, W when DimensionCount is 3
14195// H, W when DimensionCount is 2
14196
14197
14198#if __cplusplus >= 201103L
14199enum NV_META_COMMAND_CONVOLUTION_DIRECTION : NvU64
14200{
14201 NV_META_COMMAND_CONVOLUTION_DIRECTION_FORWARD, // Corresponds to regular Convolution
14202 NV_META_COMMAND_CONVOLUTION_DIRECTION_BACKWARD, // Corresponds to ConvolutionTranspose
14203
14204 NV_META_COMMAND_CONVOLUTION_DIRECTION_COUNT,
14205};
14206
14207enum NV_META_COMMAND_CONVOLUTION_MODE : NvU64
14208{
14209 NV_META_COMMAND_CONVOLUTION_MODE_CONVOLUTION,
14210 NV_META_COMMAND_CONVOLUTION_MODE_CROSS_CORRELATION,
14211
14212 NV_META_COMMAND_CONVOLUTION_MODE_COUNT,
14213};
14214
14215struct NV_META_COMMAND_CREATE_CONVOLUTION_EX_DESC
14216{
14217 // Descriptor of the input tensor
14218 NV_META_COMMAND_TENSOR_DESC DescIn;
14219
14220 // Descriptor of the tensor acting as the filter kernel
14221 NV_META_COMMAND_TENSOR_DESC DescFilter;
14222
14223 // Descriptor of the optional bias tensor
14224 NV_META_COMMAND_OPTIONAL_TENSOR_DESC DescBias;
14225
14226 // Descriptor of the output tensor
14227 NV_META_COMMAND_TENSOR_DESC DescOut;
14228
14229 // Convolution mode (CROSS_CORRELATION or CONVOLUTION)
14230 NV_META_COMMAND_CONVOLUTION_MODE Mode;
14231
14232 // Convolution direction (FORWARD or BACKWARD)
14233 NV_META_COMMAND_CONVOLUTION_DIRECTION Direction;
14234
14235 // Precision at which convolution is done
14236 NV_META_COMMAND_PRECISION Precision;
14237
14238 // Optional activation function
14239 NV_META_COMMAND_OPTIONAL_ACTIVATION_DESC Activation;
14240
14241 // Padding mode (only used when output tensor dimensions are different from input tensor dimensions)
14242 NV_META_COMMAND_PADDING_DESC Padding;
14243
14244 // enables per channel scaling i.e, use Alpha1Resource and Alpha2Resource
14245 // instead of Alpha1 and Alpha2 below
14246 NV_META_COMMAND_BOOL PerChannelScaling;
14247
14248 // scaling factors used when PerChannelScaling is FALSE
14249 // set Alpha1 = 1.0f, Alpha2 = 0.0f for simple convolutions
14250 // that don't need scaling or skip connection
14251 float Alpha1;
14252 float Alpha2;
14253
14254 // Strides for the filter kernel position
14255 NvU64 Stride[NV_META_COMMAND_NUM_SPATIAL_DIM];
14256
14257 // The distance per dimension between elements that are multiplied
14258 NvU64 Dilation[NV_META_COMMAND_NUM_SPATIAL_DIM];
14259
14260 // Padding at the start of each dimension
14261 NvU64 StartPadding[NV_META_COMMAND_NUM_SPATIAL_DIM];
14262
14263 // Padding at the end of each dimension
14264 NvU64 EndPadding[NV_META_COMMAND_NUM_SPATIAL_DIM];
14265
14266 // Number of dimensions to which convolution occurs (2 or 3)
14267 NvU64 DimensionCount;
14268
14269 // Number of channel groups convolved independently
14270 NvU64 GroupCount;
14271};
14272
14273#else
14274
14275enum NV_META_COMMAND_CONVOLUTION_DIRECTION
14276{
14277 NV_META_COMMAND_CONVOLUTION_DIRECTION_FORWARD, // Corresponds to regular Convolution
14278 NV_META_COMMAND_CONVOLUTION_DIRECTION_BACKWARD, // Corresponds to ConvolutionTranspose
14279
14280 NV_META_COMMAND_CONVOLUTION_DIRECTION_COUNT,
14281};
14282
14283enum NV_META_COMMAND_CONVOLUTION_MODE
14284{
14285 NV_META_COMMAND_CONVOLUTION_MODE_CONVOLUTION,
14286 NV_META_COMMAND_CONVOLUTION_MODE_CROSS_CORRELATION,
14287
14288 NV_META_COMMAND_CONVOLUTION_MODE_COUNT,
14289};
14290
14291struct NV_META_COMMAND_CREATE_CONVOLUTION_EX_DESC
14292{
14293 // Descriptor of the input tensor
14294 NV_META_COMMAND_TENSOR_DESC DescIn;
14295
14296 // Descriptor of the tensor acting as the filter kernel
14297 NV_META_COMMAND_TENSOR_DESC DescFilter;
14298
14299 // Descriptor of the optional bias tensor
14300 NV_META_COMMAND_OPTIONAL_TENSOR_DESC DescBias;
14301
14302 // Descriptor of the output tensor
14303 NV_META_COMMAND_TENSOR_DESC DescOut;
14304
14305 // Convolution mode (CROSS_CORRELATION or CONVOLUTION)
14306 NvU64 Mode; // NV_META_COMMAND_CONVOLUTION_MODE
14307
14308 // Convolution direction (FORWARD or BACKWARD)
14309 NvU64 Direction; // NV_META_COMMAND_CONVOLUTION_DIRECTION
14310
14311 // Precision at which convolution is done
14312 NvU64 Precision; // NV_META_COMMAND_PRECISION
14313
14314 // Optional activation function
14315 NV_META_COMMAND_OPTIONAL_ACTIVATION_DESC Activation;
14316
14317 // Padding mode (only used when output tensor dimensions are different from input tensor dimensions)
14318 NV_META_COMMAND_PADDING_DESC Padding;
14319
14320 // enables per channel scaling i.e, use Alpha1Resource and Alpha2Resource
14321 // instead of Alpha1 and Alpha2 below
14322 NV_META_COMMAND_BOOL PerChannelScaling;
14323
14324 // scaling factors used when PerChannelScaling is FALSE
14325 // set Alpha1 = 1.0f, Alpha2 = 0.0f for simple convolutions
14326 // that don't need scaling or skip connection
14327 float Alpha1;
14328 float Alpha2;
14329
14330 // Strides for the filter kernel position
14331 NvU64 Stride[NV_META_COMMAND_NUM_SPATIAL_DIM];
14332
14333 // The distance per dimension between elements that are multiplied
14334 NvU64 Dilation[NV_META_COMMAND_NUM_SPATIAL_DIM];
14335
14336 // Padding at the start of each dimension
14337 NvU64 StartPadding[NV_META_COMMAND_NUM_SPATIAL_DIM];
14338
14339 // Padding at the end of each dimension
14340 NvU64 EndPadding[NV_META_COMMAND_NUM_SPATIAL_DIM];
14341
14342 // Number of dimensions to which convolution occurs (2 or 3)
14343 NvU64 DimensionCount;
14344
14345 // Number of channel groups convolved independently
14346 NvU64 GroupCount;
14347};
14348#endif
14349
14350
14351// Fused Convolution variants
14352
14353// supported combinations right now are:
14354// - Convolution + Max Pooling (also optionally outputs pre-pool data)
14355// - 2x2 upsample + (optional) residual add + Convolution
14356//
14357// other combinations may be exposed in future
14358
14359static const GUID MetaCommand_ConvolutionExFused =
14360{ 0xe1b112eb, 0xdecd, 0x4ff6,{ 0x85, 0xbb, 0x1f, 0xe, 0x3a, 0xb0, 0x4, 0x14 } };
14361
14362
14363enum NV_META_COMMAND_CONVOLUTION_POOL_MODE
14364{
14365 NV_META_COMMAND_CONVOLUTION_POOL_MODE_NONE,
14366 NV_META_COMMAND_CONVOLUTION_POOL_MODE_REDUCTION_MAX,
14367 NV_META_COMMAND_CONVOLUTION_POOL_MODE_REDUCTION_AVG,
14368 NV_META_COMMAND_CONVOLUTION_POOL_MODE_REDUCTION_MIN,
14369
14370 NV_META_COMMAND_CONVOLUTION_POOL_MODE_COUNT,
14371};
14372
14373enum NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE
14374{
14375 NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE_NONE,
14376 NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE_REPLICATE,
14377 NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE_BILINEAR,
14378
14379 NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE_COUNT,
14380};
14381
14382enum NV_META_COMMAND_CONVOLUTION_SKIP_MODE
14383{
14384 NV_META_COMMAND_CONVOLUTION_SKIP_MODE_NONE,
14385 NV_META_COMMAND_CONVOLUTION_SKIP_MODE_ADD,
14386 NV_META_COMMAND_CONVOLUTION_SKIP_MODE_CONCAT,
14387
14388 NV_META_COMMAND_CONVOLUTION_SKIP_MODE_COUNT,
14389};
14390
14391struct NV_META_COMMAND_CONVOLUTION_FUSE_DESC
14392{
14393 NV_META_COMMAND_CONVOLUTION_POOL_MODE PoolMode;
14394 NV_META_COMMAND_CONVOLUTION_UPSAMPLE_MODE UpsampleMode;
14395 NV_META_COMMAND_CONVOLUTION_SKIP_MODE SkipMode;
14396
14397 NV_META_COMMAND_BOOL OutputPrepool; // used with NV_META_COMMAND_CONVOLUTION_POOL_MODE
14398};
14399
14400// uses same structures for init and execute descriptors
14401// SkipConnectionResource is used to specify the resource for pre-pool data or residual add
14402struct NV_META_COMMAND_CREATE_CONVOLUTION_EX_FUSED_DESC : NV_META_COMMAND_CREATE_CONVOLUTION_EX_DESC
14403{
14404 NV_META_COMMAND_CONVOLUTION_FUSE_DESC FuseDesc;
14405};
14406
14407// make sure structure sizes match what the driver assumes
14408compile_time_assert(sizeof(NV_META_COMMAND_TENSOR_DESC) == 112);
14409compile_time_assert(sizeof(NV_META_COMMAND_CREATE_CONVOLUTION_EX_DESC) == 640);
14410compile_time_assert(sizeof(NV_META_COMMAND_CONVOLUTION_FUSE_DESC) == 20);
14411compile_time_assert(sizeof(NV_META_COMMAND_CREATE_CONVOLUTION_EX_FUSED_DESC) == 660);
14412
14413
14414// GEMM (General matrix multiply)
14415//
14416// Y = alpha * t(A) * t(B) + beta * C,
14417//
14418// where t is a matrix transform option
14419//
14420// If C is null, and beta is non-zero, the output
14421// matrix is used as C matrix. i.e, the operation performed is:
14422// Y = alpha * t(A) * t(B) + beta * Y
14423//
14424static const GUID MetaCommand_Gemm =
14425 { 0x8f9ff059, 0xfe72, 0x488e, { 0xa0, 0x66, 0xb1, 0x4e, 0x79, 0x48, 0xec, 0x8 } };
14426
14427#if __cplusplus >= 201103L
14428
14429enum NV_META_COMMAND_MATRIX_TRANSFORM : NvU64
14430{
14431 NV_META_COMMAND_MATRIX_TRANSFORM_NONE,
14432 NV_META_COMMAND_MATRIX_TRANSFORM_TRANSPOSE,
14433
14434 NV_META_COMMAND_MATRIX_TRANSFORM_COUNT,
14435};
14436
14437struct NV_META_COMMAND_CREATE_GEMM_DESC
14438{
14439 NV_META_COMMAND_TENSOR_DESC DescA;
14440 NV_META_COMMAND_TENSOR_DESC DescB;
14441 NV_META_COMMAND_OPTIONAL_TENSOR_DESC DescC;
14442 NV_META_COMMAND_TENSOR_DESC DescOut;
14443 NV_META_COMMAND_PRECISION Precision;
14444
14445 NV_META_COMMAND_MATRIX_TRANSFORM TransA;
14446 NV_META_COMMAND_MATRIX_TRANSFORM TransB;
14447 float Alpha;
14448 float Beta;
14449
14450 NV_META_COMMAND_OPTIONAL_ACTIVATION_DESC Activation;
14451};
14452
14453#else
14454
14455enum NV_META_COMMAND_MATRIX_TRANSFORM
14456{
14457 NV_META_COMMAND_MATRIX_TRANSFORM_NONE,
14458 NV_META_COMMAND_MATRIX_TRANSFORM_TRANSPOSE,
14459
14460 NV_META_COMMAND_MATRIX_TRANSFORM_COUNT,
14461};
14462
14463struct NV_META_COMMAND_CREATE_GEMM_DESC
14464{
14465 NV_META_COMMAND_TENSOR_DESC DescA;
14466 NV_META_COMMAND_TENSOR_DESC DescB;
14467 NV_META_COMMAND_OPTIONAL_TENSOR_DESC DescC;
14468 NV_META_COMMAND_TENSOR_DESC DescOut;
14469 NvU64 Precision; // NV_META_COMMAND_PRECISION
14470
14471 NvU64 TransA; // NV_META_COMMAND_MATRIX_TRANSFORM
14472 NvU64 TransB; // NV_META_COMMAND_MATRIX_TRANSFORM
14473 float Alpha;
14474 float Beta;
14475
14476 NV_META_COMMAND_OPTIONAL_ACTIVATION_DESC Activation;
14477};
14478
14479#endif
14480
14481
14482#pragma pack(pop)
14483
14484#endif // #if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
14485
14486
14487#if defined (__cplusplus) && defined(__d3d11_h__)
14489//
14490// FUNCTION NAME: NvAPI_D3D11_EnumerateMetaCommands
14491//
14493//
14510
14511NVAPI_INTERFACE NvAPI_D3D11_EnumerateMetaCommands(__in ID3D11Device *pDevice,
14512 __inout NvU32 *pNumMetaCommands,
14513 __out_ecount_opt(*pNumMetaCommands) NVAPI_META_COMMAND_DESC *pDescs);
14514
14515#endif //defined(__cplusplus) && defined(__d3d11_h__)
14516
14517
14518
14519#if defined (__cplusplus) && defined(__d3d11_h__)
14521//
14522// FUNCTION NAME: NvAPI_D3D11_CreateMetaCommand
14523//
14525//
14544
14545#pragma pack(push, 4)
14546struct NV_D3D11_META_COMMAND_RESOURCE
14547{
14548 union
14549 {
14550 NVDX_ObjectHandle ResourceHandle; // NVAPI handle of a buffer resource (use NvAPI_D3D11_GetResourceHandle to get this handle)
14551 NvU64 unused; // to get correct sturcutre size on 32 bit builds
14552 };
14553 NvU64 Offset; // offset within the resource in bytes
14554};
14555
14556struct NV_D3D11_META_COMMAND_INITIALIZE_CONVOLUTION_EX_DESC
14557{
14558 // Persistent resource used as scratch space by driver
14559 // it's written at time of init, and read at time of execute
14560 // use GetRequiredParameterResourceSize to query its size
14561 NV_D3D11_META_COMMAND_RESOURCE PersistentResource;
14562};
14563
14564struct NV_D3D11_META_COMMAND_EXECUTE_CONVOLUTION_EX_DESC
14565{
14566 NV_D3D11_META_COMMAND_RESOURCE InputResource;
14567 NV_D3D11_META_COMMAND_RESOURCE FilterResource;
14568 NV_D3D11_META_COMMAND_RESOURCE BiasResource; // optional
14569 NV_D3D11_META_COMMAND_RESOURCE OutputResource;
14570
14571 // Alpha1Resource and Alpha2Resource are used only when
14572 // PerChannelScaling is set. Otherwise the scalars Alpha1/Alpha2 are used
14573 // should have same dimension as bias
14574 NV_D3D11_META_COMMAND_RESOURCE Alpha1Resource;
14575 NV_D3D11_META_COMMAND_RESOURCE Alpha2Resource;
14576
14577 // optional, same dimension/descriptor as output
14578 NV_D3D11_META_COMMAND_RESOURCE SkipConnectionResource;
14579
14580
14581 // should point to same memory that was specified at time of init
14582 NV_D3D11_META_COMMAND_RESOURCE PersistentResource;
14583
14584 // temporary resource used as scratch space by driver
14585 // used for both read and write at the time of execute
14586 // use GetRequiredParameterResourceSize to query its size
14587 NV_D3D11_META_COMMAND_RESOURCE TemporaryResource;
14588};
14589
14590// make sure structure sizes match what the driver assumes
14591compile_time_assert(sizeof(NV_D3D11_META_COMMAND_INITIALIZE_CONVOLUTION_EX_DESC) == 16);
14592compile_time_assert(sizeof(NV_D3D11_META_COMMAND_EXECUTE_CONVOLUTION_EX_DESC) == 144);
14593
14594struct NV_D3D11_META_COMMAND_INITIALIZE_GEMM_DESC
14595{
14596 NV_D3D11_META_COMMAND_RESOURCE PersistentResource;
14597};
14598
14599struct NV_D3D11_META_COMMAND_EXECUTE_GEMM_DESC
14600{
14601 NV_D3D11_META_COMMAND_RESOURCE AResource;
14602 NV_D3D11_META_COMMAND_RESOURCE BResource;
14603 NV_D3D11_META_COMMAND_RESOURCE CResource;
14604 NV_D3D11_META_COMMAND_RESOURCE OutputResource;
14605
14606 NV_D3D11_META_COMMAND_RESOURCE PersistentResource;
14607 NV_D3D11_META_COMMAND_RESOURCE TemporaryResource;
14608};
14609
14610// make sure structure sizes match what the driver assumes
14611compile_time_assert(sizeof(NV_D3D11_META_COMMAND_INITIALIZE_GEMM_DESC) == 16);
14612compile_time_assert(sizeof(NV_D3D11_META_COMMAND_EXECUTE_GEMM_DESC) == 96);
14613
14614
14615#pragma pack(pop)
14616
14617DECLARE_INTERFACE_(__declspec(uuid("00BF193A-117B-42BC-BBCD-E964A0EA4F2B"))ID3D11NvMetaCommand_V1, IUnknown)
14618{
14619 BEGIN_INTERFACE
14620
14621 // *** IUnknown methods ***
14622 STDMETHOD(QueryInterface)(THIS_ REFIID riid, void **ppv) PURE;
14623 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
14624 STDMETHOD_(ULONG,Release)(THIS) PURE;
14625
14626 // ** ID3D11NvMetaCommand methods ***
14627 // Return size of parameter
14628 STDMETHOD(GetRequiredParameterResourceSize)(THIS_ NV_META_COMMAND_RESOURCE_TYPE ResourceType, NvU64 *SizeInBytes) const PURE;
14629
14630 END_INTERFACE
14631};
14632
14633typedef ID3D11NvMetaCommand_V1 ID3D11NvMetaCommand;
14634#define ID3D11NvMetaCommand_VER1 MAKE_NVAPI_VERSION(IID3D11NvMetaCommand_V1, 1)
14635#define ID3D11NvMetaCommand_VER ID3D11NvMetaCommand_VER1
14636
14637NVAPI_INTERFACE NvAPI_D3D11_CreateMetaCommand(__in ID3D11Device *pDevice,
14638 __in REFGUID CommandId,
14639 __in_bcount(CreationParametersDataSize) const void *pCreationParametersData,
14640 __in NvU32 CreationParametersDataSize,
14641 __out ID3D11NvMetaCommand **ppMetaCommand);
14642
14643#endif //defined(__cplusplus) && defined(__d3d11_h__)
14644
14645
14646#if defined (__cplusplus) && defined(__d3d11_h__)
14648//
14649// FUNCTION NAME: NvAPI_D3D11_InitializeMetaCommand
14650//
14652//
14668
14669NVAPI_INTERFACE NvAPI_D3D11_InitializeMetaCommand(__in ID3D11DeviceContext *pDeviceContext,
14670 __in ID3D11NvMetaCommand *pMetaCommand,
14671 __in_bcount(InitializationParametersDataSize) const void *pInitializationParametersData,
14672 __in NvU32 InitializationParametersDataSize);
14673
14674#endif //defined(__cplusplus) && defined(__d3d11_h__)
14675
14676
14677#if defined (__cplusplus) && defined(__d3d11_h__)
14679//
14680// FUNCTION NAME: NvAPI_D3D11_ExecuteMetaCommand
14681//
14683//
14699
14700NVAPI_INTERFACE NvAPI_D3D11_ExecuteMetaCommand(__in ID3D11DeviceContext *pDeviceContext,
14701 __in ID3D11NvMetaCommand *pMetaCommand,
14702 __in_bcount(ExecutionParametersDataSize) const void *pExecutionParametersData,
14703 __in NvU32 ExecutionParametersDataSize);
14704
14705#endif //defined(__cplusplus) && defined(__d3d11_h__)
14706
14707
14708
14709
14710#if defined (__cplusplus) && defined(__d3d12_h__)
14712//
14713// FUNCTION NAME: NvAPI_D3D12_EnumerateMetaCommands
14714//
14716//
14733
14734NVAPI_INTERFACE NvAPI_D3D12_EnumerateMetaCommands(__in ID3D12Device *pDevice,
14735 __inout NvU32 *pNumMetaCommands,
14736 __out_ecount_opt(*pNumMetaCommands) NVAPI_META_COMMAND_DESC *pDescs);
14737
14738#endif //defined(__cplusplus) && defined(__d3d12_h__)
14739
14740
14741
14742#if defined (__cplusplus) && defined(__d3d12_h__)
14744//
14745// FUNCTION NAME: NvAPI_D3D12_CreateMetaCommand
14746//
14748//
14768
14769#pragma pack(push, 4)
14770struct NV_D3D12_META_COMMAND_INITIALIZE_CONVOLUTION_EX_DESC
14771{
14772 // Persistent resource used as scratch space by driver
14773 // it's written at time of init, and read at time of execute
14774 // use GetRequiredParameterResourceSize to query its size
14775 D3D12_GPU_VIRTUAL_ADDRESS PersistentResource;
14776};
14777
14778struct NV_D3D12_META_COMMAND_EXECUTE_CONVOLUTION_EX_DESC
14779{
14780 D3D12_GPU_VIRTUAL_ADDRESS InputResource;
14781 D3D12_GPU_VIRTUAL_ADDRESS FilterResource;
14782 D3D12_GPU_VIRTUAL_ADDRESS BiasResource; // optional
14783 D3D12_GPU_VIRTUAL_ADDRESS OutputResource;
14784
14785 // Alpha1Resource and Alpha2Resource are used only when
14786 // PerChannelScaling is set. Otherwise the scalars Alpha1/Alpha2 are used
14787 // should have same dimension as bias
14788 D3D12_GPU_VIRTUAL_ADDRESS Alpha1Resource;
14789 D3D12_GPU_VIRTUAL_ADDRESS Alpha2Resource;
14790
14791 // optional, same dimension/descriptor as output
14792 D3D12_GPU_VIRTUAL_ADDRESS SkipConnectionResource;
14793
14794 // should point to same memory that was specified at time of init
14795 D3D12_GPU_VIRTUAL_ADDRESS PersistentResource;
14796
14797 // temporary resource used as scratch space by driver
14798 // both written and read at time of execute
14799 // use GetRequiredParameterResourceSize to query its size
14800 D3D12_GPU_VIRTUAL_ADDRESS TemporaryResource;
14801};
14802
14803// make sure structure sizes match what the driver assumes
14804compile_time_assert(sizeof(NV_D3D12_META_COMMAND_INITIALIZE_CONVOLUTION_EX_DESC) == 8);
14805compile_time_assert(sizeof(NV_D3D12_META_COMMAND_EXECUTE_CONVOLUTION_EX_DESC) == 72);
14806
14807struct NV_D3D12_META_COMMAND_INITIALIZE_GEMM_DESC
14808{
14809 NvU64 PersistentResource;
14810};
14811
14812struct NV_D3D12_META_COMMAND_EXECUTE_GEMM_DESC
14813{
14814 NvU64 AResource;
14815 NvU64 BResource;
14816 NvU64 CResource;
14817 NvU64 OutputResource;
14818
14819 NvU64 PersistentResource;
14820 NvU64 TemporaryResource;
14821};
14822
14823// make sure structure sizes match what the driver assumes
14824compile_time_assert(sizeof(NV_D3D12_META_COMMAND_INITIALIZE_GEMM_DESC) == 8);
14825compile_time_assert(sizeof(NV_D3D12_META_COMMAND_EXECUTE_GEMM_DESC) == 48);
14826
14827
14828#pragma pack(pop)
14829
14830DECLARE_INTERFACE_(__declspec(uuid("00BF193A-117B-42BC-BBCD-E964A0EA4F2B"))ID3D12NvMetaCommand_V1, IUnknown)
14831{
14832 BEGIN_INTERFACE
14833
14834 // *** IUnknown methods ***
14835 STDMETHOD(QueryInterface)(THIS_ REFIID riid, void **ppv) PURE;
14836 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
14837 STDMETHOD_(ULONG,Release)(THIS) PURE;
14838
14839 // ** ID3D12NvMetaCommand methods ***
14840 // Return size of parameter
14841 STDMETHOD(GetRequiredParameterResourceSize)(THIS_ NV_META_COMMAND_RESOURCE_TYPE ResourceType, NvU64 *SizeInBytes) const PURE;
14842
14843 END_INTERFACE
14844};
14845
14846typedef ID3D12NvMetaCommand_V1 ID3D12NvMetaCommand;
14847#define ID3D12NvMetaCommand_VER1 MAKE_NVAPI_VERSION(IID3D12NvMetaCommand_V1, 1)
14848#define ID3D12NvMetaCommand_VER ID3D12NvMetaCommand_VER1
14849
14850NVAPI_INTERFACE NvAPI_D3D12_CreateMetaCommand(__in ID3D12Device *pDevice,
14851 __in REFGUID CommandId,
14852 __in NvU32 NodeMask,
14853 __in_bcount(CreationParametersDataSize) const void *pCreationParametersData,
14854 __in NvU32 CreationParametersDataSize,
14855 __out ID3D12NvMetaCommand **ppMetaCommand);
14856
14857#endif //defined(__cplusplus) && defined(__d3d12_h__)
14858
14859
14860#if defined (__cplusplus) && defined(__d3d12_h__)
14862//
14863// FUNCTION NAME: NvAPI_D3D12_InitializeMetaCommand
14864//
14866//
14882
14883NVAPI_INTERFACE NvAPI_D3D12_InitializeMetaCommand(__in ID3D12GraphicsCommandList *pCommandlist,
14884 __in ID3D12NvMetaCommand *pMetaCommand,
14885 __in_bcount(InitializationParametersDataSize) const void *pInitializationParametersData,
14886 __in NvU32 InitializationParametersDataSize);
14887
14888#endif //defined(__cplusplus) && defined(__d3d12_h__)
14889
14890
14891#if defined (__cplusplus) && defined(__d3d12_h__)
14893//
14894// FUNCTION NAME: NvAPI_D3D12_ExecuteMetaCommand
14895//
14897//
14913
14914NVAPI_INTERFACE NvAPI_D3D12_ExecuteMetaCommand(__in ID3D12GraphicsCommandList *pCommandlist,
14915 __in ID3D12NvMetaCommand *pMetaCommand,
14916 __in_bcount(ExecutionParametersDataSize) const void *pExecutionParametersData,
14917 __in NvU32 ExecutionParametersDataSize);
14918
14919#endif //defined(__cplusplus) && defined(__d3d12_h__)
14920
14921
14922#if defined (__cplusplus) && defined(__d3d12_h__)
14924//
14925// FUNCTION NAME: NvAPI_D3D12_CreateCommittedResource
14926//
14928//
14962
14963typedef enum {
14964 NV_D3D12_RESOURCE_FLAG_NONE = 0,
14965 NV_D3D12_RESOURCE_FLAG_HTEX = 1,
14966 NV_D3D12_RESOURCE_FLAG_CPUVISIBLE_VIDMEM= 2,
14967} NV_D3D12_RESOURCE_FLAGS;
14968
14969typedef struct _NV_RESOURCE_PARAMS_V1
14970{
14971 NvU32 version;
14972 NV_D3D12_RESOURCE_FLAGS NVResourceFlags;
14973} NV_RESOURCE_PARAMS_V1;
14974
14975#define NV_RESOURCE_PARAMS_VER_1 MAKE_NVAPI_VERSION(NV_RESOURCE_PARAMS_V1, 1)
14976
14977#define NV_RESOURCE_PARAMS_VER NV_RESOURCE_PARAMS_VER_1
14978typedef NV_RESOURCE_PARAMS_V1 NV_RESOURCE_PARAMS;
14979
14980NVAPI_INTERFACE NvAPI_D3D12_CreateCommittedResource(__in ID3D12Device *pDevice,
14981 __in const D3D12_HEAP_PROPERTIES *pHeapProperties,
14982 __in D3D12_HEAP_FLAGS HeapFlags,
14983 __in const D3D12_RESOURCE_DESC *pDesc,
14984 __in D3D12_RESOURCE_STATES InitialState,
14985 __in const D3D12_CLEAR_VALUE *pOptimizedClearValue,
14986 __in const NV_RESOURCE_PARAMS *pNVResourceParams,
14987 __in REFIID riid,
14988 __out_opt void **ppvResource,
14989 __out_opt bool *pSupported);
14990
14991#endif //defined(__cplusplus) && defined(__d3d12_h__)
14992
14993
14994#if defined (__cplusplus) && defined(__d3d12_h__)
14996//
14997// FUNCTION NAME: NvAPI_D3D12_GetCopyableFootprints
14998//
15000//
15026
15027NVAPI_INTERFACE NvAPI_D3D12_GetCopyableFootprints(__in ID3D12Device *pDevice,
15028 __in const D3D12_RESOURCE_DESC *pResourceDesc,
15029 __in const NV_RESOURCE_PARAMS *pNVResourceParams,
15030 __in UINT FirstSubresource,
15031 __in UINT NumSubresources,
15032 __in UINT64 BaseOffset,
15033 __out_ecount_opt(NumSubresources) D3D12_PLACED_SUBRESOURCE_FOOTPRINT *pLayouts,
15034 __out_ecount_opt(NumSubresources) UINT *pNumRows,
15035 __out_ecount_opt(NumSubresources) UINT64 *pRowSizeInBytes,
15036 __out_opt UINT64 *pTotalBytes);
15037
15038#endif //defined(__cplusplus) && defined(__d3d12_h__)
15039
15040
15041#if defined (__cplusplus) && defined(__d3d12_h__)
15043//
15044// FUNCTION NAME: NvAPI_D3D12_CopyTextureRegion
15045//
15047//
15069
15070NVAPI_INTERFACE NvAPI_D3D12_CopyTextureRegion(__in ID3D12GraphicsCommandList *pCommandList,
15071 __in const D3D12_TEXTURE_COPY_LOCATION *pDst,
15072 __in UINT DstX,
15073 __in UINT DstY,
15074 __in UINT DstZ,
15075 __in const D3D12_TEXTURE_COPY_LOCATION *pSrc,
15076 __in_opt const D3D12_BOX *pSrcBox);
15077
15078#endif //defined(__cplusplus) && defined(__d3d12_h__)
15079
15080
15081
15082#if defined (__cplusplus) && defined(__d3d12_h__)
15084//
15085// FUNCTION NAME: NvAPI_D3D12_IsNvShaderExtnOpCodeSupported
15086//
15106NVAPI_INTERFACE NvAPI_D3D12_IsNvShaderExtnOpCodeSupported(__in ID3D12Device *pDevice,
15107 __in NvU32 opCode,
15108 __out bool *pSupported);
15109
15110#endif //defined (__cplusplus) && defined(__d3d12_h__)
15111
15112
15113#if defined (__cplusplus) && defined(__d3d12_h__)
15115//
15116// FUNCTION NAME: NvAPI_D3D12_GetOptimalThreadCountForMesh
15117//
15134NVAPI_INTERFACE NvAPI_D3D12_GetOptimalThreadCountForMesh(__in ID3D12Device *pDevice,
15135 __out NvU32 *pThreadCount);
15136
15137#endif //defined (__cplusplus) && defined(__d3d12_h__)
15138
15139
15140#if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d11_h__)
15141
15159NVAPI_INTERFACE NvAPI_D3D_IsGSyncCapable(__in IUnknown *pDeviceOrContext, __in NVDX_ObjectHandle primarySurface, __out BOOL *pIsGsyncCapable);
15160#endif //if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d11_h__)
15161
15162
15163
15164#if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d11_h__)
15165
15184NVAPI_INTERFACE NvAPI_D3D_IsGSyncActive(__in IUnknown *pDeviceOrContext, __in NVDX_ObjectHandle primarySurface, __out BOOL *pIsGsyncActive);
15185#endif //if defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d11_h__)
15186
15187
15188
15191#if defined (__cplusplus) && ( defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
15193//
15194// FUNCTION NAME: NvAPI_D3D1x_DisableShaderDiskCache
15195//
15206NVAPI_INTERFACE NvAPI_D3D1x_DisableShaderDiskCache(IUnknown *pDevice);
15207
15208#endif //defined (__cplusplus) && ( defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
15209
15212#if defined (__cplusplus) && defined(__d3d11_h__)
15214//
15215// FUNCTION NAME: NvAPI_D3D11_MultiGPU_GetCaps
15216//
15225typedef struct _NV_MULTIGPU_CAPS_V1
15226{
15227 NvU32 multiGPUVersion;
15228 NvU32 reserved;
15229 NvU32 nTotalGPUs;
15230 NvU32 nSLIGPUs;
15231 NvU32 videoBridgePresent;
15232} NV_MULTIGPU_CAPS_V1, *PNV_MULTIGPU_CAPS_V1;
15233
15234#endif //defined(__cplusplus) && defined(__d3d11_h__)
15235
15238#if defined (__cplusplus) && defined(__d3d11_h__)
15239
15240typedef struct _NV_MULTIGPU_CAPS_V2
15241{
15242 NvU32 multiGPUVersion;
15243 union
15244 {
15245 NvU32 reserved;
15246 NvU32 version;
15247 };
15248 NvU32 nTotalGPUs;
15249 NvU32 nSLIGPUs;
15250 NvU32 videoBridgePresent;
15251 NvU32 NvLinkPresent;
15252 NvU32 fastNvLinkReads;
15253} NV_MULTIGPU_CAPS_V2, *PNV_MULTIGPU_CAPS_V2;
15254
15255#define NV_MULTIGPU_CAPS_VER1 MAKE_NVAPI_VERSION(NV_MULTIGPU_CAPS_V1, 1)
15256#define NV_MULTIGPU_CAPS_VER2 MAKE_NVAPI_VERSION(NV_MULTIGPU_CAPS_V2, 2)
15257
15258#define NV_MULTIGPU_CAPS_VER NV_MULTIGPU_CAPS_VER2
15259typedef NV_MULTIGPU_CAPS_V2 NV_MULTIGPU_CAPS;
15260typedef PNV_MULTIGPU_CAPS_V2 PNV_MULTIGPU_CAPS;
15261
15262#endif //defined(__cplusplus) && defined(__d3d11_h__)
15263
15266#if defined (__cplusplus) && defined(__d3d11_h__)
15268
15269#ifndef NV_MULTIGPU_CAPS_VER
15270typedef NV_MULTIGPU_CAPS_V1 NV_MULTIGPU_CAPS;
15271typedef PNV_MULTIGPU_CAPS_V1 PNV_MULTIGPU_CAPS;
15272#endif
15273
15274NVAPI_INTERFACE NvAPI_D3D11_MultiGPU_GetCaps(__inout PNV_MULTIGPU_CAPS pMultiGPUCaps);
15275
15276#endif //defined(__cplusplus) && defined(__d3d11_h__)
15277
15280#if defined (__cplusplus) && defined(__d3d11_h__)
15282//
15283// FUNCTION NAME: NvAPI_D3D11_MultiGPU_Init
15284//
15292NVAPI_INTERFACE NvAPI_D3D11_MultiGPU_Init(__in bool bEnable);
15293
15294#endif //defined(__cplusplus) && defined(__d3d11_h__)
15295
15298#if defined (__cplusplus) && defined(__d3d11_h__)
15300//
15301// FUNCTION NAME: NvAPI_D3D11_CreateMultiGPUDevice
15322
15323
15325
15326#define NVAPI_COPY_ASYNCHRONOUSLY 1
15327#endif //defined(__cplusplus) && defined(__d3d11_h__)
15328
15331#if defined (__cplusplus) && defined(__d3d11_h__)
15332#define NVAPI_COPY_P2P_READ 2
15333#endif //defined(__cplusplus) && defined(__d3d11_h__)
15334
15337#if defined (__cplusplus) && defined(__d3d11_h__)
15338
15339#define NVAPI_CPU_RESOURCE 0xffffffff
15340
15341DECLARE_INTERFACE(ID3D11MultiGPUDevice_V1)
15342{
15344 STDMETHOD_(void,Destroy)(THIS) PURE;
15345 STDMETHOD_(UINT,SetGPUMask)(THIS_ __in UINT GPUMask) PURE;
15346 STDMETHOD_(NvAPI_Status,CopySubresourceRegion)(THIS_ __in ID3D11DeviceContext *pContext, __in ID3D11Resource *pDstResource, __in UINT DstSubresource,
15347 __in UINT DstGPUIndex, __in UINT DstX, __in UINT DstY, __in UINT DstZ,
15348 __in ID3D11Resource *pSrcResource, __in UINT SrcSubresource, __in UINT SrcGPUIndex,
15349 __in const D3D11_BOX *pSrcBox, __in UINT ExtendedFlags = 0) PURE;
15350#if defined(__d3d11_1_h__)
15351 STDMETHOD_(NvAPI_Status,CopySubresourceRegion1)(THIS_ __in ID3D11DeviceContext1 *pContext1, __in ID3D11Resource *pDstResource, __in UINT DstSubresource,
15352 __in UINT DstGPUIndex, __in UINT DstX, __in UINT DstY, __in UINT DstZ,
15353 __in ID3D11Resource *pSrcResource, __in UINT SrcSubresource, __in UINT SrcGPUIndex,
15354 __in const D3D11_BOX *pSrcBox, __in UINT CopyFlags, __in UINT ExtendedFlags = 0 ) PURE;
15355#else
15356 STDMETHOD_(NvAPI_Status,CopySubresourceRegion1)(THIS_ __in void *pContext1, __in ID3D11Resource *pDstResource, __in UINT DstSubresource,
15357 __in UINT DstGPUIndex, __in UINT DstX, __in UINT DstY, __in UINT DstZ,
15358 __in ID3D11Resource *pSrcResource, __in UINT SrcSubresource, __in UINT SrcGPUIndex,
15359 __in const D3D11_BOX *pSrcBox, __in UINT CopyFlags, __in UINT ExtendedFlags = 0 ) PURE;
15360#endif
15361 STDMETHOD_(NvAPI_Status,UpdateSubresource)(THIS_ __in ID3D11DeviceContext *pContext,__in ID3D11Resource *pDstResource, __in UINT DstSubresource, __in UINT DstGPUIndex,
15362 __in const D3D11_BOX *pDstBox, __in const void *pSrcData, __in UINT SrcRowPitch, __in UINT SrcDepthPitch) PURE;
15363 STDMETHOD_(NvAPI_Status,VSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15364 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15365 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15366 STDMETHOD_(NvAPI_Status,PSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15367 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15368 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15369 STDMETHOD_(NvAPI_Status,GSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15370 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15371 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15372 STDMETHOD_(NvAPI_Status,DSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15373 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15374 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15375 STDMETHOD_(NvAPI_Status,HSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15376 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15377 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15378 STDMETHOD_(NvAPI_Status,CSSetConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT StartSlot,
15379 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers,
15380 __in UINT *const pFirstConstant = NULL, __in UINT *const pNumConstants = NULL) PURE;
15381 STDMETHOD_(NvAPI_Status,SetViewports)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT NumViewports,
15382 __in const D3D11_VIEWPORT *pViewports) PURE;
15383 STDMETHOD_(NvAPI_Status,SetScissorRects)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask, __in UINT NumRects,
15384 __in const D3D11_RECT *pRects) PURE;
15385 STDMETHOD_(HRESULT,GetData)(THIS_ __in ID3D11DeviceContext *pContext, __in ID3D11Asynchronous *pAsync, __in UINT GPUIndex,
15386 __out void *pData, __in UINT DataSize, __in UINT GetDataFlags) PURE;
15387#if defined(__d3d11_2_h__)
15388 STDMETHOD_(NvAPI_Status,UpdateTiles)(THIS_ __in ID3D11DeviceContext2 *pContext2, __in ID3D11Resource *pDestTiledResource,
15389 __in UINT GPUMask, __in const D3D11_TILED_RESOURCE_COORDINATE *pDestTileRegionStartCoordinate,
15390 __in const D3D11_TILE_REGION_SIZE *pDestTileRegionSize, __in const void *pSourceTileData,
15391 __in UINT Flags) PURE;
15392#else
15393 STDMETHOD_(NvAPI_Status,UpdateTiles)(THIS_ __in void *pContext2, __in ID3D11Resource *pDestTiledResource,
15394 __in UINT GPUMask, __in const void *pDestTileRegionStartCoordinate,
15395 __in const void *pDestTileRegionSize, __in const void *pSourceTileData,
15396 __in UINT Flags) PURE;
15397#endif
15398
15399 STDMETHOD_(NvAPI_Status,CreateFences)(THIS_ __in UINT count, __out void **ppFences) PURE;
15400 STDMETHOD_(NvAPI_Status,SetFence)(THIS_ __in UINT GPUIndex, __in void *hFence, __in UINT64 value) PURE;
15401 STDMETHOD_(NvAPI_Status,WaitForFence)(THIS_ __in UINT GPUIMask, __in void *hFence, __in UINT64 value) PURE;
15402 STDMETHOD_(NvAPI_Status,FreeFences)(THIS_ __in UINT count, __in void **ppFences) PURE;
15403 STDMETHOD_(NvAPI_Status,PresentCompositingConfig )(THIS_ __in IUnknown *pSwapChain, __in UINT GPUMask,
15404 __in const D3D11_RECT *pRects, __in UINT flags) PURE;
15406
15408 STDMETHOD_(NvAPI_Status,SetContextGPUMask)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT GPUMask) PURE;
15409 STDMETHOD_(NvAPI_Status,GetVideoBridgeStatus)(THIS_ __in IUnknown *pSwapChain, __in UINT* pVideoBridgeStatus) PURE;
15411
15413 STDMETHOD_(NvAPI_Status,CreateMultiGPUConstantBuffer)(THIS_ __in const D3D11_BUFFER_DESC *pDesc, __in_opt const D3D11_SUBRESOURCE_DATA **ppInitialData, __out ID3D11Buffer **ppBuffer) PURE;
15414 STDMETHOD_(NvAPI_Status,ReleaseMultiGPUConstantBuffer)(THIS_ __in ID3D11Buffer *pBuffer) PURE;
15415
15417 // Following XXSetMGPUConstantBuffers work the same way as DX XXSetConstantBuffers
15418 // The difference is that
15419 // 1. They are setting constant buffers on GPUs that are defined by
15420 // current GPU mask that is set via SetGPUMask.
15421 // 2. For constant buffer created via CreateMultiGPUConstantBuffer these calls set GPU specific constant buffer.
15422 // 3. For regular constant buffers these calls set the same constant buffer on all GPUs defined by 1.
15423 // 4. If these functions are called in deferred context then GPUs are defined as GlobalGPUmask&LocalGPUMask
15424 // where GlobalGPUmask is GPUMask set before CL execution
15425 // and LocalGPUMask is current GPUMask set in CL.
15427 STDMETHOD_(NvAPI_Status,VSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15428 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15429 STDMETHOD_(NvAPI_Status,PSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15430 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15431 STDMETHOD_(NvAPI_Status,GSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15432 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15433 STDMETHOD_(NvAPI_Status,DSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15434 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15435 STDMETHOD_(NvAPI_Status,HSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15436 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15437 STDMETHOD_(NvAPI_Status,CSSetMGPUConstantBuffers)(THIS_ __in ID3D11DeviceContext *pContext, __in UINT StartSlot,
15438 __in UINT NumBuffers, __in ID3D11Buffer *const *ppConstantBuffers) PURE;
15439
15440 STDMETHOD_(NvAPI_Status,UpdateConstantBuffer)(__in ID3D11DeviceContext *pContext, __in ID3D11Buffer *pBuffer, __in const void *pSrcData, __in_opt UINT GPUMask = 0) PURE;
15442};
15443
15445#define FENCE_SYNCHRONIZATION_START(pMultiGPUDevice, hFence, Value, srcGpu, dstGpu) \
15446 pMultiGPUDevice->SetFence(dstGpu, hFence, Value); \
15447 pMultiGPUDevice->WaitForFence(1 << (srcGpu), hFence, Value); \
15448 Value++;
15449
15450#define FENCE_SYNCHRONIZATION_END(pMultiGPUDevice, hFence, Value, srcGpu, dstGpu) \
15451 pMultiGPUDevice->SetFence(srcGpu, hFence, Value); \
15452 pMultiGPUDevice->WaitForFence(1 << (dstGpu), hFence, Value); \
15453 Value++;
15454
15456#define NVAPI_PRESENT_COMPOSITING_CONFIG_FLAG_USE_VIDEO_BRIDGE 0x01
15457#define NVAPI_PRESENT_COMPOSITING_CONFIG_FLAG_CLEAR_OUTBANDS 0x02
15458#define NVAPI_PRESENT_COMPOSITING_CONFIG_FLAG_GET_VIDEO_BRIDGE_STATUS 0x80000000
15459
15460#define NVAPI_VIDEO_BRIDGE_STATUS_AVAILABLE 0
15461#define NVAPI_VIDEO_BRIDGE_STATUS_NOT_AVAILABLE 1
15462#define NVAPI_VIDEO_BRIDGE_STATUS_FAILED_ACCESS 2
15463#define NVAPI_VIDEO_BRIDGE_STATUS_UNKNOWN 3
15464
15465#define NVAPI_ALL_GPUS 0
15466typedef ID3D11MultiGPUDevice_V1 ID3D11MultiGPUDevice;
15467
15468#define ID3D11MultiGPUDevice_VER1 MAKE_NVAPI_VERSION(ID3D11MultiGPUDevice_V1, 1)
15469#define ID3D11MultiGPUDevice_VER2 MAKE_NVAPI_VERSION(ID3D11MultiGPUDevice_V1, 2)
15470#define ID3D11MultiGPUDevice_VER3 MAKE_NVAPI_VERSION(ID3D11MultiGPUDevice_V1, 3)
15471#define ID3D11MultiGPUDevice_VER ID3D11MultiGPUDevice_VER3
15472
15473#define ALL_GPUS 0
15474
15476NVAPI_INTERFACE NvAPI_D3D11_CreateMultiGPUDevice(__in ID3D11Device *pDevice, __in ULONG version, __out ULONG *currentVersion, __out ID3D11MultiGPUDevice **ppD3D11MultiGPUDevice, __in UINT maxGpus=ALL_GPUS);
15477
15478#endif //defined(__cplusplus) && defined(__d3d11_h__)
15479
15485{
15486 NvU32 version; // parameter struct version
15487 NvU32 bSinglePassStereoSupported; // Single Pass Stereo supported
15489
15491{
15492 NvU32 version; // _IN_ parameter struct version
15493 NvU32 bSinglePassStereoSupported : 1; // _OUT_ Single Pass Stereo supported
15494 NvU32 bSinglePassStereoXYZWSupported : 1; // _OUT_ Single Pass Stereo XYZW supported
15495 NvU32 reserved : 30; // _INOUT_ bits reserved for future use
15497
15499#define NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_V1, 1)
15500#define NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER2 MAKE_NVAPI_VERSION(NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_V2, 2)
15501#define NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER2
15502
15503#ifndef NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER
15505#define NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_V1, 1)
15506#define NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS_VER1
15507#endif
15508
15509#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15511//
15512// FUNCTION NAME: NvAPI_D3D_QuerySinglePassStereoSupport
15513//
15528NVAPI_INTERFACE NvAPI_D3D_QuerySinglePassStereoSupport(__in IUnknown *pDevice,
15529 __inout NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS *pQuerySinglePassStereoSupportedParams);
15530
15531#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15532
15533#if defined(__cplusplus) && defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
15535//
15536// FUNCTION NAME: NvAPI_D3D_SetSinglePassStereoMode
15537//
15559NVAPI_INTERFACE NvAPI_D3D_SetSinglePassStereoMode(__in IUnknown *pDevOrContext, __in NvU32 numViews, __in NvU32 renderTargetIndexOffset, __in NvU8 independentViewportMaskEnable);
15560
15561#endif //defined(__cplusplus) && defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
15562
15563#if defined(__cplusplus) && ( defined(__d3d12_h__))
15565//
15566// FUNCTION NAME: NvAPI_D3D12_QuerySinglePassStereoSupport
15567//
15582
15583NVAPI_INTERFACE NvAPI_D3D12_QuerySinglePassStereoSupport(__in ID3D12Device *pDevice,
15584 __inout NV_QUERY_SINGLE_PASS_STEREO_SUPPORT_PARAMS *pQuerySinglePassStereoSupportedParams);
15585
15586#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
15587
15588#if defined(__cplusplus) && ( defined(__d3d12_h__))
15590//
15591// FUNCTION NAME: NvAPI_D3D12_SetSinglePassStereoMode
15592//
15615
15616NVAPI_INTERFACE NvAPI_D3D12_SetSinglePassStereoMode(__in ID3D12GraphicsCommandList* pCommandList,
15617 __in NvU32 numViews,
15618 __in NvU32 renderTargetIndexOffset,
15619 __in NvU8 independentViewportMaskEnable);
15620
15621#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
15622
15627
15629{
15630 NvU32 version; // _IN_ parameter struct version
15631 NvU32 bMultiViewSupported : 1; // _OUT_ MultiView supported (Render 4 views in a single pass)
15632 NvU32 bSinglePassStereoSupported : 1; // _OUT_ StereoX supported (Render 2 views in a single pass)
15633 NvU32 bSinglePassStereoXYZWSupported : 1; // _OUT_ StereoXYZW supported (Render 2 views in a single pass)
15634 NvU32 reserved : 29; // _INOUT_ bits reserved for future use
15636
15638#define NV_QUERY_MULTIVIEW_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_MULTIVIEW_SUPPORT_PARAMS_V1, 1)
15639#define NV_QUERY_MULTIVIEW_SUPPORT_PARAMS_VER NV_QUERY_MULTIVIEW_SUPPORT_PARAMS_VER1
15640#define NV_MULTIVIEW_MAX_SUPPORTED_VIEWS 4
15641
15642#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15644//
15645// FUNCTION NAME: NvAPI_D3D_QueryMultiViewSupport
15646//
15663NVAPI_INTERFACE NvAPI_D3D_QueryMultiViewSupport(__in IUnknown *pDevice,
15664 __inout NV_QUERY_MULTIVIEW_SUPPORT_PARAMS *pQueryMultiViewSupportedParams);
15665
15666#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15667
15673{
15674 NvU32 version; // _IN_ parameter struct version
15675 NvU32 numViews; // _IN_ Number of views to render.
15676 NvU32 renderTargetIndexOffset[NV_MULTIVIEW_MAX_SUPPORTED_VIEWS]; // _IN_ Offset between render targets for each of the per views.
15677 NvU8 independentViewportMaskEnable; // _IN_ Is the independent viewport mask enabled.
15679
15681#define NV_MULTIVIEW_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_MULTIVIEW_PARAMS_V1, 1)
15682#define NV_MULTIVIEW_PARAMS_VER NV_MULTIVIEW_PARAMS_VER1
15683
15684#if defined(__cplusplus) && defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
15686//
15687// FUNCTION NAME: NvAPI_D3D_SetMultiViewMode
15688//
15710NVAPI_INTERFACE NvAPI_D3D_SetMultiViewMode(__in IUnknown *pDevOrContext, __in NV_MULTIVIEW_PARAMS *pMultiViewParams);
15711
15712#endif //defined(__cplusplus) && defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
15713
15719{
15720 NvU32 version; // parameter struct version
15721 NvU32 bModifiedWSupported; // Modified W supported
15723
15725#define NV_QUERY_MODIFIED_W_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_MODIFIED_W_SUPPORT_PARAMS_V1, 1)
15726#define NV_QUERY_MODIFIED_W_SUPPORT_PARAMS_VER NV_QUERY_MODIFIED_W_SUPPORT_PARAMS_VER1
15727
15728#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15730//
15731// FUNCTION NAME: NvAPI_D3D_QueryModifiedWSupport
15732//
15747NVAPI_INTERFACE NvAPI_D3D_QueryModifiedWSupport(__in IUnknown *pDev,
15748 __inout NV_QUERY_MODIFIED_W_SUPPORT_PARAMS *pQueryModifiedWSupportedParams);
15749#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15750
15753#define NV_MODIFIED_W_MAX_VIEWPORTS 16
15754
15756{
15757 float fA; // A coefficient in w' = w + Ax + By
15758 float fB; // B coefficient in w' = w + Ax + By
15759 float fAReserved; // reserved
15760 float fBReserved; // reserved
15761
15762 float fReserved[2]; // reserved
15764
15766{
15767 NvU32 version; // parameter struct version
15768 NvU32 numEntries; // number of valid NV_MODIFIED_W_COEFFICIENTS structs in array
15769 NV_MODIFIED_W_COEFFICIENTS modifiedWCoefficients[NV_MODIFIED_W_MAX_VIEWPORTS]; // coefficients
15770
15771 NvU32 id; // reserved
15772 NvU32 reserved[NV_MODIFIED_W_MAX_VIEWPORTS]; // reserved
15774
15776#define NV_MODIFIED_W_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_MODIFIED_W_PARAMS_V1, 1)
15777#define NV_MODIFIED_W_PARAMS_VER NV_MODIFIED_W_PARAMS_VER1
15778
15779#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15781//
15782// FUNCTION NAME: NvAPI_D3D_SetModifiedWMode
15783//
15803NVAPI_INTERFACE NvAPI_D3D_SetModifiedWMode(__in IUnknown *pDevOrContext, __in NV_MODIFIED_W_PARAMS *psModifiedWParams);
15804
15805#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15806
15807#if defined(__cplusplus) && ( defined(__d3d12_h__))
15809//
15810// FUNCTION NAME: NvAPI_D3D12_QueryModifiedWSupport
15811//
15826
15827NVAPI_INTERFACE NvAPI_D3D12_QueryModifiedWSupport(__in ID3D12Device *pDevice,
15828 __inout NV_QUERY_MODIFIED_W_SUPPORT_PARAMS *pQueryModifiedWSupportedParams);
15829
15830#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
15831
15832#if defined(__cplusplus) && ( defined(__d3d12_h__))
15834//
15835// FUNCTION NAME: NvAPI_D3D12_SetModifiedWMode
15836//
15857
15858NVAPI_INTERFACE NvAPI_D3D12_SetModifiedWMode(__in ID3D12GraphicsCommandList* pCommandList,
15859 __in NV_MODIFIED_W_PARAMS *pModifiedWParams);
15860
15861#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
15862
15863
15864#if defined(__cplusplus) && (defined(__d3d11_h__))
15865
15868DECLARE_INTERFACE(ID3DLateLatchObject_V1)
15869{
15870 STDMETHOD_(UINT,Release) (THIS) PURE;
15871 STDMETHOD_(NvAPI_Status,Latch) (THIS_ __in IUnknown* pContext = NULL) PURE;
15872 STDMETHOD_(ID3D11Buffer*,GetD3D11Buffer) (THIS_ __in UINT index = 0) PURE;
15873 STDMETHOD_(UINT,GetBufferCount) (THIS) PURE;
15874 STDMETHOD_(NvAPI_Status,UpdateData) (THIS_ __in void **ppData) PURE;
15875 STDMETHOD_(NvAPI_Status,UpdateData) (THIS_ __in void *pData, __in size_t offset,
15876 __in size_t size, __in UINT index = 0) PURE;
15877};
15878
15881typedef ID3DLateLatchObject_V1 ID3DLateLatchObject;
15882#define ID3DLateLatchObject_VER1 MAKE_NVAPI_VERSION(ID3DLateLatchObject_V1, 1)
15883#define ID3DLateLatchObject_VER ID3DLateLatchObject_VER1
15884
15885typedef struct _NV_D3D_LATELATCH_OBJECT_DESC_V1
15886{
15887 NvU32 version;
15888 NvU32 numBuffers; // _IN_ Number of LateLatch buffers that the app wants to create.
15889 D3D11_BUFFER_DESC **ppBufferDesc; // _IN_ Description of buffers
15890 ID3DLateLatchObject **ppD3DLateLatchObject; // _Out_ Pointer to created interface
15891} NV_D3D_LATELATCH_OBJECT_DESC_V1;
15892
15893typedef NV_D3D_LATELATCH_OBJECT_DESC_V1 NV_D3D_LATELATCH_OBJECT_DESC;
15894#define NV_D3D_LATELATCH_OBJECT_DESC_VER1 MAKE_NVAPI_VERSION(NV_D3D_LATELATCH_OBJECT_DESC_V1, 1)
15895#define NV_D3D_LATELATCH_OBJECT_DESC_VER NV_D3D_LATELATCH_OBJECT_DESC_VER1
15896
15898//
15899// FUNCTION NAME: NvAPI_D3D_CreateLateLatchObject
15900//
15916
15917NVAPI_INTERFACE NvAPI_D3D_CreateLateLatchObject(__in IUnknown *pDevice, __inout NV_D3D_LATELATCH_OBJECT_DESC* pLateLatchObjectDesc);
15918
15919#endif // defined(__cplusplus) && (defined(__d3d11_h__))
15920
15921
15922
15923#if defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
15926typedef struct _NV_QUERY_LATELATCH_SUPPORT_PARAMS
15927{
15928 NvU32 version;
15929 NvU32 bLateLatchSupported;
15930} NV_QUERY_LATELATCH_SUPPORT_PARAMS_V1;
15931
15932typedef NV_QUERY_LATELATCH_SUPPORT_PARAMS_V1 NV_QUERY_LATELATCH_SUPPORT_PARAMS;
15933#define NV_QUERY_LATELATCH_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_LATELATCH_SUPPORT_PARAMS_V1, 1)
15934#define NV_QUERY_LATELATCH_SUPPORT_PARAMS_VER NV_QUERY_LATELATCH_SUPPORT_PARAMS_VER1
15935
15937//
15938// FUNCTION NAME: NvAPI_D3D_QueryLateLatchSupport
15939//
15955NVAPI_INTERFACE NvAPI_D3D_QueryLateLatchSupport(__in IUnknown *pDevice,
15956 __inout NV_QUERY_LATELATCH_SUPPORT_PARAMS *pQueryLateLatchSupportParams);
15957#endif // defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
15958
15959
15960
15961#if defined (__cplusplus) && (defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15963//
15964// FUNCTION NAME: NvAPI_D3D_RegisterDevice
15965//
15979NVAPI_INTERFACE NvAPI_D3D_RegisterDevice(__in IUnknown *pDev);
15980
15981#endif //if defined(__cplusplus) && (defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__))
15982
15983
15984
15985#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
15986
15988//
15989// FUNCTION NAME: NvAPI_D3D11_MultiDrawInstancedIndirect
15990//
16011
16012NVAPI_INTERFACE NvAPI_D3D11_MultiDrawInstancedIndirect(__in ID3D11DeviceContext *pDevContext11,
16013 __in NvU32 drawCount,
16014 __in ID3D11Buffer *pBuffer,
16015 __in NvU32 alignedByteOffsetForArgs,
16016 __in NvU32 alignedByteStrideForArgs);
16017
16018#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
16019
16020
16021#if defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
16022
16024//
16025// FUNCTION NAME: NvAPI_D3D11_MultiDrawIndexedInstancedIndirect
16026//
16047
16048NVAPI_INTERFACE NvAPI_D3D11_MultiDrawIndexedInstancedIndirect(__in ID3D11DeviceContext *pDevContext11,
16049 __in NvU32 drawCount,
16050 __in ID3D11Buffer *pBuffer,
16051 __in NvU32 alignedByteOffsetForArgs,
16052 __in NvU32 alignedByteStrideForArgs);
16053
16054#endif //defined (__cplusplus) && (defined(__d3d11_h__) || defined(__d3d11_1_h__))
16055
16058#if defined (__cplusplus) && ( defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) ||defined(__d3d11_h__) )
16060//
16061// FUNCTION NAME: NvAPI_D3D_ImplicitSLIControl
16062//
16072
16074typedef enum _IMPLICIT_SLI_CONTROL
16075{
16076 DISABLE_IMPLICIT_SLI = 0,
16077 ENABLE_IMPLICIT_SLI = 1,
16078} IMPLICIT_SLI_CONTROL;
16079
16081NVAPI_INTERFACE NvAPI_D3D_ImplicitSLIControl(__in IMPLICIT_SLI_CONTROL implicitSLIControl);
16082
16083#endif //defined (__cplusplus) && ( defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) ||defined(__d3d11_h__) )
16084
16085
16086#if defined (__cplusplus) && defined(__d3d12_h__)
16088//
16089// FUNCTION NAME: NvAPI_D3D12_GetNeedsAppFPBlendClamping
16090//
16108
16109NVAPI_INTERFACE NvAPI_D3D12_GetNeedsAppFPBlendClamping(__in ID3D12Device *pDevice,
16110 __out bool *pAppClampNeeded);
16111
16112#endif //defined(__cplusplus) && defined(__d3d12_h__)
16113
16116
16117#if defined (__cplusplus) && defined(__d3d12_h__)
16119//
16120// FUNCTION NAME: NvAPI_D3D12_UseDriverHeapPriorities
16121//
16136
16137NVAPI_INTERFACE NvAPI_D3D12_UseDriverHeapPriorities(__in ID3D12Device *pDevice);
16138
16139#endif // defined (__cplusplus) && defined(__d3d12_h__)
16140
16143#if defined(__cplusplus) && ( defined(__d3d12_h__))
16144
16145
16146typedef struct _NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS
16147{
16148 __in NvU32 version;
16149 __in ID3D12Device *pDevice;
16150 __in ID3D12Resource *pSwapChainBuffer;
16151 __in NvU32 companionBufferCount;
16152 __inout ID3D12Resource **ppCompanionResources;
16153} NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_V1;
16154
16155typedef NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_V1 NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS;
16156#define NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_VER1 MAKE_NVAPI_VERSION(NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_V1, 1)
16157#define NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_VER NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS_VER1
16158
16160//
16161// FUNCTION NAME: NvAPI_D3D12_Mosaic_GetCompanionAllocations
16162//
16178
16179NVAPI_INTERFACE NvAPI_D3D12_Mosaic_GetCompanionAllocations(__inout NV_D3D12_MOSAIC_GETCOMPANIONALLOCATIONS *params);
16180
16181#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
16182
16185#if defined(__cplusplus) && ( defined(__d3d12_h__))
16186
16187typedef struct _NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS
16188{
16189 __in NvU32 version;
16190 __in ID3D12Device *pDevice;
16191 __in ID3D12Resource *pSwapChainBuffer;
16192 __inout NvU32 *pPartitionCount;
16193 __inout RECT *pViewport;
16194 __inout NvU32 *pNodeMask;
16195} NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_V1;
16196
16197typedef NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_V1 NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS;
16198#define NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_VER1 MAKE_NVAPI_VERSION(NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_V1, 1)
16199#define NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_VER NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS_VER1
16200
16202//
16203// FUNCTION NAME: NvAPI_D3D12_Mosaic_GetViewportAndGpuPartitions
16204//
16220
16221NVAPI_INTERFACE NvAPI_D3D12_Mosaic_GetViewportAndGpuPartitions(__inout NV_D3D12_MOSAIC_GETVIEWPORTANDGPUPARTITIONS *params);
16222
16223#endif // defined(__cplusplus) && ( defined(__d3d12_h__))
16224
16225
16226#if defined(__cplusplus) && (defined(__d3d11_h__))
16229
16230typedef struct _NV_D3D1x_GRAPHICS_CAPS_V1
16231{
16232 NvU32 bExclusiveScissorRectsSupported : 1;
16233 NvU32 bVariablePixelRateShadingSupported : 1;
16234 NvU32 reservedBits : 30; // Reserved bits for future expansion
16235 NvU32 reserved[7]; // Reserved for future expansion
16236} NV_D3D1x_GRAPHICS_CAPS_V1;
16237
16238#define NV_D3D1x_GRAPHICS_CAPS_VER1 MAKE_NVAPI_VERSION(NV_D3D1x_GRAPHICS_CAPS_V1, 1)
16239
16240typedef struct _NV_D3D1x_GRAPHICS_CAPS_V2
16241{
16242 NvU32 bExclusiveScissorRectsSupported : 1;
16243 NvU32 bVariablePixelRateShadingSupported : 1;
16244 NvU32 bFastUAVClearSupported : 1;
16245 NvU32 reservedBits : 29; // Reserved bits for future expansion
16246 NvU16 majorSMVersion;
16247 NvU16 minorSMVersion;
16248 NvU32 reserved[14]; // Reserved for future expansion
16249} NV_D3D1x_GRAPHICS_CAPS_V2;
16250
16251typedef NV_D3D1x_GRAPHICS_CAPS_V2 NV_D3D1x_GRAPHICS_CAPS;
16252#define NV_D3D1x_GRAPHICS_CAPS_VER2 MAKE_NVAPI_VERSION(NV_D3D1x_GRAPHICS_CAPS_V2, 2)
16253#define NV_D3D1x_GRAPHICS_CAPS_VER NV_D3D1x_GRAPHICS_CAPS_VER2
16254
16256//
16257// FUNCTION NAME: NvAPI_D3D1x_GetGraphicsCapabilities
16258//
16278
16279NVAPI_INTERFACE NvAPI_D3D1x_GetGraphicsCapabilities(__in IUnknown *pDevice,
16280 __in NvU32 structVersion,
16281 __inout NV_D3D1x_GRAPHICS_CAPS *pGraphicsCaps);
16282
16283#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16284
16285#if defined(__cplusplus) && (defined(__d3d12_h__))
16288
16289typedef struct _NV_D3D12_GRAPHICS_CAPS_V1
16290{
16291 NvU32 bExclusiveScissorRectsSupported : 1;
16292 NvU32 bVariablePixelRateShadingSupported : 1;
16293 NvU32 bFastUAVClearSupported : 1;
16294 NvU32 reservedBits : 29; // Reserved bits for future expansion
16295 NvU16 majorSMVersion;
16296 NvU16 minorSMVersion;
16297 NvU32 reserved[6]; // Reserved for future expansion
16298} NV_D3D12_GRAPHICS_CAPS_V1;
16299
16300typedef NV_D3D12_GRAPHICS_CAPS_V1 NV_D3D12_GRAPHICS_CAPS;
16301#define NV_D3D12_GRAPHICS_CAPS_VER1 MAKE_NVAPI_VERSION(NV_D3D12_GRAPHICS_CAPS_V1, 1)
16302#define NV_D3D12_GRAPHICS_CAPS_VER NV_D3D12_GRAPHICS_CAPS_VER1
16303
16305//
16306// FUNCTION NAME: NvAPI_D3D12_GetGraphicsCapabilities
16307//
16327
16328NVAPI_INTERFACE NvAPI_D3D12_GetGraphicsCapabilities(__in IUnknown *pDevice,
16329 __in NvU32 structVersion,
16330 __inout NV_D3D12_GRAPHICS_CAPS *pGraphicsCaps);
16331
16332#endif // defined(__cplusplus) && (defined(__d3d12_h__))
16333
16334
16335#if defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16336#define NV_MAX_NUM_EXCLUSIVE_SCISSOR_RECTS 16
16337#endif // defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16338
16339#if defined(__cplusplus) && (defined(__d3d11_h__))
16342
16343typedef struct _NV_D3D11_EXCLUSIVE_SCISSOR_RECT_DESC_V1
16344{
16345 bool enableExclusiveScissorRect;
16346 D3D11_RECT scissorRect;
16347} NV_D3D11_EXCLUSIVE_SCISSOR_RECT_DESC_V1;
16348
16349typedef struct _NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_V1
16350{
16351 NvU32 version;
16352 NvU32 numRects;
16353 // \note Passing zero will globally disable Exclusive Scissor Rects
16354 // \note Max value can be equal to NV_MAX_NUM_EXCLUSIVE_SCISSOR_RECTS
16355 NV_D3D11_EXCLUSIVE_SCISSOR_RECT_DESC_V1 *pRects;
16356} NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_V1;
16357
16358typedef NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_V1 NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC;
16359typedef NV_D3D11_EXCLUSIVE_SCISSOR_RECT_DESC_V1 NV_D3D11_EXCLUSIVE_SCISSOR_RECT_DESC;
16360#define NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_VER1 MAKE_NVAPI_VERSION(NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_V1, 1)
16361#define NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_VER NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC_VER1
16362
16364//
16365// FUNCTION NAME: NvAPI_D3D11_RSSetExclusiveScissorRects
16366//
16387
16388NVAPI_INTERFACE NvAPI_D3D11_RSSetExclusiveScissorRects(__in IUnknown *pContext,
16389 __in NV_D3D11_EXCLUSIVE_SCISSOR_RECTS_DESC *pExclusiveScissorRectsDesc);
16390
16391#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16392
16393#if defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16396
16397#define NV_MAX_PIXEL_SHADING_RATES 16 // Currently only 12 Shading Rates are available
16398#define NV_MAX_NUM_VIEWPORTS 16
16399
16400// Every element in Shading Rate Resource represents the shading rate for all pixels in the corresponding tile
16401// The Shading Rate Resource dimensions must be the bound render target size divided by the tile dimensions (width/height)
16402
16403#define NV_VARIABLE_PIXEL_SHADING_TILE_WIDTH 16 // Width of the tile, in pixels
16404#define NV_VARIABLE_PIXEL_SHADING_TILE_HEIGHT 16 // Height of the tile, in pixels
16405
16406typedef enum
16407{
16408 NV_PIXEL_X0_CULL_RASTER_PIXELS, // No shading, tiles are culled
16409 NV_PIXEL_X16_PER_RASTER_PIXEL, // 16 shading passes per 1 raster pixel
16410 NV_PIXEL_X8_PER_RASTER_PIXEL, // 8 shading passes per 1 raster pixel
16411 NV_PIXEL_X4_PER_RASTER_PIXEL, // 4 shading passes per 1 raster pixel
16412 NV_PIXEL_X2_PER_RASTER_PIXEL, // 2 shading passes per 1 raster pixel
16413 NV_PIXEL_X1_PER_RASTER_PIXEL, // Per-pixel shading
16414 NV_PIXEL_X1_PER_2X1_RASTER_PIXELS, // 1 shading pass per 2 raster pixels
16415 NV_PIXEL_X1_PER_1X2_RASTER_PIXELS, // 1 shading pass per 2 raster pixels
16416 NV_PIXEL_X1_PER_2X2_RASTER_PIXELS, // 1 shading pass per 4 raster pixels
16417 NV_PIXEL_X1_PER_4X2_RASTER_PIXELS, // 1 shading pass per 8 raster pixels
16418 NV_PIXEL_X1_PER_2X4_RASTER_PIXELS, // 1 shading pass per 8 raster pixels
16419 NV_PIXEL_X1_PER_4X4_RASTER_PIXELS // 1 shading pass per 16 raster pixels
16420} NV_PIXEL_SHADING_RATE;
16421#endif // defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16422
16423#if defined(__cplusplus) && (defined(__d3d11_h__))
16424typedef struct _NV_D3D11_VIEWPORT_SHADING_RATE_DESC_V1
16425{
16426 bool enableVariablePixelShadingRate;
16427 NV_PIXEL_SHADING_RATE shadingRateTable[NV_MAX_PIXEL_SHADING_RATES];
16428 // \note Shading Rate Resource View would be populated by application with indices of this table
16429} NV_D3D11_VIEWPORT_SHADING_RATE_DESC_V1;
16430
16431typedef struct _NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_V1
16432{
16433 NvU32 version;
16434 NvU32 numViewports;
16435 // \note Passing zero will globally disable Variable Pixel Rate Shading for all viewports immaterial of values in pViewports
16436 // \note Max value can be equal to NV_MAX_NUM_VIEWPORTS
16437 NV_D3D11_VIEWPORT_SHADING_RATE_DESC_V1 *pViewports;
16438} NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_V1;
16439
16440typedef NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_V1 NV_D3D11_VIEWPORTS_SHADING_RATE_DESC;
16441typedef NV_D3D11_VIEWPORT_SHADING_RATE_DESC_V1 NV_D3D11_VIEWPORT_SHADING_RATE_DESC;
16442#define NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_VER1 MAKE_NVAPI_VERSION(NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_V1, 1)
16443#define NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_VER NV_D3D11_VIEWPORTS_SHADING_RATE_DESC_VER1
16444
16446//
16447// FUNCTION NAME: NvAPI_D3D11_RSSetViewportsPixelShadingRates
16448//
16466
16467NVAPI_INTERFACE NvAPI_D3D11_RSSetViewportsPixelShadingRates(__in IUnknown *pContext,
16468 __in NV_D3D11_VIEWPORTS_SHADING_RATE_DESC *pShadingRateDesc);
16469
16470#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16471
16472#if defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16473
16474typedef enum _NV_SRRV_DIMENSION
16475{
16476 NV_SRRV_DIMENSION_TEXTURE2D = 4,
16477 NV_SRRV_DIMENSION_TEXTURE2DARRAY = 5,
16478} NV_SRRV_DIMENSION;
16479
16480typedef struct _NV_TEX2D_SRRV
16481{
16482 UINT MipSlice;
16483} NV_TEX2D_SRRV;
16484
16485typedef struct _NV_TEX2D_ARRAY_SRRV
16486{
16487 UINT MipSlice;
16488 UINT FirstArraySlice;
16489 UINT ArraySize;
16490} NV_TEX2D_ARRAY_SRRV;
16491#endif // defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16492
16493#if defined(__cplusplus) && (defined(__d3d11_h__))
16494typedef struct _NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_V1
16495{
16496 NvU32 version;
16497 DXGI_FORMAT Format;
16498 NV_SRRV_DIMENSION ViewDimension;
16499 union
16500 {
16501 NV_TEX2D_SRRV Texture2D;
16502 NV_TEX2D_ARRAY_SRRV Texture2DArray;
16503 };
16504} NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_V1;
16505
16506typedef NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_V1 NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC;
16507#define NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_VER1 MAKE_NVAPI_VERSION(NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_V1, 1)
16508#define NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_VER NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC_VER1
16509
16510DECLARE_INTERFACE_(__declspec(uuid("E14BE7F6-8FF5-4F5E-B63A-AD016EB8FBE5"))ID3D11NvShadingRateResourceView_V1, ID3D11View)
16511{
16512 BEGIN_INTERFACE
16513
16514 // *** IUnknown methods ***
16515 STDMETHOD(QueryInterface)(THIS_ REFIID riid, void **ppv) PURE;
16516 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
16517 STDMETHOD_(ULONG,Release)(THIS) PURE;
16518
16519 // **** ID3D11View method **/
16520 // Get Shading Rate Resource used while creating the Shading Rate Resource View
16521 STDMETHOD_(void,GetResource)(THIS_ _Outptr_ ID3D11Resource **ppResource) PURE;
16522
16523 // ** ID3D11NvShadingRateResourceView methods ***
16524 // The descriptor used while creating the Shading Rate Resource View
16525 STDMETHOD(GetDesc)(THIS_ NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC* pDesc) PURE;
16526
16527 END_INTERFACE
16528};
16529
16530typedef ID3D11NvShadingRateResourceView_V1 ID3D11NvShadingRateResourceView;
16531#define ID3D11NvShadingRateResourceView_VER1 MAKE_NVAPI_VERSION(ID3D11NvShadingRateResourceView_V1, 1)
16532#define ID3D11NvShadingRateResourceView_VER ID3D11NvShadingRateResourceView_VER1
16533
16535//
16536// FUNCTION NAME: NvAPI_D3D11_CreateShadingRateResourceView
16537//
16560
16561NVAPI_INTERFACE NvAPI_D3D11_CreateShadingRateResourceView(__in ID3D11Device *pDevice,
16562 __in ID3D11Resource *pShadingRateResource,
16563 __in NV_D3D11_SHADING_RATE_RESOURCE_VIEW_DESC *pShadingRateResourceViewDesc,
16564 __out ID3D11NvShadingRateResourceView **ppShadingRateResourceView);
16565
16566#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16567
16568#if defined(__cplusplus) && (defined(__d3d11_h__))
16569
16571//
16572// FUNCTION NAME: NvAPI_D3D11_RSSetShadingRateResourceView
16573//
16593
16594NVAPI_INTERFACE NvAPI_D3D11_RSSetShadingRateResourceView(__in IUnknown *pContext,
16595 __in ID3D11NvShadingRateResourceView *pShadingRateResourceView);
16596
16597#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16598
16599#if defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16603
16604// X, Y = sample position. S = sample number.
16605// The inner-most dimension is the sample number, followed by X and Y.
16606
16607typedef struct _NV_PIXEL_SRSO_1x2
16608{
16609 struct NV_PIXEL_SRSO_1x2_X1 { NvU8 Y[2]; } X1;
16610 struct NV_PIXEL_SRSO_1x2_X2 { NvU8 YS[2][2]; } X2;
16611 struct NV_PIXEL_SRSO_1x2_X4 { NvU8 YS[2][4]; } X4;
16612 struct NV_PIXEL_SRSO_1x2_X8 { NvU8 YS[2][8]; } X8;
16613} NV_PIXEL_SRSO_1x2;
16614
16615typedef struct _NV_PIXEL_SRSO_2x1
16616{
16617 struct NV_PIXEL_SRSO_2x1_X1 { NvU8 X[2]; } X1;
16618 struct NV_PIXEL_SRSO_2x1_X2 { NvU8 XS[2][2]; } X2;
16619 struct NV_PIXEL_SRSO_2x1_X4 { NvU8 XS[2][4]; } X4;
16620} NV_PIXEL_SRSO_2x1;
16621
16622typedef struct _NV_PIXEL_SRSO_2x2
16623{
16624 struct NV_PIXEL_SRSO_2x2_X1 { NvU8 YX[2][2]; } X1;
16625 struct NV_PIXEL_SRSO_2x2_X2 { NvU8 YXS[2][2][2]; } X2;
16626 struct NV_PIXEL_SRSO_2x2_X4 { NvU8 YXS[2][2][4]; } X4;
16627} NV_PIXEL_SRSO_2x2;
16628
16629typedef struct _NV_PIXEL_SRSO_2x4
16630{
16631 struct NV_PIXEL_SRSO_2x4_X1 { NvU8 YX[4][2]; } X1;
16632 struct NV_PIXEL_SRSO_2x4_X2 { NvU8 YXS[4][2][2]; } X2;
16633} NV_PIXEL_SRSO_2x4;
16634
16635typedef struct _NV_PIXEL_SRSO_4x2
16636{
16637 struct NV_PIXEL_SRSO_4x2_X1 { NvU8 YX[2][4]; } X1;
16638} NV_PIXEL_SRSO_4x2;
16639
16640typedef struct _NV_PIXEL_SRSO_4x4
16641{
16642 struct NV_PIXEL_SRSO_4x4_X1 { NvU8 YX[4][4]; } X1;
16643} NV_PIXEL_SRSO_4x4;
16644
16645typedef struct _NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_V1
16646{
16647 NvU32 version;
16648 NV_PIXEL_SRSO_1x2 Pixel_1x2;
16649 NV_PIXEL_SRSO_2x1 Pixel_2x1;
16650 NV_PIXEL_SRSO_2x2 Pixel_2x2;
16651 NV_PIXEL_SRSO_2x4 Pixel_2x4;
16652 NV_PIXEL_SRSO_4x2 Pixel_4x2;
16653 NV_PIXEL_SRSO_4x4 Pixel_4x4;
16654} NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_V1;
16655
16656typedef NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_V1 NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE;
16657#define NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_VER1 MAKE_NVAPI_VERSION(NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_V1, 1)
16658#define NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_VER NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE_VER1
16659
16660#endif // defined(__cplusplus) && (defined(__d3d11_h__) || defined(__d3d12_h__))
16661
16662#if defined(__cplusplus) && (defined(__d3d11_h__))
16664//
16665// FUNCTION NAME: NvAPI_D3D11_RSGetPixelShadingRateSampleOrder
16666//
16684
16685NVAPI_INTERFACE NvAPI_D3D11_RSGetPixelShadingRateSampleOrder(__in IUnknown *pContext,
16686 __out NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE* pSampleOrderTable);
16687
16688#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16689
16690#if defined(__cplusplus) && (defined(__d3d11_h__))
16691
16693//
16694// FUNCTION NAME: NvAPI_D3D11_RSSetPixelShadingRateSampleOrder
16695//
16713
16714NVAPI_INTERFACE NvAPI_D3D11_RSSetPixelShadingRateSampleOrder(__in IUnknown *pContext,
16715 __in NV_PIXEL_SHADING_RATE_SAMPLE_ORDER_TABLE* pSampleOrderTable);
16716
16717#endif // defined(__cplusplus) && (defined(__d3d11_h__))
16718
16721
16722#if defined(__cplusplus) && (defined(__d3d11_h__))
16723typedef struct _NV_VRS_HELPER_LATCH_GAZE_PARAMS_V1
16724{
16725 NvU32 version;
16726 NvU32 flags;
16727} NV_VRS_HELPER_LATCH_GAZE_PARAMS_V1;
16728
16729typedef NV_VRS_HELPER_LATCH_GAZE_PARAMS_V1 NV_VRS_HELPER_LATCH_GAZE_PARAMS;
16730#define NV_VRS_HELPER_LATCH_GAZE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_LATCH_GAZE_PARAMS_V1, 1)
16731#define NV_VRS_HELPER_LATCH_GAZE_PARAMS_VER NV_VRS_HELPER_LATCH_GAZE_PARAMS_VER1
16732
16733typedef enum _NV_VRS_CONTENT_TYPE
16734{
16735 NV_VRS_CONTENT_TYPE_INVALID = 0x0,
16736 NV_VRS_CONTENT_TYPE_FOVEATED_RENDERING = 0x1,
16737 NV_VRS_CONTENT_TYPE_MAX = NV_VRS_CONTENT_TYPE_FOVEATED_RENDERING
16738} NV_VRS_CONTENT_TYPE;
16739
16740typedef enum _NV_FOVEATED_RENDERING_SHADING_RATE_PRESET
16741{
16742 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_INVALID = 0,
16743 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_HIGHEST_PERFORMANCE = 1,
16744 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_HIGH_PERFORMANCE = 2,
16745 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_BALANCED = 3,
16746 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_HIGH_QUALITY = 4,
16747 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_HIGHEST_QUALITY = 5,
16748 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_CUSTOM = 6,
16749 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_MAX = NV_FOVEATED_RENDERING_SHADING_RATE_PRESET_CUSTOM
16750} NV_FOVEATED_RENDERING_SHADING_RATE_PRESET;
16751
16752typedef struct _NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_V1
16753{
16754 NvU32 version;
16755
16756 NV_PIXEL_SHADING_RATE InnerMostRegionShadingRate;
16757 NV_PIXEL_SHADING_RATE MiddleRegionShadingRate;
16758 NV_PIXEL_SHADING_RATE PeripheralRegionShadingRate;
16759} NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_V1;
16760
16761typedef NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_V1 NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC;
16762#define NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_VER1 MAKE_NVAPI_VERSION(NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_V1, 1)
16763#define NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_VER NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_VER1
16764
16765typedef enum _NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET
16766{
16767 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_INVALID = 0,
16768 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_WIDE = 1,
16769 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_BALANCED = 2,
16770 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_NARROW = 3,
16771 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_CUSTOM = 4,
16772 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_MAX = NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET_CUSTOM
16773} NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET;
16774
16775typedef struct _NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_V1
16776{
16777 NvU32 version;
16778
16779 float fInnermostRadii[2];
16780 float fMiddleRadii[2];
16781 float fPeripheralRadii[2];
16782} NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_V1;
16783
16784typedef NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_V1 NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC;
16785#define NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_VER1 MAKE_NVAPI_VERSION(NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_V1, 1)
16786#define NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_VER NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_VER1
16787
16788typedef struct _NV_FOVEATED_RENDERING_DESC_V1
16789{
16790 NvU32 version;
16791 NvU32 flags;
16792
16793 NV_FOVEATED_RENDERING_SHADING_RATE_PRESET ShadingRatePreset;
16794 NV_FOVEATED_RENDERING_CUSTOM_SHADING_RATE_PRESET_DESC_V1 ShadingRateCustomPresetDesc;
16795
16796 NV_FOVEATED_RENDERING_FOVEATION_PATTERN_PRESET FoveationPatternPreset;
16797 NV_FOVEATED_RENDERING_CUSTOM_FOVEATION_PATTERN_PRESET_DESC_V1 FoveationPatternCustomPresetDesc;
16798
16799 NvU32 GazeDataDeviceId;
16800 // Should be 0 if gaze data is provided only from a single device. Should be less than (MAX_NUMBER_OF_GAZE_DATA_PROVIDERS - 1)
16801
16802} NV_FOVEATED_RENDERING_DESC_V1;
16803
16804typedef NV_FOVEATED_RENDERING_DESC_V1 NV_FOVEATED_RENDERING_DESC;
16805#define NV_FOVEATED_RENDERING_DESC_VER1 MAKE_NVAPI_VERSION(NV_FOVEATED_RENDERING_DESC_V1, 1)
16806#define NV_FOVEATED_RENDERING_DESC_VER NV_FOVEATED_RENDERING_DESC_VER1
16807
16808typedef enum _NV_VRS_RENDER_MODE
16809{
16810 NV_VRS_RENDER_MODE_INVALID = 0,
16811 NV_VRS_RENDER_MODE_MONO = 1, // States mono rendering on the entire render target
16812 NV_VRS_RENDER_MODE_LEFT_EYE = 2, // States Left eye rendering of a stereo pair on the entire render target
16813 NV_VRS_RENDER_MODE_RIGHT_EYE = 3, // States Right eye rendering of a stereo pair on the entire render target
16814 NV_VRS_RENDER_MODE_STEREO = 4, // States side-by-side stereo rendering on the render target
16815 NV_VRS_RENDER_MODE_MAX = NV_VRS_RENDER_MODE_STEREO
16816} NV_VRS_RENDER_MODE;
16817
16818#define MAX_NUMBER_OF_GAZE_DATA_PROVIDERS 8 // Maximum number of gaze data providers / devices.
16819
16820typedef struct _NV_VRS_HELPER_ENABLE_PARAMS_V1
16821{
16822 NvU32 version;
16823 NvU32 flags;
16824
16825 NV_VRS_RENDER_MODE RenderMode;
16826 NV_VRS_CONTENT_TYPE ContentType;
16827
16828 NV_FOVEATED_RENDERING_DESC_V1 sFoveatedRenderingDesc;
16829} NV_VRS_HELPER_ENABLE_PARAMS_V1;
16830
16831typedef NV_VRS_HELPER_ENABLE_PARAMS_V1 NV_VRS_HELPER_ENABLE_PARAMS;
16832#define NV_VRS_HELPER_ENABLE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_ENABLE_PARAMS_V1, 1)
16833#define NV_VRS_HELPER_ENABLE_PARAMS_VER NV_VRS_HELPER_ENABLE_PARAMS_VER1
16834
16835typedef struct _NV_VRS_HELPER_DISABLE_PARAMS_V1
16836{
16837 NvU32 version;
16838 NvU32 reserved;
16839} NV_VRS_HELPER_DISABLE_PARAMS_V1;
16840
16841typedef NV_VRS_HELPER_DISABLE_PARAMS_V1 NV_VRS_HELPER_DISABLE_PARAMS;
16842#define NV_VRS_HELPER_DISABLE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_DISABLE_PARAMS_V1, 1)
16843#define NV_VRS_HELPER_DISABLE_PARAMS_VER NV_VRS_HELPER_DISABLE_PARAMS_VER1
16844
16845typedef struct _NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_V1
16846{
16847 NvU32 version;
16848 IUnknown **ppShadingRateResource;
16849 NV_PIXEL_SHADING_RATE shadingRateTable[NV_MAX_PIXEL_SHADING_RATES];
16850} NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_V1;
16851
16852typedef NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_V1 NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS;
16853#define NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_V1, 1)
16854#define NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_VER NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS_VER1
16855
16856typedef struct _NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_V1
16857{
16858 NvU32 version;
16859 NvU32 reserved;
16860} NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_V1;
16861
16862typedef NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_V1 NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS;
16863#define NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_V1, 1)
16864#define NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_VER NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS_VER1
16865
16866DECLARE_INTERFACE(ID3DNvVRSHelper_V1)
16867{
16868 BEGIN_INTERFACE
16869
16870 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
16871 STDMETHOD_(ULONG,Release)(THIS) PURE;
16872
16873 // Latches the latest gaze which will be used for subsequent foveated rendering. Recommended to be called once per frame before scene drawing begins.
16874 STDMETHOD_(NvAPI_Status,LatchGaze)(THIS_ IUnknown* pContext, NV_VRS_HELPER_LATCH_GAZE_PARAMS* pLatchGazeParams) PURE;
16875
16876 // Enables VRS with sepcified content type and preset. This can be called per draw call.
16877 STDMETHOD_(NvAPI_Status,Enable)(THIS_ IUnknown* pContext, NV_VRS_HELPER_ENABLE_PARAMS* pEnableParams) PURE;
16878
16879 // Disables VRS till re-enabled.
16880 STDMETHOD_(NvAPI_Status,Disable)(THIS_ IUnknown* pContext, NV_VRS_HELPER_DISABLE_PARAMS* pDisableParams) PURE;
16881
16882 // Creates a 2D texture, copies the current shading rate pattern on it and returns the pointer to this texture.
16883 // It also returns an array that conveys which value in the shading rate resource corresponds to which exact pixel shading rate.
16884 STDMETHOD_(NvAPI_Status,GetShadingRateResource)(THIS_ IUnknown* pContext, NV_VRS_HELPER_GET_SHADING_RATE_RESOURCE_PARAMS *pGetShadingRateResourceParams) PURE;
16885
16886 // Destroys all internally created shading rate resources and views.
16887 STDMETHOD_(NvAPI_Status,PurgeInternalShadingRateResources)(THIS_ IUnknown* pContext, NV_VRS_HELPER_PURGE_INTERNAL_RESOURCES_PARAMS* pPurgeParams) PURE;
16888
16889 END_INTERFACE
16890};
16891
16892typedef ID3DNvVRSHelper_V1 ID3DNvVRSHelper;
16893#define ID3DNvVRSHelper_VER1 MAKE_NVAPI_VERSION(ID3DNvVRSHelper_V1, 1)
16894#define ID3DNvVRSHelper_VER ID3DNvVRSHelper_VER1
16895
16896typedef struct _NV_VRS_HELPER_INIT_PARAMS_V1
16897{
16898 NvU32 version;
16899 NvU32 flags;
16900
16901 ID3DNvVRSHelper_V1 **ppVRSHelper;
16902} NV_VRS_HELPER_INIT_PARAMS_V1;
16903
16904typedef NV_VRS_HELPER_INIT_PARAMS_V1 NV_VRS_HELPER_INIT_PARAMS;
16905#define NV_VRS_HELPER_INIT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_VRS_HELPER_INIT_PARAMS_V1, 1)
16906#define NV_VRS_HELPER_INIT_PARAMS_VER NV_VRS_HELPER_INIT_PARAMS_VER1
16907
16911//
16912// FUNCTION NAME: NvAPI_D3D_InitializeVRSHelper
16913//
16932
16933NVAPI_INTERFACE NvAPI_D3D_InitializeVRSHelper(__in IUnknown *pDevice,
16934 __inout NV_VRS_HELPER_INIT_PARAMS *pInitializeVRSHelperParams);
16935
16936typedef enum _NV_GAZE_DATA_VALIDITY_FLAGS
16937{
16938 NV_GAZE_ORIGIN_VALID = 0x1,
16939 NV_GAZE_DIRECTION_VALID = 0x2,
16940 NV_GAZE_LOCATION_VALID = 0x4,
16941 NV_GAZE_VELOCITY_VALID = 0x8,
16942 NV_GAZE_PUPIL_DIAMETER_VALID = 0x10,
16943 NV_GAZE_EYE_OPENNESS_VALID = 0x20,
16944 NV_GAZE_EYE_SACCADE_DATA_VALID = 0x40
16945} NV_GAZE_DATA_VALIDITY_FLAGS;
16946
16947typedef struct _NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE
16948{
16949 NvU32 version;
16950
16951 NvU32 GazeDataValidityFlags;
16952
16953 float fGazeOrigin_mm[3];
16954 float fGazeDirection[3];
16955 float fGazeNormalizedLocation[2];
16956 float fGazeVelocity[2];
16957 float fPupilDiameter_mm;
16958 float fEyeOpenness;
16959 BOOL bInSaccade;
16960} NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1;
16961
16962typedef NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1 NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE;
16963#define NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_VER1 MAKE_NVAPI_VERSION(NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1, 1)
16964#define NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_VER NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_VER1
16965
16966typedef struct _NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS
16967{
16968 NvU32 version;
16969 NvU32 flags;
16970
16971 NvU64 Timestamp;
16972 union
16973 {
16974 NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1 sMonoData;
16975 struct
16976 {
16977 NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1 sLeftEye;
16978 NV_FOVEATED_RENDERING_GAZE_DATA_PER_EYE_V1 sRightEye;
16979 } sStereoData;
16980 };
16981} NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_V1;
16982
16983typedef NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_V1 NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS;
16984#define NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_V1, 1)
16985#define NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_VER NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS_VER1
16986
16987
16988DECLARE_INTERFACE(ID3DNvGazeHandler_V2)
16989{
16990 BEGIN_INTERFACE
16991
16992 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
16993 STDMETHOD_(ULONG,Release)(THIS) PURE;
16994
16995 // Updates the gaze data for foveated rendering
16996 STDMETHOD_(NvAPI_Status,UpdateGazeData)(THIS_ IUnknown* pContext, NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS* pUpdateGazeDataParams) PURE;
16997
16998
16999 END_INTERFACE
17000};
17001typedef ID3DNvGazeHandler_V2 ID3DNvGazeHandler;
17002#define ID3DNvGazeHandler_VER2 MAKE_NVAPI_VERSION(ID3DNvGazeHandler_V2, 2)
17003#define ID3DNvGazeHandler_VER ID3DNvGazeHandler_VER2
17004
17005DECLARE_INTERFACE(ID3DNvGazeHandler_V1)
17006{
17007 BEGIN_INTERFACE
17008
17009 STDMETHOD_(ULONG,AddRef)(THIS) PURE;
17010 STDMETHOD_(ULONG,Release)(THIS) PURE;
17011
17012 // Updates the gaze data for foveated rendering
17013 STDMETHOD_(NvAPI_Status,UpdateGazeData)(THIS_ IUnknown* pContext, NV_FOVEATED_RENDERING_UPDATE_GAZE_DATA_PARAMS* pUpdateGazeDataParams) PURE;
17014
17015 END_INTERFACE
17016};
17017#define ID3DNvGazeHandler_VER1 MAKE_NVAPI_VERSION(ID3DNvGazeHandler_V1, 1)
17018#ifndef ID3DNvGazeHandler_VER
17019typedef ID3DNvGazeHandler_V1 ID3DNvGazeHandler;
17020#define ID3DNvGazeHandler_VER ID3DNvGazeHandler_VER1
17021#endif
17022
17023typedef enum _NV_GAZE_DATA_TYPE
17024{
17025 NV_GAZE_DATA_INVALID = 0,
17026 NV_GAZE_DATA_MONO = 1,
17027 NV_GAZE_DATA_STEREO = 2,
17028 NV_GAZE_DATA_MAX = NV_GAZE_DATA_STEREO
17029} NV_GAZE_DATA_TYPE;
17030
17031typedef struct _NV_GAZE_HANDLER_INIT_PARAMS_V2
17032{
17033 NvU32 version;
17034
17035 NvU32 GazeDataDeviceId;
17036 // Should be 0 if gaze data is provided only from a single device. Should be less than (MAX_NUMBER_OF_GAZE_DATA_PROVIDERS - 1)
17037
17038 NV_GAZE_DATA_TYPE GazeDataType;
17039 NvU32 flags;
17040 float fHorizontalFOV;
17041 float fVericalFOV;
17042
17043 ID3DNvGazeHandler_V2 **ppNvGazeHandler;
17044} NV_GAZE_HANDLER_INIT_PARAMS_V2;
17045
17046typedef NV_GAZE_HANDLER_INIT_PARAMS_V2 NV_GAZE_HANDLER_INIT_PARAMS;
17047#define NV_GAZE_HANDLER_INIT_PARAMS_VER2 MAKE_NVAPI_VERSION(NV_GAZE_HANDLER_INIT_PARAMS_V2, 2)
17048#define NV_GAZE_HANDLER_INIT_PARAMS_VER NV_GAZE_HANDLER_INIT_PARAMS_VER2
17049
17050typedef struct _NV_GAZE_HANDLER_INIT_PARAMS_V1
17051{
17052 NvU32 version;
17053
17054 NvU32 GazeDataDeviceId;
17055 // Should be 0 if gaze data is provided only from a single device. Should be less than (MAX_NUMBER_OF_GAZE_DATA_PROVIDERS - 1)
17056
17057 NV_GAZE_DATA_TYPE GazeDataType;
17058 NvU32 flags;
17059 float fHorizontalFOV;
17060 float fVericalFOV;
17061
17062 ID3DNvGazeHandler_V1 **ppNvGazeHandler;
17063} NV_GAZE_HANDLER_INIT_PARAMS_V1;
17064
17065#define NV_GAZE_HANDLER_INIT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_GAZE_HANDLER_INIT_PARAMS_V1, 1)
17066#ifndef NV_GAZE_HANDLER_INIT_PARAMS_VER
17067typedef NV_GAZE_HANDLER_INIT_PARAMS_V1 NV_GAZE_HANDLER_INIT_PARAMS;
17068#define NV_GAZE_HANDLER_INIT_PARAMS_VER NV_GAZE_HANDLER_INIT_PARAMS_VER1
17069#endif
17070
17071#endif // defined(__cplusplus) && (defined(__d3d11_h__))
17072
17075
17076#if defined(__cplusplus) && (defined(__d3d11_h__))
17078//
17079// FUNCTION NAME: NvAPI_D3D_InitializeNvGazeHandler
17080//
17099
17100NVAPI_INTERFACE NvAPI_D3D_InitializeNvGazeHandler(__in IUnknown *pDevice,
17101 __inout NV_GAZE_HANDLER_INIT_PARAMS *pInitializeNvGazeHandlerParams);
17102
17103#endif // defined(__cplusplus) && (defined(__d3d11_h__))
17104
17107#if defined (__cplusplus) && defined(__d3d11_h__)
17108
17110
17111typedef enum NV_SMP_ASSIST_TYPE
17112{
17113 NV_SMP_ASSIST_NONE = 0,
17114 NV_SMP_ASSIST_MRS = 1, // SMP Assist required for Multi-Res Shading
17115 NV_SMP_ASSIST_LMS = 2, // SMP Assist required for Lens Matched Shading
17116 NV_SMP_ASSIST_NUM_TYPES
17117} NV_SMP_ASSIST_TYPE;
17118
17119typedef enum NV_SMP_ASSIST_LEVEL
17120{
17121 NV_SMP_ASSIST_LEVEL_FULL = 0, // Full assistance. App selects a pre-baked MRS/LMS config, driver handles correct setting of viewport, scissors and FastGS
17122 NV_SMP_ASSIST_LEVEL_PARTIAL = 1, // Partial assistance. App provides a custom MRS/LMS config, driver handles correct setting of viewport, scissors and FastGS
17123 NV_SMP_ASSIST_LEVEL_MINIMAL = 2, // Minimal assistance. App provides viewports and scissors. App sets FastGS as required. App sets LMS params as required (NvAPI_D3D_SetModifiedWMode). App provides SMPType as NONE. Driver handles correct setting of viewports and scissors.
17124 NV_SMP_ASSIST_NUM_LEVELS
17125} NV_SMP_ASSIST_LEVEL;
17126
17127typedef enum NV_MRS_CONFIG
17128{
17129 NV_MRS_CONFIG_BALANCED = 0,
17130 NV_MRS_CONFIG_AGGRESSIVE = 1,
17131 NV_MRS_CONFIG_OCULUSRIFT_CV1_CONSERVATIVE = 2,
17132 NV_MRS_CONFIG_OCULUSRIFT_CV1_BALANCED = 3,
17133 NV_MRS_CONFIG_OCULUSRIFT_CV1_AGGRESSIVE = 4,
17134 NV_MRS_CONFIG_HTC_VIVE_CONSERVATIVE = 5,
17135 NV_MRS_CONFIG_HTC_VIVE_BALANCED = 6,
17136 NV_MRS_CONFIG_HTC_VIVE_AGGRESSIVE = 7,
17137 NV_MRS_NUM_CONFIGS
17138} NV_MRS_CONFIG;
17139
17140typedef enum NV_LMS_CONFIG
17141{
17142 NV_LMS_CONFIG_OCULUSRIFT_CV1_CONSERVATIVE = 0,
17143 NV_LMS_CONFIG_OCULUSRIFT_CV1_BALANCED = 1,
17144 NV_LMS_CONFIG_OCULUSRIFT_CV1_AGGRESSIVE = 2,
17145 NV_LMS_CONFIG_HTC_VIVE_CONSERVATIVE = 3,
17146 NV_LMS_CONFIG_HTC_VIVE_BALANCED = 4,
17147 NV_LMS_CONFIG_HTC_VIVE_AGGRESSIVE = 5,
17148 NV_LMS_NUM_CONFIGS
17149} NV_LMS_CONFIG;
17150
17151#define NV_SMP_ASSIST_FLAGS_DEFAULT 0x00000000
17152
17153#define NV_SMP_ASSIST_MAX_VIEWPORTS 16
17154
17155typedef struct _NV_MRS_CUSTOM_CONFIG_V1
17156{
17157 float centerWidth;
17158 float centerHeight;
17159 float centerX;
17160 float centerY;
17161 float densityScaleX[3];
17162 float densityScaleY[3];
17163} NV_MRS_CUSTOM_CONFIG_V1;
17164
17165typedef NV_MRS_CUSTOM_CONFIG_V1 NV_MRS_CUSTOM_CONFIG;
17166
17167typedef struct _NV_MRS_INSTANCED_STEREO_CONFIG_V1
17168{
17169 float centerWidth[2];
17170 float centerHeight;
17171 float centerX[2];
17172 float centerY;
17173 float densityScaleX[5];
17174 float densityScaleY[3];
17175} NV_MRS_INSTANCED_STEREO_CONFIG_V1;
17176
17177typedef NV_MRS_INSTANCED_STEREO_CONFIG_V1 NV_MRS_INSTANCED_STEREO_CONFIG;
17178
17179typedef struct _NV_LMS_CUSTOM_CONFIG_V1
17180{
17181 float warpLeft;
17182 float warpRight;
17183 float warpUp;
17184 float warpDown;
17185
17186 float relativeSizeLeft;
17187 float relativeSizeRight;
17188 float relativeSizeUp;
17189 float relativeSizeDown;
17190} NV_LMS_CUSTOM_CONFIG_V1;
17191
17192typedef NV_LMS_CUSTOM_CONFIG_V1 NV_LMS_CUSTOM_CONFIG;
17193
17194typedef struct _NV_LMS_INSTANCED_STEREO_CONFIG_V1
17195{
17196 NV_LMS_CUSTOM_CONFIG_V1 sLeftConfig;
17197 NV_LMS_CUSTOM_CONFIG_V1 sRightConfig;
17198} NV_LMS_INSTANCED_STEREO_CONFIG_V1;
17199
17200typedef NV_LMS_INSTANCED_STEREO_CONFIG_V1 NV_LMS_INSTANCED_STEREO_CONFIG;
17201
17202typedef enum _NV_SMP_ASSIST_EYE_INDEX
17203{
17204 NV_SMP_ASSIST_EYE_INDEX_MONO = 0, // Non-stereo rendering
17205 NV_SMP_ASSIST_EYE_INDEX_LEFT_EYE = 1, // Stereo - Rendering left eye
17206 NV_SMP_ASSIST_EYE_INDEX_RIGHT_EYE = 2, // Stereo - Rendering right eye
17207 NV_SMP_ASSIST_EYE_INDEX_INSTANCED_STEREO = 3, // Stereo - Rendering both eyes
17208} NV_SMP_ASSIST_EYE_INDEX;
17209
17210#define NV_SMP_ASSIST_MINIMAL_LEVEL_NUM_EYE_INDICES 4
17211
17212typedef struct _NV_CUSTOM_RECTS_V1
17213{
17214 NvU32 numViewports[NV_SMP_ASSIST_MINIMAL_LEVEL_NUM_EYE_INDICES];
17215 D3D11_VIEWPORT *pViewports[NV_SMP_ASSIST_MINIMAL_LEVEL_NUM_EYE_INDICES];
17216 D3D11_RECT *pScissors[NV_SMP_ASSIST_MINIMAL_LEVEL_NUM_EYE_INDICES];
17217} NV_CUSTOM_RECTS_V1;
17218
17219typedef NV_CUSTOM_RECTS_V1 NV_CUSTOM_RECTS;
17220
17221typedef struct _NV_SMP_ASSIST_ENABLE_PARAMS_V1
17222{
17223 NvU32 version;
17224 NV_SMP_ASSIST_EYE_INDEX eEyeIndex;
17225} NV_SMP_ASSIST_ENABLE_PARAMS_V1;
17226
17227typedef NV_SMP_ASSIST_ENABLE_PARAMS_V1 NV_SMP_ASSIST_ENABLE_PARAMS;
17228#define NV_SMP_ASSIST_ENABLE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_ENABLE_PARAMS_V1, 1)
17229#define NV_SMP_ASSIST_ENABLE_PARAMS_VER NV_SMP_ASSIST_ENABLE_PARAMS_VER1
17230
17231typedef struct _NV_SMP_ASSIST_DISABLE_PARAMS_V1
17232{
17233 NvU32 version;
17234 NvU32 Reserved;
17235} NV_SMP_ASSIST_DISABLE_PARAMS_V1;
17236
17237typedef NV_SMP_ASSIST_DISABLE_PARAMS_V1 NV_SMP_ASSIST_DISABLE_PARAMS;
17238#define NV_SMP_ASSIST_DISABLE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_DISABLE_PARAMS_V1, 1)
17239#define NV_SMP_ASSIST_DISABLE_PARAMS_VER NV_SMP_ASSIST_DISABLE_PARAMS_VER1
17240
17241// FastGS constant buffer data returned by the GetConstants API.
17242// Refer VRWorks SDK's multiprojection_dx app (struct FastGSCBData)
17243typedef struct _NV_SMP_ASSIST_FASTGSCBDATA_V1
17244{
17245 float NDCSplitsX[2];
17246 float NDCSplitsY[2];
17247} NV_SMP_ASSIST_FASTGSCBDATA_V1;
17248
17249typedef NV_SMP_ASSIST_FASTGSCBDATA_V1 NV_SMP_ASSIST_FASTGSCBDATA;
17250
17251typedef struct _NV_SMP_ASSIST_FASTGSCBDATA_MRS_INSTANCED_STEREO_V1
17252{
17253 float NDCSplitsX[4];
17254 float NDCSplitsY[2];
17255} NV_SMP_ASSIST_FASTGSCBDATA_MRS_INSTANCED_STEREO_V1;
17256
17257typedef NV_SMP_ASSIST_FASTGSCBDATA_MRS_INSTANCED_STEREO_V1 NV_SMP_ASSIST_FASTGSCBDATA_MRS_INSTANCED_STEREO;
17258
17259// Constant buffer data to supply the UV-remapping helper functions
17260// Refer VRWorks SDK's multiprojection_dx app (struct RemapCBData)
17261typedef struct _NV_SMP_ASSIST_REMAPCBDATA_V1
17262{
17264 float ClipToWindowSplitsX[2];
17265 float ClipToWindowSplitsY[2];
17266 float ClipToWindowX[3][2]; // ClipToWindowX[i][0] is Scale and ClipToWindowX[i][1] is Bias
17267 float ClipToWindowY[3][2]; // ClipToWindowY[i][0] is Scale and ClipToWindowY[i][1] is Bias
17268 float ClipToWindowZ[2]; // ClipToWindowZ[0] is Scale and ClipToWindowZ[1] is Bias
17269
17270 float WindowToClipSplitsX[2];
17271 float WindowToClipSplitsY[2];
17272 float WindowToClipX[3][2]; // WindowToClipX[i][0] is Scale and WindowToClipX[i][1] is Bias
17273 float WindowToClipY[3][2]; // WindowToClipY[i][0] is Scale and WindowToClipY[i][1] is Bias
17274 float WindowToClipZ[2]; // WindowToClipZ[0] is Scale and WindowToClipZ[1] is Bias
17275
17276 float BoundingRectOriginX;
17277 float BoundingRectOriginY;
17278 float BoundingRectSizeWidth;
17279 float BoundingRectSizeHeight;
17280 float BoundingRectSizeInvWidth;
17281 float BoundingRectSizeInvHeight;
17282
17283 float Padding[2];
17284}NV_SMP_ASSIST_REMAPCBDATA_V1;
17285
17286typedef NV_SMP_ASSIST_REMAPCBDATA_V1 NV_SMP_ASSIST_REMAPCBDATA;
17287
17290
17291typedef struct _NV_SMP_ASSIST_GET_CONSTANTS_V3
17292{
17293 NvU32 version;
17294 NV_SMP_ASSIST_EYE_INDEX eEyeIndex;
17295 NvU32 numViewports;
17296 D3D11_VIEWPORT *pViewports;
17297 D3D11_RECT *pScissors;
17298
17299 NV_SMP_ASSIST_TYPE eSMPAssistType;
17300 NV_SMP_ASSIST_LEVEL eSMPAssistLevel;
17301
17302 union
17303 {
17304 NV_MRS_CUSTOM_CONFIG_V1 sMRSConfig;
17305 NV_LMS_CUSTOM_CONFIG_V1 sLMSConfig;
17306 };
17307
17308 float projectionSizeWidth;
17309 float projectionSizeHeight;
17310
17311 NV_SMP_ASSIST_FASTGSCBDATA_V1 *pFastGSCBData;
17312 NV_SMP_ASSIST_REMAPCBDATA_V1 *pRemapCBData;
17313
17314 D3D11_VIEWPORT boundingViewport;
17315 D3D11_RECT boundingScissor;
17316
17317 union
17318 {
17319 NV_MRS_INSTANCED_STEREO_CONFIG_V1 sMRS_ISConfig;
17320 NV_LMS_INSTANCED_STEREO_CONFIG_V1 sLMS_ISConfig;
17321 };
17322
17323 NV_SMP_ASSIST_FASTGSCBDATA_MRS_INSTANCED_STEREO_V1 *pFastGSCBDataMRS_IS;
17324} NV_SMP_ASSIST_GET_CONSTANTS_V3;
17325
17326#define NV_SMP_ASSIST_GET_CONSTANTS_VER3 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_GET_CONSTANTS_V3, 3)
17327typedef NV_SMP_ASSIST_GET_CONSTANTS_V3 NV_SMP_ASSIST_GET_CONSTANTS;
17328#define NV_SMP_ASSIST_GET_CONSTANTS_VER NV_SMP_ASSIST_GET_CONSTANTS_VER3
17329
17332
17333typedef struct _NV_SMP_ASSIST_SETUP_PARAMS_V1
17334{
17335 NvU32 version;
17336 union
17337 {
17338 NV_MRS_CONFIG eMRSConfig;
17339 NV_LMS_CONFIG eLMSConfig;
17340 NV_MRS_CUSTOM_CONFIG_V1 sMRSCustomConfig;
17341 NV_LMS_CUSTOM_CONFIG_V1 sLMSCustomConfig;
17342 NV_CUSTOM_RECTS_V1 sCustomRects;
17343 };
17344
17345 float resolutionScale;
17346 D3D11_VIEWPORT boundingBox;
17347 float vpOffsets[2];
17349} NV_SMP_ASSIST_SETUP_PARAMS_V1;
17350
17351typedef NV_SMP_ASSIST_SETUP_PARAMS_V1 NV_SMP_ASSIST_SETUP_PARAMS;
17352#define NV_SMP_ASSIST_SETUP_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_SETUP_PARAMS_V1, 1)
17353#define NV_SMP_ASSIST_SETUP_PARAMS_VER NV_SMP_ASSIST_SETUP_PARAMS_VER1
17354
17355typedef struct _NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_V1
17356{
17357 NvU32 version;
17358 NV_SMP_ASSIST_TYPE eSMPAssistType; // Patch instanced stereo shaders (created with packed eye index) with this SMPAssistType (NV_SMP_ASSIST_LMS only)
17359 float leftCoeffs[4]; // Left eye: outpos.x = dotproduct(outputpos, leftCoeffs) + leftConst
17360 float leftConst;
17361 float rightCoeffs[4]; // Right eye: outpos.x = dotproduct(outputpos, rightCoeffs) + rightConst
17362 float rightConst;
17363} NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_V1;
17364
17365typedef NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_V1 NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS;
17366#define NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_V1, 1)
17367#define NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_VER NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS_VER1
17368
17371
17372DECLARE_INTERFACE(ID3DNvSMPAssist_V1)
17373{
17375 // Disable SMP Assist for further Draw calls
17376 STDMETHOD_(NvAPI_Status,Disable)(THIS_ __in IUnknown *pDevContext, __in const NV_SMP_ASSIST_DISABLE_PARAMS *psSMPAssistDisableParams) PURE;
17377
17378 // Enable SMP Assist for further Draw calls. App has to provide the type of rendering done in upcoming Draw calls - Mono/Left eye/Right eye/Instanced Stereo
17379 STDMETHOD_(NvAPI_Status,Enable)(THIS_ __in IUnknown *pDevContext, __in const NV_SMP_ASSIST_ENABLE_PARAMS *psSMPAssistEnableParams) PURE;
17380
17381 // Get the constants used by the drivers
17382 STDMETHOD_(NvAPI_Status,GetConstants)(THIS_ __inout NV_SMP_ASSIST_GET_CONSTANTS *psSMPAssistGetConstants) PURE;
17383
17384 // Setup the projections (rects, constant buffer data etc.)
17385 STDMETHOD_(NvAPI_Status,SetupProjections)(THIS_ __in IUnknown *pDevice, __in const NV_SMP_ASSIST_SETUP_PARAMS *psSMPAssistSetupParams) PURE;
17386
17387 // Update instanced stereo specific data
17388 STDMETHOD_(NvAPI_Status,UpdateInstancedStereoData)(THIS_ __in IUnknown *pDevice, __in const NV_SMP_ASSIST_UPDATE_INSTANCEDSTEREO_DATA_PARAMS *psSMPAssistInstancedStereoParams) PURE;
17390};
17391
17392typedef ID3DNvSMPAssist_V1 ID3DNvSMPAssist;
17393#define ID3DNVSMPASSIST_VER1 MAKE_NVAPI_VERSION(ID3DNvSMPAssist_V1, 1)
17394#define ID3DNVSMPASSIST_VER ID3DNVSMPASSIST_VER1
17395
17398
17399typedef struct _NV_SMP_ASSIST_INITIALIZE_PARAMS_V1
17400{
17401 NvU32 version;
17402 NV_SMP_ASSIST_TYPE eSMPAssistType;
17403 NV_SMP_ASSIST_LEVEL eSMPAssistLevel;
17404 NvU32 flags;
17405
17406 ID3DNvSMPAssist **ppD3DNvSMPAssist;
17407
17408} NV_SMP_ASSIST_INITIALIZE_PARAMS_V1;
17409
17410#define NV_SMP_ASSIST_INITIALIZE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SMP_ASSIST_INITIALIZE_PARAMS_V1, 1)
17411#ifndef NV_SMP_ASSIST_INITIALIZE_PARAMS_VER
17412typedef NV_SMP_ASSIST_INITIALIZE_PARAMS_V1 NV_SMP_ASSIST_INITIALIZE_PARAMS;
17413#define NV_SMP_ASSIST_INITIALIZE_PARAMS_VER NV_SMP_ASSIST_INITIALIZE_PARAMS_VER1
17414#endif
17415
17417//
17418// FUNCTION NAME: NvAPI_D3D_InitializeSMPAssist
17419//
17433NVAPI_INTERFACE NvAPI_D3D_InitializeSMPAssist(__in IUnknown *pDevice, __inout NV_SMP_ASSIST_INITIALIZE_PARAMS *pSMPAssistInitParams);
17434
17435#endif //defined(__cplusplus) && defined(__d3d11_h__)
17436
17439#if defined (__cplusplus) && defined(__d3d11_h__)
17441typedef struct _NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_V1
17442{
17443 NvU32 version;
17444 NV_SMP_ASSIST_TYPE eSMPAssistType;
17445 NV_SMP_ASSIST_LEVEL eSMPAssistLevel;
17446 NvBool bSMPAssistSupported;
17447} NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_V1;
17448
17449typedef NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_V1 NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS;
17450#define NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_V1, 1)
17451#define NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_VER NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS_VER1
17452
17457//
17458// FUNCTION NAME: NvAPI_D3D_QuerySMPAssistSupport
17459//
17473NVAPI_INTERFACE NvAPI_D3D_QuerySMPAssistSupport(__in IUnknown *pDev, __inout NV_QUERY_SMP_ASSIST_SUPPORT_PARAMS *pQuerySMPAssistSupportParams);
17474
17475#endif //defined(__cplusplus) && defined(__d3d11_h__)
17476
17477
17478
17491
17493#define NV_GET_SLEEP_STATUS_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_GET_SLEEP_STATUS_PARAMS_V1, 1)
17494#define NV_GET_SLEEP_STATUS_PARAMS_VER NV_GET_SLEEP_STATUS_PARAMS_VER1
17495
17496#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17498//
17499// FUNCTION NAME: NvAPI_D3D_GetSleepStatus
17500//
17522NVAPI_INTERFACE NvAPI_D3D_GetSleepStatus(__in IUnknown *pDev, __in NV_GET_SLEEP_STATUS_PARAMS *pGetSleepStatusParams);
17523#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17524
17538
17540#define NV_SET_SLEEP_MODE_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SET_SLEEP_MODE_PARAMS_V1, 1)
17541#define NV_SET_SLEEP_MODE_PARAMS_VER NV_SET_SLEEP_MODE_PARAMS_VER1
17542
17543#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17545//
17546// FUNCTION NAME: NvAPI_D3D_SetSleepMode
17547//
17578NVAPI_INTERFACE NvAPI_D3D_SetSleepMode(__in IUnknown *pDev, __in NV_SET_SLEEP_MODE_PARAMS *pSetSleepModeParams);
17579#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17580
17581#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17583//
17584// FUNCTION NAME: NvAPI_D3D_Sleep
17585//
17609NVAPI_INTERFACE NvAPI_D3D_Sleep(__in IUnknown *pDev);
17610#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17611
17627
17629#define NV_SET_REFLEX_SYNC_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_SET_REFLEX_SYNC_PARAMS_V1, 1)
17630#define NV_SET_REFLEX_SYNC_PARAMS_VER NV_SET_REFLEX_SYNC_PARAMS_VER1
17631
17632#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17634//
17635// FUNCTION NAME: NvAPI_D3D_SetReflexSync
17636//
17650NVAPI_INTERFACE NvAPI_D3D_SetReflexSync(__in IUnknown *pDev, __in NV_SET_REFLEX_SYNC_PARAMS *pSetReflexSyncParams);
17651#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17652
17657
17659{
17660 NvU32 version;
17662 NvU64 frameID;
17663 NvU64 inputSampleTime;
17664 NvU64 simStartTime;
17665 NvU64 simEndTime;
17666 NvU64 renderSubmitStartTime;
17667 NvU64 renderSubmitEndTime;
17668 NvU64 presentStartTime;
17669 NvU64 presentEndTime;
17670 NvU64 driverStartTime;
17671 NvU64 driverEndTime;
17672 NvU64 osRenderQueueStartTime;
17673 NvU64 osRenderQueueEndTime;
17674 NvU64 gpuRenderStartTime;
17675 NvU64 gpuRenderEndTime;
17678 NvU8 rsvd[120];
17679 } frameReport[64];
17680 NvU8 rsvd[32];
17682
17684#define NV_LATENCY_RESULT_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_LATENCY_RESULT_PARAMS_V1, 1)
17685#define NV_LATENCY_RESULT_PARAMS_VER NV_LATENCY_RESULT_PARAMS_VER1
17686
17687#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17689//
17690// FUNCTION NAME: NvAPI_D3D_GetLatency
17691//
17712NVAPI_INTERFACE NvAPI_D3D_GetLatency(__in IUnknown *pDev, __out NV_LATENCY_RESULT_PARAMS *pGetLatencyParams);
17713#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17714
17719typedef enum
17720{
17721 SIMULATION_START = 0,
17722 SIMULATION_END = 1,
17723 RENDERSUBMIT_START = 2,
17724 RENDERSUBMIT_END = 3,
17725 PRESENT_START = 4,
17726 PRESENT_END = 5,
17727 INPUT_SAMPLE = 6,
17728 TRIGGER_FLASH = 7,
17729 PC_LATENCY_PING = 8,
17730 OUT_OF_BAND_RENDERSUBMIT_START = 9,
17731 OUT_OF_BAND_RENDERSUBMIT_END = 10,
17732 OUT_OF_BAND_PRESENT_START = 11,
17733 OUT_OF_BAND_PRESENT_END = 12,
17734} NV_LATENCY_MARKER_TYPE;
17735
17741{
17742 NvU32 version;
17743 NvU64 frameID;
17744 NV_LATENCY_MARKER_TYPE markerType;
17745 NvU8 rsvd[64];
17747
17749#define NV_LATENCY_MARKER_PARAMS_VER1 MAKE_NVAPI_VERSION(NV_LATENCY_MARKER_PARAMS_V1, 1)
17750#define NV_LATENCY_MARKER_PARAMS_VER NV_LATENCY_MARKER_PARAMS_VER1
17751
17752#if defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17754//
17755// FUNCTION NAME: NvAPI_D3D_SetLatencyMarker
17756//
17782NVAPI_INTERFACE NvAPI_D3D_SetLatencyMarker(__in IUnknown *pDev, __in NV_LATENCY_MARKER_PARAMS* pSetLatencyMarkerParams);
17783#endif //defined(__cplusplus) && (defined(_D3D9_H_) || defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__) || defined(__d3d12_h__))
17784
17789#define NV_ASYNC_FRAME_MARKER_PARAMS_VER1 NV_LATENCY_MARKER_PARAMS_VER1
17790#define NV_ASYNC_FRAME_MARKER_PARAMS_VER NV_LATENCY_MARKER_PARAMS_VER1
17791
17792#if defined(__cplusplus) && (defined(__d3d12_h__))
17794//
17795// FUNCTION NAME: NvAPI_D3D12_SetAsyncFrameMarker
17796//
17810NVAPI_INTERFACE NvAPI_D3D12_SetAsyncFrameMarker(__in ID3D12CommandQueue *pCommandQueue, __in NV_ASYNC_FRAME_MARKER_PARAMS* pSetAsyncFrameMarkerParams);
17811#endif //defined(__cplusplus) && (defined(__d3d12_h__))
17812
17817typedef enum
17818{
17819 OUT_OF_BAND_RENDER = 0,
17820 OUT_OF_BAND_PRESENT = 1,
17821} NV_OUT_OF_BAND_CQ_TYPE;
17822
17823#if defined(__cplusplus) && defined(__d3d12_h__)
17825//
17826// FUNCTION NAME: NvAPI_D3D12_NotifyOutOfBandCommandQueue
17827//
17842NVAPI_INTERFACE NvAPI_D3D12_NotifyOutOfBandCommandQueue(__in ID3D12CommandQueue *pCommandQueue, __in NV_OUT_OF_BAND_CQ_TYPE cqType);
17843#endif //defined(__cplusplus) && defined(__d3d12_h__))
17844
17845
17846#if defined (__cplusplus) && defined(__d3d12_h__)
17847
17848// Experimental API for internal use. DO NOT USE!
17851NVAPI_INTERFACE NvAPI_D3D12_CreateCubinComputeShader(__in ID3D12Device* pDevice,
17852 __in const void* pCubin,
17853 __in NvU32 size,
17854 __in NvU32 blockX,
17855 __in NvU32 blockY,
17856 __in NvU32 blockZ,
17857 __out NVDX_ObjectHandle* phShader);
17858
17859// Experimental API for internal use. DO NOT USE!
17862NVAPI_INTERFACE NvAPI_D3D12_CreateCubinComputeShaderEx(__in ID3D12Device* pDevice,
17863 __in const void* pCubin,
17864 __in NvU32 size,
17865 __in NvU32 blockX,
17866 __in NvU32 blockY,
17867 __in NvU32 blockZ,
17868 __in NvU32 dynSharedMemBytes,
17869 __in const char* pShaderName,
17870 __out NVDX_ObjectHandle* phShader);
17871
17872// Experimental API for internal use. DO NOT USE!
17875NVAPI_INTERFACE NvAPI_D3D12_CreateCubinComputeShaderWithName(__in ID3D12Device* pDevice,
17876 __in const void* pCubin,
17877 __in NvU32 size,
17878 __in NvU32 blockX,
17879 __in NvU32 blockY,
17880 __in NvU32 blockZ,
17881 __in const char* pShaderName,
17882 __out NVDX_ObjectHandle* phShader);
17883
17884// Experimental API for internal use. DO NOT USE!
17887NVAPI_INTERFACE NvAPI_D3D12_LaunchCubinShader(__in ID3D12GraphicsCommandList* pCommandList,
17888 __in NVDX_ObjectHandle hShader,
17889 __in NvU32 gridX,
17890 __in NvU32 gridY,
17891 __in NvU32 gridZ,
17892 __in const void* pParams,
17893 __in NvU32 paramSize);
17894
17895// Experimental API for internal use. DO NOT USE!
17898NVAPI_INTERFACE NvAPI_D3D12_DestroyCubinComputeShader(__in ID3D12Device* pDevice,
17899 __in NVDX_ObjectHandle hShader);
17900
17901// Experimental API for internal use. DO NOT USE!
17904NVAPI_INTERFACE NvAPI_D3D12_GetCudaTextureObject(__in ID3D12Device* pDevice,
17905 __in D3D12_CPU_DESCRIPTOR_HANDLE texDesc,
17906 __in D3D12_CPU_DESCRIPTOR_HANDLE smpDesc,
17907 __out NvU32* pTextureHandle);
17908
17909// Experimental API for internal use. DO NOT USE!
17912NVAPI_INTERFACE NvAPI_D3D12_GetCudaSurfaceObject(__in ID3D12Device* pDevice,
17913 __in D3D12_CPU_DESCRIPTOR_HANDLE uavDesc,
17914 __out NvU32* pSurfaceHandle);
17915
17916// Experimental API for internal use. DO NOT USE!
17919NVAPI_INTERFACE NvAPI_D3D12_IsFatbinPTXSupported(__in ID3D12Device *pDevice,
17920 __out bool *pSupported);
17921
17922// Experimental API for internal use. DO NOT USE!
17925NVAPI_INTERFACE NvAPI_D3D12_CreateCuModule(__in ID3D12Device* pDevice,
17926 __in const void* pBlob,
17927 __in NvU32 size,
17928 __out NVDX_ObjectHandle* phModule);
17929
17930// Experimental API for internal use. DO NOT USE!
17933NVAPI_INTERFACE NvAPI_D3D12_EnumFunctionsInModule(__in ID3D12Device* pDevice,
17934 __in NVDX_ObjectHandle hModule,
17935 __inout NvU32* pArraySize,
17936 __out const char** const pFunctionNames);
17937
17938// Experimental API for internal use. DO NOT USE!
17941NVAPI_INTERFACE NvAPI_D3D12_CreateCuFunction(__in ID3D12Device* pDevice,
17942 __in NVDX_ObjectHandle hModule,
17943 __in const char* pName,
17944 __out NVDX_ObjectHandle* phFunction);
17945
17946// Experimental API for internal use. DO NOT USE!
17949
17950typedef struct _NVAPI_DIM3
17951{
17952 NvU32 x;
17953 NvU32 y;
17954 NvU32 z;
17955} NVAPI_DIM3;
17956
17957typedef struct _NVAPI_CU_KERNEL_LAUNCH_PARAMS
17958{
17959 NVDX_ObjectHandle hFunction;
17960 NVAPI_DIM3 gridDim;
17961 NVAPI_DIM3 blockDim;
17962 NvU32 dynSharedMemBytes;
17963 void const * pParams;
17964 NvU32 paramSize;
17965} NVAPI_CU_KERNEL_LAUNCH_PARAMS;
17966
17967NVAPI_INTERFACE NvAPI_D3D12_LaunchCuKernelChain(__in ID3D12GraphicsCommandList* pCommandList,
17968 __in const NVAPI_CU_KERNEL_LAUNCH_PARAMS* pKernels,
17969 __in NvU32 numKernels);
17970
17971// Experimental API for internal use. DO NOT USE!
17974
17975typedef struct _NVAPI_CU_KERNEL_LAUNCH_PARAMS_EX
17976{
17977 NVDX_ObjectHandle hFunction;
17978 NVAPI_DIM3 gridDim;
17979 NVAPI_DIM3 blockDim;
17980 NvU32 dynSharedMemBytes;
17981
17982 // either pParams/paramsSize is used or kernelParams is used
17983 void const * pParams;
17984 NvU32 paramSize;
17985 void **kernelParams;
17986} NVAPI_CU_KERNEL_LAUNCH_PARAMS_EX;
17987
17988NVAPI_INTERFACE NvAPI_D3D12_LaunchCuKernelChainEx(__in ID3D12GraphicsCommandList* pCommandList,
17989 __in const NVAPI_CU_KERNEL_LAUNCH_PARAMS_EX* pKernels,
17990 __in NvU32 numKernels);
17991
17992
17993// Experimental API for internal use. DO NOT USE!
17996NVAPI_INTERFACE NvAPI_D3D12_DestroyCuModule(__in ID3D12Device* pDevice,
17997 __in NVDX_ObjectHandle hModule);
17998
17999// Experimental API for internal use. DO NOT USE!
18002NVAPI_INTERFACE NvAPI_D3D12_DestroyCuFunction(__in ID3D12Device* pDevice,
18003 __in NVDX_ObjectHandle hFunction);
18004#endif //if defined (__cplusplus) && defined(__d3d12_h__)
18005
18006
18007#if defined (__cplusplus) && defined(__d3d11_h__)
18008
18009// Experimental API for internal use. DO NOT USE!
18012NVAPI_INTERFACE NvAPI_D3D11_CreateCubinComputeShader(__in ID3D11Device* pDevice,
18013 __in const void* pCubin,
18014 __in NvU32 size,
18015 __in NvU32 blockX,
18016 __in NvU32 blockY,
18017 __in NvU32 blockZ,
18018 __out NVDX_ObjectHandle* phShader);
18019
18020// Experimental API for internal use. DO NOT USE!
18023NVAPI_INTERFACE NvAPI_D3D11_CreateCubinComputeShaderEx(__in ID3D11Device* pDevice,
18024 __in const void* pCubin,
18025 __in NvU32 size,
18026 __in NvU32 blockX,
18027 __in NvU32 blockY,
18028 __in NvU32 blockZ,
18029 __in NvU32 dynSharedMemBytes,
18030 __in const char* pShaderName,
18031 __out NVDX_ObjectHandle* phShader);
18032
18033// Experimental API for internal use. DO NOT USE!
18036NVAPI_INTERFACE NvAPI_D3D11_CreateCubinComputeShaderWithName(__in ID3D11Device* pDevice,
18037 __in const void* pCubin,
18038 __in NvU32 size,
18039 __in NvU32 blockX,
18040 __in NvU32 blockY,
18041 __in NvU32 blockZ,
18042 __in const char* pShaderName,
18043 __out NVDX_ObjectHandle* phShader);
18044
18045
18046// Experimental API for internal use. DO NOT USE!
18049NVAPI_INTERFACE NvAPI_D3D11_LaunchCubinShader(__in ID3D11DeviceContext *pDeviceContext,
18050 __in NVDX_ObjectHandle hShader,
18051 __in NvU32 gridX,
18052 __in NvU32 gridY,
18053 __in NvU32 gridZ,
18054 __in const void* pParams,
18055 __in NvU32 paramSize,
18056 __in const NVDX_ObjectHandle* pReadResources,
18057 __in NvU32 numReadResources,
18058 __in const NVDX_ObjectHandle* pWriteResources,
18059 __in NvU32 numWriteResources);
18060
18061// Experimental API for internal use. DO NOT USE!
18064NVAPI_INTERFACE NvAPI_D3D11_DestroyCubinComputeShader(__in ID3D11Device* pDevice,
18065 __in NVDX_ObjectHandle hShader);
18066
18067// Experimental API for internal use. DO NOT USE!
18070NVAPI_INTERFACE NvAPI_D3D11_IsFatbinPTXSupported(__in ID3D11Device *pDevice,
18071 __out bool *pSupported);
18072
18073// Experimental API for internal use. DO NOT USE!
18076NVAPI_INTERFACE NvAPI_D3D11_CreateUnorderedAccessView(__in ID3D11Device* pDevice,
18077 __in ID3D11Resource* pResource,
18078 __in const D3D11_UNORDERED_ACCESS_VIEW_DESC* pDesc,
18079 __out ID3D11UnorderedAccessView** ppUAV,
18080 __out NvU32* pDriverHandle);
18081
18082// Experimental API for internal use. DO NOT USE!
18085NVAPI_INTERFACE NvAPI_D3D11_CreateShaderResourceView(__in ID3D11Device* pDevice,
18086 __in ID3D11Resource* pResource,
18087 __in const D3D11_SHADER_RESOURCE_VIEW_DESC* pDesc,
18088 __out ID3D11ShaderResourceView** ppSRV,
18089 __out NvU32* pDriverHandle);
18090
18091// Experimental API for internal use. DO NOT USE!
18094NVAPI_INTERFACE NvAPI_D3D11_CreateSamplerState(__in ID3D11Device* pDevice,
18095 __in const D3D11_SAMPLER_DESC* pSamplerDesc,
18096 __out ID3D11SamplerState** ppSamplerState,
18097 __out NvU32* pDriverHandle);
18098
18099// Experimental API for internal use. DO NOT USE!
18102NVAPI_INTERFACE NvAPI_D3D11_GetCudaTextureObject(__in ID3D11Device* pDevice,
18103 __in NvU32 srvDriverHandle,
18104 __in NvU32 samplerDriverHandle,
18105 __out NvU32* pCudaTextureHandle);
18106
18107// Experimental API for internal use. DO NOT USE!
18110NVAPI_INTERFACE NvAPI_D3D11_GetResourceGPUVirtualAddress(__in ID3D11Device* pDevice,
18111 __in const NVDX_ObjectHandle hResource,
18112 __out NvU64* pGpuVA);
18113#endif //defined(__cplusplus) && defined(__d3d11_h__)
18114
18115
18116#if defined(__cplusplus) && defined(__d3d12_h__)
18121typedef enum _NVAPI_D3D12_RAYTRACING_THREAD_REORDERING_CAPS
18122{
18123 NVAPI_D3D12_RAYTRACING_THREAD_REORDERING_CAP_NONE = 0x0,
18124 NVAPI_D3D12_RAYTRACING_THREAD_REORDERING_CAP_STANDARD = NV_BIT(0)
18125} NVAPI_D3D12_RAYTRACING_THREAD_REORDERING_CAPS;
18126
18131typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_CAPS
18132{
18133 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_CAP_NONE = 0x0,
18135 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_CAP_STANDARD = NV_BIT(0)
18136} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_CAPS;
18137
18142typedef enum _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_CAPS
18143{
18144 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_CAP_NONE = 0x0,
18146 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_CAP_STANDARD = NV_BIT(0)
18147} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_CAPS;
18148
18152typedef enum _NVAPI_D3D12_RAYTRACING_CAPS_TYPE
18153{
18154 NVAPI_D3D12_RAYTRACING_CAPS_TYPE_THREAD_REORDERING = 0,
18155 NVAPI_D3D12_RAYTRACING_CAPS_TYPE_OPACITY_MICROMAP = 1,
18156 NVAPI_D3D12_RAYTRACING_CAPS_TYPE_DISPLACEMENT_MICROMAP = 2,
18157 NVAPI_D3D12_RAYTRACING_CAPS_TYPE_INVALID = -1
18158} NVAPI_D3D12_RAYTRACING_CAPS_TYPE;
18159
18161//
18162// FUNCTION NAME: NvAPI_D3D12_GetRaytracingCaps
18163//
18185NVAPI_INTERFACE NvAPI_D3D12_GetRaytracingCaps(
18186 __in ID3D12Device* pDevice,
18187 __in NVAPI_D3D12_RAYTRACING_CAPS_TYPE type,
18188 __out void* pData,
18189 __in size_t dataSize);
18190#endif // defined(__cplusplus) && defined(__d3d12_h__)
18191
18192#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
18193
18197typedef enum _NVAPI_D3D12_RAYTRACING_VALIDATION_FLAGS
18198{
18199 NVAPI_D3D12_RAYTRACING_VALIDATION_FLAG_NONE = 0x0,
18200} NVAPI_D3D12_RAYTRACING_VALIDATION_FLAGS;
18201
18203//
18204// FUNCTION NAME: NvAPI_D3D12_EnableRaytracingValidation
18205//
18229NVAPI_INTERFACE NvAPI_D3D12_EnableRaytracingValidation(
18230 __in ID3D12Device5* pDevice,
18231 __in NVAPI_D3D12_RAYTRACING_VALIDATION_FLAGS flags);
18232
18233
18234
18238typedef enum _NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_SEVERITY
18239{
18240 NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_SEVERITY_ERROR = 0x0,
18241 NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_SEVERITY_WARNING = 0x1
18242} NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_SEVERITY;
18243
18252typedef void(__stdcall *NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_CALLBACK)(void* pUserData, NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_SEVERITY severity, const char* messageCode, const char* message, const char* messageDetails);
18253
18255//
18256// FUNCTION NAME: NvAPI_D3D12_RegisterRaytracingValidationMessageCallback
18257//
18280NVAPI_INTERFACE NvAPI_D3D12_RegisterRaytracingValidationMessageCallback(
18281 __in ID3D12Device5* pDevice,
18282 __in NVAPI_D3D12_RAYTRACING_VALIDATION_MESSAGE_CALLBACK pfnMessageCallback,
18283 __in_opt void* pUserData,
18284 __out void** pHandle);
18285
18286
18287
18289//
18290// FUNCTION NAME: NvAPI_D3D12_UnregisterRaytracingValidationMessageCallback
18291//
18311NVAPI_INTERFACE NvAPI_D3D12_UnregisterRaytracingValidationMessageCallback(
18312 __in ID3D12Device5* pDevice,
18313 __in void* handle);
18314
18315
18316
18318//
18319// FUNCTION NAME: NvAPI_D3D12_FlushRaytracingValidationMessages
18320//
18340NVAPI_INTERFACE NvAPI_D3D12_FlushRaytracingValidationMessages(
18341 __in ID3D12Device5* pDevice);
18342
18343#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
18344
18347#if defined(__cplusplus) && defined(__d3d12_h__) && (defined(__ID3D12Device5_INTERFACE_DEFINED__) || defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__))
18348
18349// Types used by both device and command list functions.
18350
18354typedef enum _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAGS
18355{
18356 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAG_NONE = 0x0,
18357 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAG_PREFER_FAST_TRACE = NV_BIT(0),
18359 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAG_PREFER_FAST_BUILD = NV_BIT(1)
18361} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAGS;
18362
18369typedef enum _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT
18370{
18371 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT_DC1_64_TRIS_64_BYTES = 0x1,
18372 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT_DC1_256_TRIS_128_BYTES = 0x2,
18373 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT_DC1_1024_TRIS_128_BYTES = 0x3,
18374
18375} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT;
18376
18381typedef struct _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_USAGE_COUNT
18382{
18383 NvU32 count;
18385 NvU32 subdivisionLevel;
18387 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_FORMAT format;
18388} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_USAGE_COUNT;
18389
18393typedef struct _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_DESC
18394{
18395 NvU32 byteOffset;
18396 NvU16 subdivisionLevel;
18398 NvU16 format;
18399} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_DESC;
18400
18405typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_INPUTS
18406{
18407 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BUILD_FLAGS flags;
18408 NvU32 numDMMUsageCounts;
18409 const NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_USAGE_COUNT* pDMMUsageCounts;
18410 D3D12_GPU_VIRTUAL_ADDRESS inputBuffer;
18412 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE perDMMDescs;
18413} NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_INPUTS;
18414
18415#endif // defined(__cplusplus) && defined(__d3d12_h__) && (defined(__ID3D12Device5_INTERFACE_DEFINED__) || defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__))
18416
18417#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18418
18422typedef struct _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO
18423{
18424 NvU64 resultDataMaxSizeInBytes;
18425 NvU64 scratchDataSizeInBytes;
18426} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO;
18427
18431typedef struct _NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1
18432{
18433 NvU32 version;
18434 const NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_INPUTS* pDesc;
18435 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO* pInfo;
18436} NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1;
18437#define NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1, 1)
18438typedef NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1 NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS;
18439#define NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER1
18440
18442//
18443// FUNCTION NAME: NvAPI_D3D12_GetRaytracingDisplacementMicromapArrayPrebuildInfo
18444//
18463NVAPI_INTERFACE NvAPI_D3D12_GetRaytracingDisplacementMicromapArrayPrebuildInfo(
18464 __in ID3D12Device5* pDevice,
18465 __inout NVAPI_GET_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS* pParams);
18466
18467#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18468
18471#if defined(__cplusplus) && defined(__d3d12_h__) && (defined(__ID3D12Device5_INTERFACE_DEFINED__) || defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__))
18472
18473// Types used by both device and command list functions.
18474
18478typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAGS
18479{
18480 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAG_NONE = 0x0,
18481 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAG_PREFER_FAST_TRACE = NV_BIT(0),
18483 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAG_PREFER_FAST_BUILD = NV_BIT(1)
18485} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAGS;
18486
18493typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_FORMAT
18494{
18495 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_FORMAT_OC1_2_STATE = 0x1,
18496 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_FORMAT_OC1_4_STATE = 0x2
18497} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_FORMAT;
18498
18503typedef struct _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_USAGE_COUNT
18504{
18505 NvU32 count;
18506 NvU32 subdivisionLevel;
18508 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_FORMAT format;
18509} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_USAGE_COUNT;
18510
18514typedef struct _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_DESC
18515{
18516 NvU32 byteOffset;
18517 NvU16 subdivisionLevel;
18519 NvU16 format;
18520} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_DESC;
18521
18526typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_INPUTS
18527{
18528 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BUILD_FLAGS flags;
18529 NvU32 numOMMUsageCounts;
18530 const NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_USAGE_COUNT* pOMMUsageCounts;
18531 D3D12_GPU_VIRTUAL_ADDRESS inputBuffer;
18533 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE perOMMDescs;
18534} NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_INPUTS;
18535
18536#endif // defined(__cplusplus) && defined(__d3d12_h__) && (defined(__ID3D12Device5_INTERFACE_DEFINED__) || defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__))
18537
18538#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18539
18543typedef struct _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO
18544{
18545 NvU64 resultDataMaxSizeInBytes;
18546 NvU64 scratchDataSizeInBytes;
18547} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO;
18548
18552typedef struct _NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1
18553{
18554 NvU32 version;
18555 const NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_INPUTS* pDesc;
18556 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO* pInfo;
18557} NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1;
18558#define NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1, 1)
18559typedef NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_V1 NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS;
18560#define NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS_VER1
18561
18563//
18564// FUNCTION NAME: NvAPI_D3D12_GetRaytracingOpacityMicromapArrayPrebuildInfo
18565//
18584NVAPI_INTERFACE NvAPI_D3D12_GetRaytracingOpacityMicromapArrayPrebuildInfo(
18585 __in ID3D12Device5* pDevice,
18586 __inout NVAPI_GET_RAYTRACING_OPACITY_MICROMAP_ARRAY_PREBUILD_INFO_PARAMS* pParams);
18587
18588#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18589
18590#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18591
18595typedef enum _NVAPI_D3D12_PIPELINE_CREATION_STATE_FLAGS
18596{
18597 NVAPI_D3D12_PIPELINE_CREATION_STATE_FLAGS_NONE = 0,
18598 NVAPI_D3D12_PIPELINE_CREATION_STATE_FLAGS_ENABLE_OMM_SUPPORT = NV_BIT(0),
18601 NVAPI_D3D12_PIPELINE_CREATION_STATE_FLAGS_ENABLE_DMM_SUPPORT = NV_BIT(1),
18604} NVAPI_D3D12_PIPELINE_CREATION_STATE_FLAGS;
18605
18609typedef struct _NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_V1
18610{
18611 NvU32 version;
18612 NvU32 flags;
18613} NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_V1;
18614#define NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_V1, 1)
18615typedef NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_V1 NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS;
18616#define NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_VER NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS_VER1
18617
18619//
18620// FUNCTION NAME: NvAPI_D3D12_SetCreatePipelineStateOptions
18621//
18635
18641NVAPI_INTERFACE NvAPI_D3D12_SetCreatePipelineStateOptions(
18642 __in ID3D12Device5* pDevice,
18643 __in const NVAPI_D3D12_SET_CREATE_PIPELINE_STATE_OPTIONS_PARAMS* pState);
18644
18645#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18646
18647#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18648
18652typedef enum _NVAPI_D3D12_SERIALIZED_DATA_TYPE_EX
18653{
18654 // D3D12_SERIALIZED_DATA_TYPE flags
18655 NVAPI_D3D12_SERIALIZED_DATA_RAYTRACING_ACCELERATION_STRUCTURE_EX = 0x0,
18658
18659 // NVAPI_D3D12_SERIALIZED_DATA_TYPE_EX specific flags
18660 NVAPI_D3D12_SERIALIZED_DATA_RAYTRACING_OPACITY_MICROMAP_ARRAY_EX = 0x1,
18662 NVAPI_D3D12_SERIALIZED_DATA_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_EX = 0x2,
18664
18665} NVAPI_D3D12_SERIALIZED_DATA_TYPE_EX;
18666
18670typedef struct _NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_V1
18671{
18672 NvU32 version;
18673 NVAPI_D3D12_SERIALIZED_DATA_TYPE_EX serializedDataType;
18674 const D3D12_SERIALIZED_DATA_DRIVER_MATCHING_IDENTIFIER* pIdentifierToCheck;
18676 D3D12_DRIVER_MATCHING_IDENTIFIER_STATUS checkStatus;
18677} NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_V1;
18678#define NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_V1, 1)
18679typedef NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_V1 NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS;
18680#define NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_VER NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS_VER1
18681
18683//
18684// FUNCTION NAME: NvAPI_D3D12_CheckDriverMatchingIdentifierEx
18685//
18701NVAPI_INTERFACE NvAPI_D3D12_CheckDriverMatchingIdentifierEx(
18702 __in ID3D12Device5* pDevice,
18703 __inout NVAPI_CHECK_DRIVER_MATCHING_IDENTIFIER_EX_PARAMS* pParams);
18704
18705#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18706
18707#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18708
18713typedef enum _NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAGS_EX
18714{
18715 // D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAGS flags
18716 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_NONE_EX = 0x0,
18717 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_UPDATE_EX = NV_BIT(0),
18718 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_COMPACTION_EX = NV_BIT(1),
18719 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_PREFER_FAST_TRACE_EX = NV_BIT(2),
18720 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_PREFER_FAST_BUILD_EX = NV_BIT(3),
18721 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_MINIMIZE_MEMORY_EX = NV_BIT(4),
18722 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_PERFORM_UPDATE_EX = NV_BIT(5),
18724
18725 // NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAGS_EX specific flags
18726 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_OMM_UPDATE_EX = NV_BIT(6),
18728 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_DISABLE_OMMS_EX = NV_BIT(7),
18730 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_OMM_OPACITY_STATES_UPDATE_EX = NV_BIT(8),
18732 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAG_ALLOW_DATA_ACCESS_EX = NV_BIT(9),
18733
18734} NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAGS_EX;
18735
18740typedef enum _NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_EX
18741{
18742 // D3D12_RAYTRACING_GEOMETRY_TYPE flags
18743 NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_TRIANGLES_EX = 0x0,
18744 NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_PROCEDURAL_PRIMITIVE_AABBS_EX = 0x1,
18745
18746 // NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_EX specific flags
18747 NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_OMM_TRIANGLES_EX = 0x2,
18749 NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_DMM_TRIANGLES_EX = 0x3,
18751
18752} NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_EX;
18753
18758typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX
18759{
18760 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX_FULLY_TRANSPARENT = -1,
18761 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX_FULLY_OPAQUE = -2,
18762 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX_FULLY_UNKNOWN_TRANSPARENT = -3,
18763 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX_FULLY_UNKNOWN_OPAQUE = -4
18764} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_SPECIAL_INDEX;
18765
18769typedef struct _NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_ATTACHMENT_DESC
18770{
18771 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE opacityMicromapIndexBuffer;
18774 DXGI_FORMAT opacityMicromapIndexFormat;
18775 NvU32 opacityMicromapBaseLocation;
18776 D3D12_GPU_VIRTUAL_ADDRESS opacityMicromapArray;
18778
18779 NvU32 numOMMUsageCounts;
18780 const NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_USAGE_COUNT* pOMMUsageCounts;
18781
18782} NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_ATTACHMENT_DESC;
18783
18788typedef enum _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_PRIMITIVE_FLAGS
18789{
18790 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_PRIMITIVE_FLAG_DECIMATE_01 = NV_BIT(0),
18791 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_PRIMITIVE_FLAG_DECIMATE_12 = NV_BIT(1),
18792 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_PRIMITIVE_FLAG_DECIMATE_20 = NV_BIT(2),
18793
18794} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_PRIMITIVE_FLAGS;
18795
18799typedef struct _NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_ATTACHMENT_DESC
18800{
18801 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE triangleMicromapIndexBuffer;
18803 DXGI_FORMAT triangleMicromapIndexFormat;
18804 NvU32 triangleMicromapBaseLocation;
18805
18806 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE trianglePrimitiveFlagsBuffer;
18807
18808 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE vertexBiasAndScaleBuffer;
18809 DXGI_FORMAT vertexBiasAndScaleFormat;
18810
18811 D3D12_GPU_VIRTUAL_ADDRESS_AND_STRIDE vertexDisplacementVectorBuffer;
18812 DXGI_FORMAT vertexDisplacementVectorFormat;
18813
18814 D3D12_GPU_VIRTUAL_ADDRESS displacementMicromapArray;
18816
18817 NvU32 numDMMUsageCounts;
18818 const NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_USAGE_COUNT* pDMMUsageCounts;
18819
18820} NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_ATTACHMENT_DESC;
18821
18825typedef struct _NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_TRIANGLES_DESC
18826{
18827 D3D12_RAYTRACING_GEOMETRY_TRIANGLES_DESC triangles;
18828 NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_ATTACHMENT_DESC dmmAttachment;
18829} NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_TRIANGLES_DESC;
18830
18834typedef struct _NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_TRIANGLES_DESC
18835{
18836 D3D12_RAYTRACING_GEOMETRY_TRIANGLES_DESC triangles;
18837 NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_ATTACHMENT_DESC ommAttachment;
18838} NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_TRIANGLES_DESC;
18839
18844typedef struct _NVAPI_D3D12_RAYTRACING_GEOMETRY_DESC_EX
18845{
18846 NVAPI_D3D12_RAYTRACING_GEOMETRY_TYPE_EX type;
18847 D3D12_RAYTRACING_GEOMETRY_FLAGS flags;
18848 union
18849 {
18850 D3D12_RAYTRACING_GEOMETRY_TRIANGLES_DESC triangles;
18852 D3D12_RAYTRACING_GEOMETRY_AABBS_DESC aabbs;
18854 NVAPI_D3D12_RAYTRACING_GEOMETRY_OMM_TRIANGLES_DESC ommTriangles;
18856 NVAPI_D3D12_RAYTRACING_GEOMETRY_DMM_TRIANGLES_DESC dmmTriangles;
18858 };
18859} NVAPI_D3D12_RAYTRACING_GEOMETRY_DESC_EX;
18860
18865typedef enum _NVAPI_D3D12_RAYTRACING_INSTANCE_FLAGS_EX
18866{
18867 // D3D12_RAYTRACING_INSTANCE_FLAGS flags
18868 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_NONE_EX = 0x0,
18869 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_TRIANGLE_CULL_DISABLE_EX = NV_BIT(0),
18870 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_TRIANGLE_FRONT_COUNTERCLOCKWISE_EX = NV_BIT(1),
18871 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_FORCE_OPAQUE_EX = NV_BIT(2),
18872 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_FORCE_NON_OPAQUE_EX = NV_BIT(3),
18873
18874 // NVAPI_D3D12_RAYTRACING_INSTANCE_FLAGS_EX specific flags
18875 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_FORCE_OMM_2_STATE_EX = NV_BIT(4),
18877 NVAPI_D3D12_RAYTRACING_INSTANCE_FLAG_DISABLE_OMMS_EX = NV_BIT(5)
18879} NVAPI_D3D12_RAYTRACING_INSTANCE_FLAGS_EX;
18880
18885typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_INPUTS_EX
18886{
18887 D3D12_RAYTRACING_ACCELERATION_STRUCTURE_TYPE type;
18888 NVAPI_D3D12_RAYTRACING_ACCELERATION_STRUCTURE_BUILD_FLAGS_EX flags;
18889 NvU32 numDescs;
18891 D3D12_ELEMENTS_LAYOUT descsLayout;
18893 NvU32 geometryDescStrideInBytes;
18896 union
18897 {
18898 D3D12_GPU_VIRTUAL_ADDRESS instanceDescs;
18900 const NVAPI_D3D12_RAYTRACING_GEOMETRY_DESC_EX* pGeometryDescs;
18902 const NVAPI_D3D12_RAYTRACING_GEOMETRY_DESC_EX*const* ppGeometryDescs;
18904 };
18905} NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_INPUTS_EX;
18906
18910typedef struct _NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_V1
18911{
18912 NvU32 version;
18913 const NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_INPUTS_EX* pDesc;
18914 D3D12_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO* pInfo;
18915} NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_V1;
18916#define NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_V1, 1)
18917typedef NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_V1 NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS;
18918#define NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_VER NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS_VER1
18919
18921//
18922// FUNCTION NAME: NvAPI_D3D12_GetRaytracingAccelerationStructurePrebuildInfoEx
18923//
18942NVAPI_INTERFACE NvAPI_D3D12_GetRaytracingAccelerationStructurePrebuildInfoEx(
18943 __in ID3D12Device5* pDevice,
18944 __inout NVAPI_GET_RAYTRACING_ACCELERATION_STRUCTURE_PREBUILD_INFO_EX_PARAMS* pParams);
18945
18946#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12Device5_INTERFACE_DEFINED__)
18947
18948#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
18949
18953typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_DESC
18954{
18955 D3D12_GPU_VIRTUAL_ADDRESS destOpacityMicromapArrayData;
18958 NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_INPUTS inputs;
18959 D3D12_GPU_VIRTUAL_ADDRESS scratchOpacityMicromapArrayData;
18965} NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_DESC;
18966
18970typedef struct _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE_DESC
18971{
18972 NvU64 currentSizeInBytes;
18975} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE_DESC;
18976
18980typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE
18981{
18982 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE = 0x0
18984} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE;
18985
18989typedef struct _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_DESC
18990{
18991 D3D12_GPU_VIRTUAL_ADDRESS destBuffer;
18995 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE infoType;
18996} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_DESC;
18997
19001typedef struct _NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1
19002{
19003 NvU32 version;
19004 const NVAPI_D3D12_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_DESC* pDesc;
19005 NvU32 numPostbuildInfoDescs;
19006 const NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_DESC* pPostbuildInfoDescs;
19008} NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1;
19009#define NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1, 1)
19010typedef NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1 NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS;
19011#define NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER1
19012
19014//
19015// FUNCTION NAME: NvAPI_D3D12_BuildRaytracingOpacityMicromapArray
19016//
19037NVAPI_INTERFACE NvAPI_D3D12_BuildRaytracingOpacityMicromapArray(
19038 __in ID3D12GraphicsCommandList4* pCommandList,
19039 __in NVAPI_BUILD_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS* pParams);
19040
19041#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19042
19043#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19044
19048typedef struct _NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1
19049{
19050 NvU32 version;
19051 D3D12_GPU_VIRTUAL_ADDRESS opacityMicromapArray;
19052} NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1;
19053#define NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1, 1)
19054typedef NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_V1 NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS;
19055#define NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS_VER1
19056
19058//
19059// FUNCTION NAME: NvAPI_D3D12_RelocateRaytracingOpacityMicromapArray
19060//
19077NVAPI_INTERFACE NvAPI_D3D12_RelocateRaytracingOpacityMicromapArray(
19078 __in ID3D12GraphicsCommandList4* pCommandList,
19079 __in const NVAPI_RELOCATE_RAYTRACING_OPACITY_MICROMAP_ARRAY_PARAMS* pParams);
19080
19081#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19082
19083#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19084
19088typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_DESC
19089{
19090 D3D12_GPU_VIRTUAL_ADDRESS destDisplacementMicromapArrayData;
19093 NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_INPUTS inputs;
19094 D3D12_GPU_VIRTUAL_ADDRESS scratchDisplacementMicromapArrayData;
19100} NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_DESC;
19101
19105typedef struct _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE_DESC
19106{
19107 NvU64 currentSizeInBytes;
19110} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE_DESC;
19111
19115typedef enum _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE
19116{
19117 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_CURRENT_SIZE = 0x0,
19119} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE;
19120
19124typedef struct _NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_DESC
19125{
19126 D3D12_GPU_VIRTUAL_ADDRESS destBuffer;
19130 NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_TYPE infoType;
19131} NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_DESC;
19132
19136typedef struct _NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1
19137{
19138 NvU32 version;
19139 const NVAPI_D3D12_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_DESC* pDesc;
19140 NvU32 numPostbuildInfoDescs;
19141 const NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_DESC* pPostbuildInfoDescs;
19143} NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1;
19144#define NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1, 1)
19145typedef NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1 NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS;
19146#define NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER1
19147
19149//
19150// FUNCTION NAME: NvAPI_D3D12_BuildRaytracingDisplacementMicromapArray
19151//
19172NVAPI_INTERFACE NvAPI_D3D12_BuildRaytracingDisplacementMicromapArray(
19173 __in ID3D12GraphicsCommandList4* pCommandList,
19174 __in NVAPI_BUILD_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS* pParams);
19175
19176#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19177
19178#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19179
19183typedef struct _NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1
19184{
19185 NvU32 version;
19186 D3D12_GPU_VIRTUAL_ADDRESS displacementMicromapArray;
19187} NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1;
19188#define NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1, 1)
19189typedef NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_V1 NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS;
19190#define NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS_VER1
19191
19193//
19194// FUNCTION NAME: NvAPI_D3D12_RelocateRaytracingDisplacementMicromapArray
19195//
19212NVAPI_INTERFACE NvAPI_D3D12_RelocateRaytracingDisplacementMicromapArray(
19213 __in ID3D12GraphicsCommandList4* pCommandList,
19214 __in const NVAPI_RELOCATE_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_PARAMS* pParams);
19215
19216#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19217
19218#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19219
19223typedef struct _NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1
19224{
19225 NvU32 version;
19226 const NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_DESC* pDesc;
19227 NvU32 numSources;
19228 const D3D12_GPU_VIRTUAL_ADDRESS* pSources;
19229} NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1;
19230#define NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1, 1)
19231typedef NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1 NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS;
19232#define NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER1
19233
19235//
19236// FUNCTION NAME: NvAPI_D3D12_EmitRaytracingDisplacementMicromapArrayPostbuildInfo
19237//
19253NVAPI_INTERFACE NvAPI_D3D12_EmitRaytracingDisplacementMicromapArrayPostbuildInfo(
19254 __in ID3D12GraphicsCommandList4* pCommandList,
19255 __in const NVAPI_EMIT_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS* pParams);
19256
19257#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19258
19259#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19260
19264typedef struct _NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1
19265{
19266 NvU32 version;
19267 const NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_DESC* pDesc;
19268 NvU32 numSources;
19269 const D3D12_GPU_VIRTUAL_ADDRESS* pSources;
19270} NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1;
19271#define NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1, 1)
19272typedef NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_V1 NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS;
19273#define NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS_VER1
19274
19276//
19277// FUNCTION NAME: NvAPI_D3D12_EmitRaytracingOpacityMicromapArrayPostbuildInfo
19278//
19294NVAPI_INTERFACE NvAPI_D3D12_EmitRaytracingOpacityMicromapArrayPostbuildInfo(
19295 __in ID3D12GraphicsCommandList4* pCommandList,
19296 __in const NVAPI_EMIT_RAYTRACING_OPACITY_MICROMAP_ARRAY_POSTBUILD_INFO_PARAMS* pParams);
19297
19298#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19299
19300#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19301
19306typedef struct _NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_DESC_EX
19307{
19308 D3D12_GPU_VIRTUAL_ADDRESS destAccelerationStructureData;
19309 NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_INPUTS_EX inputs;
19310 D3D12_GPU_VIRTUAL_ADDRESS sourceAccelerationStructureData;
19312 D3D12_GPU_VIRTUAL_ADDRESS scratchAccelerationStructureData;
19313} NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_DESC_EX;
19314
19318typedef struct _NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_V1
19319{
19320 NvU32 version;
19321 const NVAPI_D3D12_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_DESC_EX* pDesc;
19322 NvU32 numPostbuildInfoDescs;
19323 const D3D12_RAYTRACING_ACCELERATION_STRUCTURE_POSTBUILD_INFO_DESC* pPostbuildInfoDescs;
19325} NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_V1;
19326#define NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_V1, 1)
19327typedef NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_V1 NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS;
19328#define NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_VER NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS_VER1
19329
19331//
19332// FUNCTION NAME: NvAPI_D3D12_BuildRaytracingAccelerationStructureEx
19333//
19356NVAPI_INTERFACE NvAPI_D3D12_BuildRaytracingAccelerationStructureEx(
19357 __in ID3D12GraphicsCommandList4* pCommandList,
19358 __in const NVAPI_BUILD_RAYTRACING_ACCELERATION_STRUCTURE_EX_PARAMS* pParams);
19359
19360#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19361
19362#if defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19363
19365//
19366// Miscellaneous
19367//
19369
19374typedef enum _NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE
19375{
19376 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE_TRANSPARENT = 0,
19377 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE_OPAQUE = 1,
19378 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE_UNKNOWN_TRANSPARENT = 2,
19381 NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE_UNKNOWN_OPAQUE = 3
19384} NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_STATE;
19385
19389#define NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_ARRAY_BYTE_ALIGNMENT 256
19390
19394#define NVAPI_D3D12_RAYTRACING_OPACITY_MICROMAP_OC1_MAX_SUBDIVISION_LEVEL 12
19395
19400typedef enum _NVAPI_RAY_FLAGS_EX
19401{
19402 // RAY_FLAGS flags
19403 NVAPI_RAY_FLAG_NONE_EX = 0x0,
19404 NVAPI_RAY_FLAG_FORCE_OPAQUE_EX = NV_BIT( 0),
19405 NVAPI_RAY_FLAG_FORCE_NON_OPAQUE_EX = NV_BIT( 1),
19406 NVAPI_RAY_FLAG_ACCEPT_FIRST_HIT_AND_END_SEARCH_EX = NV_BIT( 2),
19407 NVAPI_RAY_FLAG_SKIP_CLOSEST_HIT_SHADER_EX = NV_BIT( 3),
19408 NVAPI_RAY_FLAG_CULL_BACK_FACING_TRIANGLES_EX = NV_BIT( 4),
19409 NVAPI_RAY_FLAG_CULL_FRONT_FACING_TRIANGLES_EX = NV_BIT( 5),
19410 NVAPI_RAY_FLAG_CULL_OPAQUE_EX = NV_BIT( 6),
19411 NVAPI_RAY_FLAG_CULL_NON_OPAQUE_EX = NV_BIT( 7),
19412 NVAPI_RAY_FLAG_SKIP_TRIANGLES_EX = NV_BIT( 8),
19413 NVAPI_RAY_FLAG_SKIP_PROCEDURAL_PRIMITIVES_EX = NV_BIT( 9),
19414
19415 // NVAPI_RAY_FLAGS_EX specific flags
19416 NVAPI_RAY_FLAG_FORCE_OMM_2_STATE_EX = NV_BIT(10),
19418} NVAPI_RAY_FLAG_EX;
19419
19423#define NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_ARRAY_BYTE_ALIGNMENT 256
19424
19428#define NVAPI_D3D12_RAYTRACING_DISPLACEMENT_MICROMAP_DC1_MAX_SUBDIVISION_LEVEL 5
19429
19430#endif // defined(__cplusplus) && defined(__d3d12_h__) && defined(__ID3D12GraphicsCommandList4_INTERFACE_DEFINED__)
19431
19432
19434typedef enum _NV_D3D12_WORKSTATION_FEATURE_TYPE
19435{
19436 NV_D3D12_WORKSTATION_FEATURE_TYPE_PRESENT_BARRIER = 1, // PresentBarrier feature
19437 NV_D3D12_WORKSTATION_FEATURE_TYPE_RDMA_BAR1_SUPPORT = 2, // RDMA heap supported via Bar1 carveout
19438} NV_D3D12_WORKSTATION_FEATURE_TYPE;
19439
19440// parameter structure for NV_D3D12_WORKSTATION_FEATURE_TYPE_RDMA_BAR1_AVAILABLE related information
19442{
19443 NvU64 rdmaHeapSize; // maximum available Bar1 heap size for RDMA allocations
19445
19446// parameter structure for querying workstation feature information
19458
19459#define NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS_VER1 MAKE_NVAPI_VERSION(NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS_V1,1)
19460#define NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS_VER NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS_VER1
19461#define NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS_V1
19462
19463
19464#if defined(__cplusplus) && defined(__d3d12_h__)
19466//
19467// FUNCTION NAME: NvAPI_D3D12_QueryWorkstationFeatureProperties
19468//
19486NVAPI_INTERFACE NvAPI_D3D12_QueryWorkstationFeatureProperties(__in ID3D12Device *pDevice, __inout NVAPI_D3D12_WORKSTATION_FEATURE_PROPERTIES_PARAMS *pWorkstationFeatureProperties);
19487#endif // defined(__cplusplus) && defined(__d3d12_h__)
19488
19489
19490#if defined (__cplusplus) && defined(__d3d12_h__)
19491
19493//
19494// FUNCTION NAME: NvAPI_D3D12_CreateCommittedRDMABuffer
19495//
19497//
19511
19521NVAPI_INTERFACE NvAPI_D3D12_CreateCommittedRDMABuffer(
19522 __in ID3D12Device* pDevice,
19523 __in NvU64 size,
19524 __in NvU32 heapCreationNodeMask,
19525 __in NvU32 heapVisibleNodeMask,
19526 __in REFIID riidResource,
19527 __out void **ppvResource,
19528 __out void **ppRDMAAddress);
19529
19530#endif //defined(__cplusplus) && defined(__d3d12_h__)
19531
19534#if defined(__cplusplus) && defined(__d3d12_h__)
19535
19537//
19538// NVAPI DIRECT TYPE NAME: INvAPI_DirectD3D12GraphicsCommandList
19539//
19541class INvAPI_DirectD3D12GraphicsCommandList
19542{
19543public:
19544 virtual bool IsValid() const = 0;
19545 virtual ID3D12GraphicsCommandList* GetID3D12GraphicsCommandList() const = 0;
19546
19547 void DispatchGraphics(NvU32 numDispatches);
19548 void SetMarker(void* pMarkerData, NvU32 markerSize);
19549};
19550
19552//
19553// NVAPI DIRECT FUNCTION NAME: NvAPI_DirectD3D12GraphicsCommandList_Create
19554//
19567NVAPI_INTERFACE NvAPI_DirectD3D12GraphicsCommandList_Create(__in ID3D12GraphicsCommandList *pDXD3D12GraphicsCommandList,
19568 __out INvAPI_DirectD3D12GraphicsCommandList **ppReturnD3D12GraphicsCommandList);
19569
19571//
19572// NVAPI DIRECT FUNCTION NAME: NvAPI_DirectD3D12GraphicsCommandList_Release
19573//
19584NVAPI_INTERFACE NvAPI_DirectD3D12GraphicsCommandList_Release(__in INvAPI_DirectD3D12GraphicsCommandList *pD3D12GraphicsCommandList);
19585
19586
19588//
19589// NVAPI DIRECT FUNCTION NAME: NvAPI_DirectD3D12GraphicsCommandList_Reset
19590//
19603NVAPI_INTERFACE NvAPI_DirectD3D12GraphicsCommandList_Reset(__in INvAPI_DirectD3D12GraphicsCommandList *pD3D12GraphicsCommandList);
19604#endif
19605
19606
19607
19609// Video Input Output (VIO) API
19611
19612
19613
19616typedef NvU32 NVVIOOWNERID;
19617
19618
19621
19622
19623#define NVVIOOWNERID_NONE 0
19624
19625
19633
19634// Access rights for NvAPI_VIO_Open()
19635
19637#define NVVIO_O_READ 0x00000000
19638
19640#define NVVIO_O_WRITE_EXCLUSIVE 0x00010001
19641
19643#define NVVIO_VALID_ACCESSRIGHTS (NVVIO_O_READ | \
19644 NVVIO_O_WRITE_EXCLUSIVE )
19645
19646
19649#define NVVIO_OWNERID_INITIALIZED 0x80000000
19650
19652#define NVVIO_OWNERID_EXCLUSIVE 0x40000000
19653
19656#define NVVIO_OWNERID_TYPEMASK 0x0FFFFFFF
19657
19658
19660
19661//---------------------------------------------------------------------
19662// Enumerations
19663//---------------------------------------------------------------------
19664
19665
19668
19671{
19706
19712
19716
19740
19742
19744
19755
19762
19770
19801
19809
19816
19824
19833
19844
19852
19859
19860
19862#define NVAPI_MAX_VIO_DEVICES 8
19863
19865#define NVAPI_MAX_VIO_JACKS 4
19866
19867
19872#define NVAPI_MAX_VIO_CHANNELS_PER_JACK 2
19873
19875#define NVAPI_MAX_VIO_STREAMS 4
19876
19877#define NVAPI_MIN_VIO_STREAMS 1
19878
19880#define NVAPI_MAX_VIO_LINKS_PER_STREAM 2
19881
19882
19883#define NVAPI_MAX_FRAMELOCK_MAPPING_MODES 20
19884
19886#define NVAPI_GVI_MIN_RAW_CAPTURE_IMAGES 1
19887
19889#define NVAPI_GVI_MAX_RAW_CAPTURE_IMAGES 32
19890
19892#define NVAPI_GVI_DEFAULT_RAW_CAPTURE_IMAGES 5
19893
19894
19895
19896// Data Signal notification events. These need a event handler in RM.
19897// Register/Unregister and PopEvent NVAPI's are already available.
19898
19905
19906typedef enum _NVVIOCOLORSPACE
19907{
19908 NVVIOCOLORSPACE_UNKNOWN,
19909 NVVIOCOLORSPACE_YCBCR,
19910 NVVIOCOLORSPACE_YCBCRA,
19911 NVVIOCOLORSPACE_YCBCRD,
19912 NVVIOCOLORSPACE_GBR,
19913 NVVIOCOLORSPACE_GBRA,
19914 NVVIOCOLORSPACE_GBRD,
19915} NVVIOCOLORSPACE;
19916
19919{
19920 NVVIOCOMPONENTSAMPLING_UNKNOWN,
19921 NVVIOCOMPONENTSAMPLING_4444,
19922 NVVIOCOMPONENTSAMPLING_4224,
19923 NVVIOCOMPONENTSAMPLING_444,
19924 NVVIOCOMPONENTSAMPLING_422
19926
19927typedef enum _NVVIOBITSPERCOMPONENT
19928{
19929 NVVIOBITSPERCOMPONENT_UNKNOWN,
19930 NVVIOBITSPERCOMPONENT_8,
19931 NVVIOBITSPERCOMPONENT_10,
19932 NVVIOBITSPERCOMPONENT_12,
19933} NVVIOBITSPERCOMPONENT;
19934
19935typedef enum _NVVIOLINKID
19936{
19937 NVVIOLINKID_UNKNOWN,
19938 NVVIOLINKID_A,
19939 NVVIOLINKID_B,
19940 NVVIOLINKID_C,
19941 NVVIOLINKID_D
19942} NVVIOLINKID;
19943
19944
19945typedef enum _NVVIOANCPARITYCOMPUTATION
19946{
19947 NVVIOANCPARITYCOMPUTATION_AUTO,
19948 NVVIOANCPARITYCOMPUTATION_ON,
19949 NVVIOANCPARITYCOMPUTATION_OFF
19950} NVVIOANCPARITYCOMPUTATION;
19951
19952
19953
19955
19956
19957//---------------------------------------------------------------------
19958// Structures
19959//---------------------------------------------------------------------
19960
19963
19964
19966#define NVVIOCAPS_VIDOUT_SDI 0x00000001
19967
19969#define NVVIOCAPS_SYNC_INTERNAL 0x00000100
19970
19972#define NVVIOCAPS_SYNC_GENLOCK 0x00000200
19973
19975#define NVVIOCAPS_SYNCSRC_SDI 0x00001000
19976
19978#define NVVIOCAPS_SYNCSRC_COMP 0x00002000
19979
19981#define NVVIOCAPS_OUTPUTMODE_DESKTOP 0x00010000
19982
19984#define NVVIOCAPS_OUTPUTMODE_OPENGL 0x00020000
19985
19987#define NVVIOCAPS_VIDIN_SDI 0x00100000
19988
19990#define NVVIOCAPS_PACKED_ANC_SUPPORTED 0x00200000
19991
19993#define NVVIOCAPS_AUDIO_BLANKING_SUPPORTED 0x00400000
19994
19996#define NVVIOCLASS_SDI 0x00000001
19997
19999typedef struct _NVVIOCAPS
20000{
20001 NvU32 version;
20002 NvAPI_String adapterName;
20007 NvU32 boardID;
20009 struct //
20010 {
20015 struct
20016 {
20023
20025#define NVVIOCAPS_VER1 MAKE_NVAPI_VERSION(NVVIOCAPS,1)
20026#define NVVIOCAPS_VER2 MAKE_NVAPI_VERSION(NVVIOCAPS,2)
20027#define NVVIOCAPS_VER NVVIOCAPS_VER2
20028
20039
20046
20065
20077
20079#define NVVIOSTATUS_VER MAKE_NVAPI_VERSION(NVVIOSTATUS,1)
20080
20083{
20084 NvU32 x;
20085 NvU32 y;
20086 NvU32 width;
20087 NvU32 height;
20089
20091typedef struct _NVVIOGAMMARAMP8
20092{
20093 NvU16 uRed[256];
20094 NvU16 uGreen[256];
20095 NvU16 uBlue[256];
20097
20099typedef struct _NVVIOGAMMARAMP10
20100{
20101 NvU16 uRed[1024];
20102 NvU16 uGreen[1024];
20103 NvU16 uBlue[1024];
20105
20106
20114
20116#define NVVIOSYNCDELAY_VER MAKE_NVAPI_VERSION(NVVIOSYNCDELAY,1)
20117
20118
20129
20136
20137
20139#define NVVIOBUFFERFORMAT_R8G8B8 0x00000001
20140
20142#define NVVIOBUFFERFORMAT_R8G8B8Z24 0x00000002
20143
20145#define NVVIOBUFFERFORMAT_R8G8B8A8 0x00000004
20146
20148#define NVVIOBUFFERFORMAT_R8G8B8A8Z24 0x00000008
20149
20151#define NVVIOBUFFERFORMAT_R16FPG16FPB16FP 0x00000010
20152
20154#define NVVIOBUFFERFORMAT_R16FPG16FPB16FPZ24 0x00000020
20155
20157#define NVVIOBUFFERFORMAT_R16FPG16FPB16FPA16FP 0x00000040
20158
20160#define NVVIOBUFFERFORMAT_R16FPG16FPB16FPA16FPZ24 0x00000080
20161
20162
20163
20170
20185
20187#define NVVIOCOLORCONVERSION_VER MAKE_NVAPI_VERSION(NVVIOCOLORCONVERSION,1)
20188
20204
20206#define NVVIOGAMMACORRECTION_VER MAKE_NVAPI_VERSION(NVVIOGAMMACORRECTION,1)
20207
20209#define MAX_NUM_COMPOSITE_RANGE 2
20210
20211
20213{
20214 NvU32 uRange;
20215 NvU32 uEnabled;
20216 NvU32 uMin;
20217 NvU32 uMax;
20219
20220
20221
20222// Device configuration (fields masks indicating NVVIOCONFIG fields to use for NvAPI_VIO_GetConfig/NvAPI_VIO_SetConfig() )
20223//
20224#define NVVIOCONFIG_SIGNALFORMAT 0x00000001
20225#define NVVIOCONFIG_DATAFORMAT 0x00000002
20226#define NVVIOCONFIG_OUTPUTREGION 0x00000004
20227#define NVVIOCONFIG_OUTPUTAREA 0x00000008
20228#define NVVIOCONFIG_COLORCONVERSION 0x00000010
20229#define NVVIOCONFIG_GAMMACORRECTION 0x00000020
20230#define NVVIOCONFIG_SYNCSOURCEENABLE 0x00000040
20231#define NVVIOCONFIG_SYNCDELAY 0x00000080
20232#define NVVIOCONFIG_COMPOSITESYNCTYPE 0x00000100
20233#define NVVIOCONFIG_FRAMELOCKENABLE 0x00000200
20234#define NVVIOCONFIG_422FILTER 0x00000400
20235#define NVVIOCONFIG_COMPOSITETERMINATE 0x00000800
20236#define NVVIOCONFIG_DATAINTEGRITYCHECK 0x00001000
20237#define NVVIOCONFIG_CSCOVERRIDE 0x00002000
20238#define NVVIOCONFIG_FLIPQUEUELENGTH 0x00004000
20239#define NVVIOCONFIG_ANCTIMECODEGENERATION 0x00008000
20240#define NVVIOCONFIG_COMPOSITE 0x00010000
20241#define NVVIOCONFIG_ALPHAKEYCOMPOSITE 0x00020000
20242#define NVVIOCONFIG_COMPOSITE_Y 0x00040000
20243#define NVVIOCONFIG_COMPOSITE_CR 0x00080000
20244#define NVVIOCONFIG_COMPOSITE_CB 0x00100000
20245#define NVVIOCONFIG_FULL_COLOR_RANGE 0x00200000
20246#define NVVIOCONFIG_RGB_DATA 0x00400000
20247#define NVVIOCONFIG_RESERVED_SDIOUTPUTENABLE 0x00800000
20248#define NVVIOCONFIG_STREAMS 0x01000000
20249#define NVVIOCONFIG_ANC_PARITY_COMPUTATION 0x02000000
20250#define NVVIOCONFIG_ANC_AUDIO_REPEAT 0x04000000
20251
20252
20253// Don't forget to update NVVIOCONFIG_VALIDFIELDS in nvapi.spec when NVVIOCONFIG_ALLFIELDS changes.
20254#define NVVIOCONFIG_ALLFIELDS ( NVVIOCONFIG_SIGNALFORMAT | \
20255 NVVIOCONFIG_DATAFORMAT | \
20256 NVVIOCONFIG_OUTPUTREGION | \
20257 NVVIOCONFIG_OUTPUTAREA | \
20258 NVVIOCONFIG_COLORCONVERSION | \
20259 NVVIOCONFIG_GAMMACORRECTION | \
20260 NVVIOCONFIG_SYNCSOURCEENABLE | \
20261 NVVIOCONFIG_SYNCDELAY | \
20262 NVVIOCONFIG_COMPOSITESYNCTYPE | \
20263 NVVIOCONFIG_FRAMELOCKENABLE | \
20264 NVVIOCONFIG_422FILTER | \
20265 NVVIOCONFIG_COMPOSITETERMINATE | \
20266 NVVIOCONFIG_DATAINTEGRITYCHECK | \
20267 NVVIOCONFIG_CSCOVERRIDE | \
20268 NVVIOCONFIG_FLIPQUEUELENGTH | \
20269 NVVIOCONFIG_ANCTIMECODEGENERATION | \
20270 NVVIOCONFIG_COMPOSITE | \
20271 NVVIOCONFIG_ALPHAKEYCOMPOSITE | \
20272 NVVIOCONFIG_COMPOSITE_Y | \
20273 NVVIOCONFIG_COMPOSITE_CR | \
20274 NVVIOCONFIG_COMPOSITE_CB | \
20275 NVVIOCONFIG_FULL_COLOR_RANGE | \
20276 NVVIOCONFIG_RGB_DATA | \
20277 NVVIOCONFIG_RESERVED_SDIOUTPUTENABLE | \
20278 NVVIOCONFIG_STREAMS | \
20279 NVVIOCONFIG_ANC_PARITY_COMPUTATION | \
20280 NVVIOCONFIG_ANC_AUDIO_REPEAT )
20281
20282#define NVVIOCONFIG_VALIDFIELDS ( NVVIOCONFIG_SIGNALFORMAT | \
20283 NVVIOCONFIG_DATAFORMAT | \
20284 NVVIOCONFIG_OUTPUTREGION | \
20285 NVVIOCONFIG_OUTPUTAREA | \
20286 NVVIOCONFIG_COLORCONVERSION | \
20287 NVVIOCONFIG_GAMMACORRECTION | \
20288 NVVIOCONFIG_SYNCSOURCEENABLE | \
20289 NVVIOCONFIG_SYNCDELAY | \
20290 NVVIOCONFIG_COMPOSITESYNCTYPE | \
20291 NVVIOCONFIG_FRAMELOCKENABLE | \
20292 NVVIOCONFIG_RESERVED_SDIOUTPUTENABLE | \
20293 NVVIOCONFIG_422FILTER | \
20294 NVVIOCONFIG_COMPOSITETERMINATE | \
20295 NVVIOCONFIG_DATAINTEGRITYCHECK | \
20296 NVVIOCONFIG_CSCOVERRIDE | \
20297 NVVIOCONFIG_FLIPQUEUELENGTH | \
20298 NVVIOCONFIG_ANCTIMECODEGENERATION | \
20299 NVVIOCONFIG_COMPOSITE | \
20300 NVVIOCONFIG_ALPHAKEYCOMPOSITE | \
20301 NVVIOCONFIG_COMPOSITE_Y | \
20302 NVVIOCONFIG_COMPOSITE_CR | \
20303 NVVIOCONFIG_COMPOSITE_CB | \
20304 NVVIOCONFIG_FULL_COLOR_RANGE | \
20305 NVVIOCONFIG_RGB_DATA | \
20306 NVVIOCONFIG_RESERVED_SDIOUTPUTENABLE | \
20307 NVVIOCONFIG_STREAMS | \
20308 NVVIOCONFIG_ANC_PARITY_COMPUTATION | \
20309 NVVIOCONFIG_ANC_AUDIO_REPEAT)
20310
20311#define NVVIOCONFIG_DRIVERFIELDS ( NVVIOCONFIG_OUTPUTREGION | \
20312 NVVIOCONFIG_OUTPUTAREA | \
20313 NVVIOCONFIG_COLORCONVERSION | \
20314 NVVIOCONFIG_FLIPQUEUELENGTH)
20315
20316#define NVVIOCONFIG_GAMMAFIELDS ( NVVIOCONFIG_GAMMACORRECTION )
20317
20318#define NVVIOCONFIG_RMCTRLFIELDS ( NVVIOCONFIG_SIGNALFORMAT | \
20319 NVVIOCONFIG_DATAFORMAT | \
20320 NVVIOCONFIG_SYNCSOURCEENABLE | \
20321 NVVIOCONFIG_COMPOSITESYNCTYPE | \
20322 NVVIOCONFIG_FRAMELOCKENABLE | \
20323 NVVIOCONFIG_422FILTER | \
20324 NVVIOCONFIG_COMPOSITETERMINATE | \
20325 NVVIOCONFIG_DATAINTEGRITYCHECK | \
20326 NVVIOCONFIG_COMPOSITE | \
20327 NVVIOCONFIG_ALPHAKEYCOMPOSITE | \
20328 NVVIOCONFIG_COMPOSITE_Y | \
20329 NVVIOCONFIG_COMPOSITE_CR | \
20330 NVVIOCONFIG_COMPOSITE_CB)
20331
20332#define NVVIOCONFIG_RMSKEWFIELDS ( NVVIOCONFIG_SYNCDELAY )
20333
20334#define NVVIOCONFIG_ALLOWSDIRUNNING_FIELDS ( NVVIOCONFIG_DATAINTEGRITYCHECK | \
20335 NVVIOCONFIG_SYNCDELAY | \
20336 NVVIOCONFIG_CSCOVERRIDE | \
20337 NVVIOCONFIG_ANCTIMECODEGENERATION | \
20338 NVVIOCONFIG_COMPOSITE | \
20339 NVVIOCONFIG_ALPHAKEYCOMPOSITE | \
20340 NVVIOCONFIG_COMPOSITE_Y | \
20341 NVVIOCONFIG_COMPOSITE_CR | \
20342 NVVIOCONFIG_COMPOSITE_CB | \
20343 NVVIOCONFIG_ANC_PARITY_COMPUTATION)
20344
20345
20346 #define NVVIOCONFIG_RMMODESET_FIELDS ( NVVIOCONFIG_SIGNALFORMAT | \
20347 NVVIOCONFIG_DATAFORMAT | \
20348 NVVIOCONFIG_SYNCSOURCEENABLE | \
20349 NVVIOCONFIG_FRAMELOCKENABLE | \
20350 NVVIOCONFIG_COMPOSITESYNCTYPE | \
20351 NVVIOCONFIG_ANC_AUDIO_REPEAT)
20352
20353
20355// No members can be deleted from below structure. Only add new members at the
20356// end of the structure.
20384
20413
20443
20457
20471
20483
20484
20496
20510
20511#define NVVIOCONFIG_VER1 MAKE_NVAPI_VERSION(NVVIOCONFIG_V1,1)
20512#define NVVIOCONFIG_VER2 MAKE_NVAPI_VERSION(NVVIOCONFIG_V2,2)
20513#define NVVIOCONFIG_VER3 MAKE_NVAPI_VERSION(NVVIOCONFIG_V3,3)
20514#define NVVIOCONFIG_VER NVVIOCONFIG_VER3
20515
20516
20517typedef struct
20518{
20519 NvPhysicalGpuHandle hPhysicalGpu;
20520 NvVioHandle hVioHandle;
20521 NvU32 vioId;
20522 NvU32 outputId;
20525
20532
20533
20535#define NV_VIO_TOPOLOGY_VER MAKE_NVAPI_VERSION(NV_VIO_TOPOLOGY,1)
20536
20538#define NVVIOTOPOLOGY_VER MAKE_NVAPI_VERSION(NVVIOTOPOLOGY,1)
20539
20540
20541
20543
20544
20545
20566__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20567NVAPI_INTERFACE NvAPI_VIO_GetCapabilities(NvVioHandle hVioHandle,
20568 NVVIOCAPS *pAdapterCaps);
20569
20570
20592__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20593NVAPI_INTERFACE NvAPI_VIO_Open(NvVioHandle hVioHandle,
20594 NvU32 vioClass,
20595 NVVIOOWNERTYPE ownerType);
20596
20616__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20617NVAPI_INTERFACE NvAPI_VIO_Close(NvVioHandle hVioHandle,
20618 NvU32 bRelease);
20636__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20637NVAPI_INTERFACE NvAPI_VIO_Status(NvVioHandle hVioHandle,
20638 NVVIOSTATUS *pStatus);
20639
20658__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20659NVAPI_INTERFACE NvAPI_VIO_SyncFormatDetect(NvVioHandle hVioHandle,
20660 NvU32 *pWait);
20678__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20679NVAPI_INTERFACE NvAPI_VIO_GetConfig(NvVioHandle hVioHandle,
20680 NVVIOCONFIG *pConfig);
20681
20699__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20700NVAPI_INTERFACE NvAPI_VIO_SetConfig(NvVioHandle hVioHandle,
20701 const NVVIOCONFIG *pConfig);
20702
20720__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_SetConfig.")
20721NVAPI_INTERFACE NvAPI_VIO_SetCSC(NvVioHandle hVioHandle,
20722 NVVIOCOLORCONVERSION *pCSC);
20740__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_GetConfig.")
20741NVAPI_INTERFACE NvAPI_VIO_GetCSC(NvVioHandle hVioHandle,
20742 NVVIOCOLORCONVERSION *pCSC);
20760__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_SetConfig.")
20761NVAPI_INTERFACE NvAPI_VIO_SetGamma(NvVioHandle hVioHandle,
20762 NVVIOGAMMACORRECTION *pGamma);
20763
20781__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_GetConfig.")
20782NVAPI_INTERFACE NvAPI_VIO_GetGamma(NvVioHandle hVioHandle,
20783 NVVIOGAMMACORRECTION* pGamma);
20801__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_SetConfig.")
20802NVAPI_INTERFACE NvAPI_VIO_SetSyncDelay(NvVioHandle hVioHandle,
20803 const NVVIOSYNCDELAY *pSyncDelay);
20804
20822__nvapi_deprecated_function("Do not use this function - it is deprecated in release 290. Instead, use NvAPI_VIO_GetConfig.")
20823NVAPI_INTERFACE NvAPI_VIO_GetSyncDelay(NvVioHandle hVioHandle,
20824 NVVIOSYNCDELAY *pSyncDelay);
20825
20826typedef enum _NVVIOPCILINKRATE
20827{
20828 NVVIOPCILINKRATE_UNKNOWN = 0,
20829 NVVIOPCILINKRATE_GEN1 = 1, //<! 2.5 Gbps.
20830 NVVIOPCILINKRATE_GEN2 = 2, //<! 5 Gbps.
20831 NVVIOPCILINKRATE_GEN3 = 3, //<! 8 Gbps.
20832}NVVIOPCILINKRATE;
20833
20834typedef enum _NVVIOPCILINKWIDTH
20835{
20836 NVVIOPCILINKWIDTH_UNKNOWN = 0,
20837 NVVIOPCILINKWIDTH_x1 = 1,
20838 NVVIOPCILINKWIDTH_x2 = 2,
20839 NVVIOPCILINKWIDTH_x4 = 4,
20840 NVVIOPCILINKWIDTH_x8 = 8,
20841 NVVIOPCILINKWIDTH_x16 = 16,
20842}NVVIOPCILINKWIDTH;
20843
20844typedef struct _NVVIOPCIINFO
20845{
20846 NvU32 version;
20847
20852 NvU32 pciBus;
20853 NvU32 pciSlot;
20854 NVVIOPCILINKWIDTH pciLinkWidth;
20855 NVVIOPCILINKRATE pciLinkRate;
20857
20859#define NVVIOPCIINFO_VER1 MAKE_NVAPI_VERSION(NVVIOPCIINFO_V1,1)
20860#define NVVIOPCIINFO_VER NVVIOPCIINFO_VER1
20861
20863//
20864// FUNCTION NAME: NvAPI_VIO_GetPCIInfo()
20865//
20866// DESCRIPTION: This API gets PCI information of the attached SDI(input) capture card.
20867//
20868// PARAMETERS: hVioHandle (IN) - Handle to SDI capture card.
20869// pVioPCIInfo (OUT) - PCI information of the attached SDI capture card.
20870//
20874//
20876//
20878__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20879NVAPI_INTERFACE NvAPI_VIO_GetPCIInfo(__in NvVioHandle hVioHandle,
20880 __inout NVVIOPCIINFO* pVioPCIInfo);
20881
20898__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20899NVAPI_INTERFACE NvAPI_VIO_IsRunning(NvVioHandle hVioHandle);
20900
20918__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20919NVAPI_INTERFACE NvAPI_VIO_Start(NvVioHandle hVioHandle);
20920
20938__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20939NVAPI_INTERFACE NvAPI_VIO_Stop(NvVioHandle hVioHandle);
20940
20941
20961__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20962NVAPI_INTERFACE NvAPI_VIO_IsFrameLockModeCompatible(NvVioHandle hVioHandle,
20963 NvU32 srcEnumIndex,
20964 NvU32 destEnumIndex,
20965 NvU32* pbCompatible);
20966
20967
20986__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
20987NVAPI_INTERFACE NvAPI_VIO_EnumDevices(NvVioHandle hVioHandle[NVAPI_MAX_VIO_DEVICES],
20988 NvU32 *vioDeviceCount);
20989
20990
21007__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
21008NVAPI_INTERFACE NvAPI_VIO_QueryTopology(NV_VIO_TOPOLOGY *pNvVIOTopology);
21009
21010
21029__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
21030NVAPI_INTERFACE NvAPI_VIO_EnumSignalFormats(NvVioHandle hVioHandle,
21031 NvU32 enumIndex,
21032 NVVIOSIGNALFORMATDETAIL *pSignalFormatDetail);
21033
21052__nvapi_deprecated_function("Do not use this function - it is deprecated in release 440.")
21053NVAPI_INTERFACE NvAPI_VIO_EnumDataFormats(NvVioHandle hVioHandle,
21054 NvU32 enumIndex,
21055 NVVIODATAFORMATDETAIL *pDataFormatDetail);
21056
21057
21059
21060
21061
21062
21064// CAMERA TEST API
21065// These APIs allows test apps to perform low level camera tests
21066
21070//
21071// FUNCTION NAME: NvAPI_Stereo_CreateConfigurationProfileRegistryKey
21072//
21107
21108
21117
21118
21120NVAPI_INTERFACE NvAPI_Stereo_CreateConfigurationProfileRegistryKey(NV_STEREO_REGISTRY_PROFILE_TYPE registryProfileType);
21121
21122
21123
21124
21126//
21127// FUNCTION NAME: NvAPI_Stereo_DeleteConfigurationProfileRegistryKey
21128//
21155
21157//
21158// FUNCTION NAME: NvAPI_Stereo_SetConfigurationProfileValue
21159//
21189//
21191
21192
21200
21201
21203NVAPI_INTERFACE NvAPI_Stereo_SetConfigurationProfileValue(NV_STEREO_REGISTRY_PROFILE_TYPE registryProfileType, NV_STEREO_REGISTRY_ID valueRegistryID, void *pValue);
21204
21205
21207//
21208// FUNCTION NAME: NvAPI_Stereo_DeleteConfigurationProfileValue
21209//
21236
21237
21238
21239
21240
21241
21244
21246{
21247 NvU32 version;
21248 NvU32 supportsWindowedModeOff : 1;
21249 NvU32 supportsWindowedModeAutomatic : 1;
21250 NvU32 supportsWindowedModePersistent : 1;
21251 NvU32 reserved : 29; // must be 0
21252 NvU32 reserved2[3]; // must be 0
21254
21255#define NVAPI_STEREO_CAPS_VER1 MAKE_NVAPI_VERSION(NVAPI_STEREO_CAPS,1)
21256#define NVAPI_STEREO_CAPS_VER NVAPI_STEREO_CAPS_VER1
21257
21259
21261
21263//
21264// FUNCTION NAME: NvAPI_Stereo_GetStereoSupport
21265//
21288NVAPI_INTERFACE NvAPI_Stereo_GetStereoSupport(__in NvMonitorHandle hMonitor, __out NVAPI_STEREO_CAPS *pCaps);
21289
21290
21291
21292
21293
21294
21295
21296
21297
21299//
21300// FUNCTION NAME: NvAPI_Stereo_DecreaseSeparation
21301//
21321NVAPI_INTERFACE NvAPI_Stereo_DecreaseSeparation(StereoHandle stereoHandle);
21322
21323
21325//
21326// FUNCTION NAME: NvAPI_Stereo_IncreaseSeparation
21327//
21347NVAPI_INTERFACE NvAPI_Stereo_IncreaseSeparation(StereoHandle stereoHandle);
21348
21349
21350
21351
21353//
21354// FUNCTION NAME: NvAPI_Stereo_DecreaseConvergence
21355//
21376
21377
21379//
21380// FUNCTION NAME: NvAPI_Stereo_IncreaseConvergence
21381//
21402
21403
21405//
21406// FUNCTION NAME: NvAPI_Stereo_GetFrustumAdjustMode
21407//
21428
21437
21439NVAPI_INTERFACE NvAPI_Stereo_GetFrustumAdjustMode(StereoHandle stereoHandle, NV_FRUSTUM_ADJUST_MODE *pFrustumAdjustMode);
21440
21441
21442
21443
21444
21446//
21447// FUNCTION NAME: NvAPI_Stereo_SetFrustumAdjustMode
21448//
21472NVAPI_INTERFACE NvAPI_Stereo_SetFrustumAdjustMode(StereoHandle stereoHandle, NV_FRUSTUM_ADJUST_MODE newFrustumAdjustModeValue);
21473
21474
21476//
21477// FUNCTION NAME: NvAPI_Stereo_CaptureJpegImage
21478//
21501NVAPI_INTERFACE NvAPI_Stereo_CaptureJpegImage(StereoHandle stereoHandle, NvU32 quality);
21502
21504//
21505// FUNCTION NAME: NvAPI_Stereo_InitActivation
21506//
21528
21531
21534{
21535 NVAPI_STEREO_INIT_ACTIVATION_IMMEDIATE = 0X00,
21536 NVAPI_STEREO_INIT_ACTIVATION_DELAYED = 0x01,
21538
21539NVAPI_INTERFACE NvAPI_Stereo_InitActivation(__in StereoHandle hStereoHandle, __in NVAPI_STEREO_INIT_ACTIVATION_FLAGS flags);
21540
21542
21544//
21545// FUNCTION NAME: NvAPI_Stereo_Trigger_Activation
21546//
21564NVAPI_INTERFACE NvAPI_Stereo_Trigger_Activation(__in StereoHandle hStereoHandle);
21565
21567//
21568// FUNCTION NAME: NvAPI_Stereo_CapturePngImage
21569//
21590NVAPI_INTERFACE NvAPI_Stereo_CapturePngImage(StereoHandle stereoHandle);
21591
21592
21594//
21595// FUNCTION NAME: NvAPI_Stereo_ReverseStereoBlitControl
21596//
21640NVAPI_INTERFACE NvAPI_Stereo_ReverseStereoBlitControl(StereoHandle hStereoHandle, NvU8 TurnOn);
21641
21642
21644//
21645// FUNCTION NAME: NvAPI_Stereo_SetNotificationMessage
21646//
21685NVAPI_INTERFACE NvAPI_Stereo_SetNotificationMessage(StereoHandle hStereoHandle, NvU64 hWnd,NvU64 messageID);
21686
21687
21688
21689
21690
21691
21692
21693
21694
21695
21696
21697
21698
21699
21700
21702#define NVAPI_STEREO_QUADBUFFERED_API_VERSION 0x2
21703
21705 typedef enum _NV_StereoSwapChainMode
21706 {
21707 NVAPI_STEREO_SWAPCHAIN_DEFAULT = 0,
21708 NVAPI_STEREO_SWAPCHAIN_STEREO = 1,
21709 NVAPI_STEREO_SWAPCHAIN_MONO = 2,
21710 } NV_STEREO_SWAPCHAIN_MODE;
21711
21712#if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
21714//
21715// FUNCTION NAME: NvAPI_D3D1x_CreateSwapChain
21716//
21742NVAPI_INTERFACE NvAPI_D3D1x_CreateSwapChain(StereoHandle hStereoHandle,
21743 DXGI_SWAP_CHAIN_DESC* pDesc,
21744 IDXGISwapChain** ppSwapChain,
21745 NV_STEREO_SWAPCHAIN_MODE mode);
21746
21747#endif //if defined(__d3d10_h__) || defined(__d3d10_1_h__) || defined(__d3d11_h__)
21748
21749
21750#if defined(_D3D9_H_) //NvAPI_D3D9_CreateSwapChain
21752//
21753// FUNCTION NAME: NvAPI_D3D9_CreateSwapChain
21754//
21779NVAPI_INTERFACE NvAPI_D3D9_CreateSwapChain(StereoHandle hStereoHandle,
21780 D3DPRESENT_PARAMETERS *pPresentationParameters,
21781 IDirect3DSwapChain9 **ppSwapChain,
21782 NV_STEREO_SWAPCHAIN_MODE mode);
21783#endif //if defined(_D3D9_H_) //NvAPI_D3D9_CreateSwapChain
21784
21785
21786
21787
21788
21791
21792
21793// GPU Profile APIs
21794
21795NV_DECLARE_HANDLE(NvDRSSessionHandle);
21796NV_DECLARE_HANDLE(NvDRSProfileHandle);
21797
21798#define NVAPI_DRS_GLOBAL_PROFILE ((NvDRSProfileHandle) -1)
21799
21800#define NVAPI_SETTING_MAX_VALUES 100
21801
21802typedef enum _NVDRS_SETTING_TYPE
21803{
21804 NVDRS_DWORD_TYPE,
21805 NVDRS_BINARY_TYPE,
21806 NVDRS_STRING_TYPE,
21807 NVDRS_WSTRING_TYPE
21808} NVDRS_SETTING_TYPE;
21809
21810typedef enum _NVDRS_SETTING_LOCATION
21811{
21812 NVDRS_CURRENT_PROFILE_LOCATION,
21813 NVDRS_GLOBAL_PROFILE_LOCATION,
21814 NVDRS_BASE_PROFILE_LOCATION,
21815 NVDRS_DEFAULT_PROFILE_LOCATION
21816} NVDRS_SETTING_LOCATION;
21817
21818
21820{
21821 NvU32 geforce : 1;
21822 NvU32 quadro : 1;
21823 NvU32 nvs : 1;
21824 NvU32 reserved4 : 1;
21825 NvU32 reserved5 : 1;
21826 NvU32 reserved6 : 1;
21827 NvU32 reserved7 : 1;
21828 NvU32 reserved8 : 1;
21829 NvU32 reserved9 : 1;
21830 NvU32 reserved10 : 1;
21831 NvU32 reserved11 : 1;
21832 NvU32 reserved12 : 1;
21833 NvU32 reserved13 : 1;
21834 NvU32 reserved14 : 1;
21835 NvU32 reserved15 : 1;
21836 NvU32 reserved16 : 1;
21837 NvU32 reserved17 : 1;
21838 NvU32 reserved18 : 1;
21839 NvU32 reserved19 : 1;
21840 NvU32 reserved20 : 1;
21841 NvU32 reserved21 : 1;
21842 NvU32 reserved22 : 1;
21843 NvU32 reserved23 : 1;
21844 NvU32 reserved24 : 1;
21845 NvU32 reserved25 : 1;
21846 NvU32 reserved26 : 1;
21847 NvU32 reserved27 : 1;
21848 NvU32 reserved28 : 1;
21849 NvU32 reserved29 : 1;
21850 NvU32 reserved30 : 1;
21851 NvU32 reserved31 : 1;
21852 NvU32 reserved32 : 1;
21854
21857{
21859 NvU8 valueData[NVAPI_BINARY_DATA_MAX];
21861
21863{
21864 NvU32 version;
21866 NVDRS_SETTING_TYPE settingType;
21867 union
21868 {
21872 NvAPI_UnicodeString wszDefaultValue;
21873 };
21874 union
21875 {
21876 NvU32 u32Value;
21878 NvAPI_UnicodeString wszValue;
21879 }settingValues[NVAPI_SETTING_MAX_VALUES];
21881
21883#define NVDRS_SETTING_VALUES_VER MAKE_NVAPI_VERSION(NVDRS_SETTING_VALUES,1)
21884
21885typedef struct _NVDRS_SETTING_V1
21886{
21887 NvU32 version;
21888 NvAPI_UnicodeString settingName;
21890 NVDRS_SETTING_TYPE settingType;
21891 NVDRS_SETTING_LOCATION settingLocation;
21895 union
21896 {
21901 NvAPI_UnicodeString wszPredefinedValue;
21902 };
21903 union
21904 {
21909 NvAPI_UnicodeString wszCurrentValue;
21910 };
21912
21914#define NVDRS_SETTING_VER1 MAKE_NVAPI_VERSION(NVDRS_SETTING_V1, 1)
21915
21917#define NVDRS_SETTING_VER NVDRS_SETTING_VER1
21918
21920{
21921 NvU32 version;
21923 NvAPI_UnicodeString appName;
21924 NvAPI_UnicodeString userFriendlyName;
21925 NvAPI_UnicodeString launcher;
21927
21929{
21930 NvU32 version;
21932 NvAPI_UnicodeString appName;
21933 NvAPI_UnicodeString userFriendlyName;
21934 NvAPI_UnicodeString launcher;
21935 NvAPI_UnicodeString fileInFolder;
21938
21940{
21941 NvU32 version;
21943 NvAPI_UnicodeString appName;
21944 NvAPI_UnicodeString userFriendlyName;
21945 NvAPI_UnicodeString launcher;
21946 NvAPI_UnicodeString fileInFolder;
21948 NvU32 isMetro:1;
21950 NvU32 reserved:30;
21952
21954{
21955 NvU32 version;
21957 NvAPI_UnicodeString appName;
21958 NvAPI_UnicodeString userFriendlyName;
21959 NvAPI_UnicodeString launcher;
21960 NvAPI_UnicodeString fileInFolder;
21962 NvU32 isMetro:1;
21964 NvU32 reserved:30;
21965 NvAPI_UnicodeString commandLine;
21968
21969#define NVDRS_APPLICATION_VER_V1 MAKE_NVAPI_VERSION(NVDRS_APPLICATION_V1,1)
21970#define NVDRS_APPLICATION_VER_V2 MAKE_NVAPI_VERSION(NVDRS_APPLICATION_V2,2)
21971#define NVDRS_APPLICATION_VER_V3 MAKE_NVAPI_VERSION(NVDRS_APPLICATION_V3,3)
21972#define NVDRS_APPLICATION_VER_V4 MAKE_NVAPI_VERSION(NVDRS_APPLICATION_V4,4)
21973
21975#define NVDRS_APPLICATION_VER NVDRS_APPLICATION_VER_V4
21976
21987
21989
21991#define NVDRS_PROFILE_VER1 MAKE_NVAPI_VERSION(NVDRS_PROFILE_V1,1)
21992#define NVDRS_PROFILE_VER NVDRS_PROFILE_VER1
21993
21994
21996//
21997// FUNCTION NAME: NvAPI_DRS_CreateSession
21998//
22008//
22010NVAPI_INTERFACE NvAPI_DRS_CreateSession(NvDRSSessionHandle *phSession);
22011
22012
22014//
22015// FUNCTION NAME: NvAPI_DRS_DestroySession
22016//
22026//
22028NVAPI_INTERFACE NvAPI_DRS_DestroySession(NvDRSSessionHandle hSession);
22029
22031//
22032// FUNCTION NAME: NvAPI_DRS_LoadSettings
22033//
22043//
22045NVAPI_INTERFACE NvAPI_DRS_LoadSettings(NvDRSSessionHandle hSession);
22046
22047
22049//
22050// FUNCTION NAME: NvAPI_DRS_SaveSettings
22051//
22061//
22063NVAPI_INTERFACE NvAPI_DRS_SaveSettings(NvDRSSessionHandle hSession);
22064
22066//
22067// FUNCTION NAME: NvAPI_DRS_LoadSettingsFromFile
22068//
22079//
22081NVAPI_INTERFACE NvAPI_DRS_LoadSettingsFromFile(NvDRSSessionHandle hSession, NvAPI_UnicodeString fileName);
22082
22084//
22085// FUNCTION NAME: NvAPI_DRS_SaveSettingsToFile
22086//
22097//
22099NVAPI_INTERFACE NvAPI_DRS_SaveSettingsToFile(NvDRSSessionHandle hSession, NvAPI_UnicodeString fileName);
22100
22102
22103
22104
22106//
22107// FUNCTION NAME: NvAPI_DRS_CreateProfile
22108//
22123NVAPI_INTERFACE NvAPI_DRS_CreateProfile(NvDRSSessionHandle hSession, NVDRS_PROFILE *pProfileInfo, NvDRSProfileHandle *phProfile);
22124
22126//
22127// FUNCTION NAME: NvAPI_DRS_DeleteProfile
22128//
22142NVAPI_INTERFACE NvAPI_DRS_DeleteProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile);
22143
22145//
22146// FUNCTION NAME: NvAPI_DRS_SetCurrentGlobalProfile
22147//
22161NVAPI_INTERFACE NvAPI_DRS_SetCurrentGlobalProfile(NvDRSSessionHandle hSession, NvAPI_UnicodeString wszGlobalProfileName);
22162
22163
22165//
22166// FUNCTION NAME: NvAPI_DRS_GetCurrentGlobalProfile
22167//
22181NVAPI_INTERFACE NvAPI_DRS_GetCurrentGlobalProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle *phProfile);
22182
22184//
22185// FUNCTION NAME: NvAPI_DRS_GetProfileInfo
22186//
22201NVAPI_INTERFACE NvAPI_DRS_GetProfileInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_PROFILE *pProfileInfo);
22202
22204//
22205// FUNCTION NAME: NvAPI_DRS_SetProfileInfo
22206//
22223NVAPI_INTERFACE NvAPI_DRS_SetProfileInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_PROFILE *pProfileInfo);
22224
22225
22227//
22228// FUNCTION NAME: NvAPI_DRS_FindProfileByName
22229//
22245NVAPI_INTERFACE NvAPI_DRS_FindProfileByName(NvDRSSessionHandle hSession, NvAPI_UnicodeString profileName, NvDRSProfileHandle* phProfile);
22246
22248//
22249// FUNCTION NAME: NvAPI_DRS_EnumProfiles
22250//
22266NVAPI_INTERFACE NvAPI_DRS_EnumProfiles(NvDRSSessionHandle hSession, NvU32 index, NvDRSProfileHandle *phProfile);
22267
22269//
22270// FUNCTION NAME: NvAPI_DRS_GetNumProfiles
22271//
22286NVAPI_INTERFACE NvAPI_DRS_GetNumProfiles(NvDRSSessionHandle hSession, NvU32 *numProfiles);
22287
22289//
22290// FUNCTION NAME: NvAPI_DRS_CreateApplication
22291//
22306NVAPI_INTERFACE NvAPI_DRS_CreateApplication(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_APPLICATION *pApplication);
22307
22308
22310//
22311// FUNCTION NAME: NvAPI_DRS_DeleteApplicationEx
22312//
22329NVAPI_INTERFACE NvAPI_DRS_DeleteApplicationEx(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_APPLICATION *pApp);
22330
22331
22333//
22334// FUNCTION NAME: NvAPI_DRS_DeleteApplication
22335//
22352NVAPI_INTERFACE NvAPI_DRS_DeleteApplication(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvAPI_UnicodeString appName);
22353
22355//
22356// FUNCTION NAME: NvAPI_DRS_GetApplicationInfo
22357//
22375// single out only one executable.
22380NVAPI_INTERFACE NvAPI_DRS_GetApplicationInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvAPI_UnicodeString appName, NVDRS_APPLICATION *pApplication);
22381
22383//
22384// FUNCTION NAME: NvAPI_DRS_EnumApplications
22385//
22403NVAPI_INTERFACE NvAPI_DRS_EnumApplications(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 startIndex, NvU32 *appCount, NVDRS_APPLICATION *pApplication);
22404
22406//
22407// FUNCTION NAME: NvAPI_DRS_FindApplicationByName
22408//
22430NVAPI_INTERFACE NvAPI_DRS_FindApplicationByName(__in NvDRSSessionHandle hSession, __in NvAPI_UnicodeString appName, __out NvDRSProfileHandle *phProfile, __inout NVDRS_APPLICATION *pApplication);
22431
22433//
22434// FUNCTION NAME: NvAPI_DRS_SetSetting
22435//
22450NVAPI_INTERFACE NvAPI_DRS_SetSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_SETTING *pSetting);
22451
22453//
22454// FUNCTION NAME: NvAPI_DRS_GetSetting
22455//
22471NVAPI_INTERFACE NvAPI_DRS_GetSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId, NVDRS_SETTING *pSetting);
22472
22473
22475//
22476// FUNCTION NAME: NvAPI_DRS_EnumSettings
22477//
22495NVAPI_INTERFACE NvAPI_DRS_EnumSettings(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 startIndex, NvU32 *settingsCount, NVDRS_SETTING *pSetting);
22496
22498//
22499// FUNCTION NAME: NvAPI_DRS_EnumAvailableSettingIds
22500//
22515NVAPI_INTERFACE NvAPI_DRS_EnumAvailableSettingIds(NvU32 *pSettingIds, NvU32 *pMaxCount);
22516
22518//
22519// FUNCTION NAME: NvAPI_DRS_EnumAvailableSettingValues
22520//
22535NVAPI_INTERFACE NvAPI_DRS_EnumAvailableSettingValues(NvU32 settingId, NvU32 *pMaxNumValues, NVDRS_SETTING_VALUES *pSettingValues);
22536
22538//
22539// FUNCTION NAME: NvAPI_DRS_GetSettingIdFromName
22540//
22556NVAPI_INTERFACE NvAPI_DRS_GetSettingIdFromName(NvAPI_UnicodeString settingName, NvU32 *pSettingId);
22557
22559//
22560// FUNCTION NAME: NvAPI_DRS_GetSettingNameFromId
22561//
22577NVAPI_INTERFACE NvAPI_DRS_GetSettingNameFromId(NvU32 settingId, NvAPI_UnicodeString *pSettingName);
22578
22580//
22581// FUNCTION NAME: NvAPI_DRS_DeleteProfileSetting
22582//
22597NVAPI_INTERFACE NvAPI_DRS_DeleteProfileSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId);
22598
22600//
22601// FUNCTION NAME: NvAPI_DRS_RestoreAllDefaults
22602//
22615NVAPI_INTERFACE NvAPI_DRS_RestoreAllDefaults(NvDRSSessionHandle hSession);
22616
22618//
22619// FUNCTION NAME: NvAPI_DRS_RestoreProfileDefault
22620//
22638NVAPI_INTERFACE NvAPI_DRS_RestoreProfileDefault(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile);
22639
22641//
22642// FUNCTION NAME: NvAPI_DRS_RestoreProfileDefaultSetting
22643//
22658NVAPI_INTERFACE NvAPI_DRS_RestoreProfileDefaultSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId);
22659
22661//
22662// FUNCTION NAME: NvAPI_DRS_GetBaseProfile
22663//
22677NVAPI_INTERFACE NvAPI_DRS_GetBaseProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle *phProfile);
22678
22679
22680
22681
22684
22685typedef struct
22686{
22687 NvU32 version;
22688 NvU32 vendorId;
22689 NvU32 deviceId;
22690 NvAPI_ShortString szVendorName;
22691 NvAPI_ShortString szChipsetName;
22692 NvU32 flags;
22695 NvAPI_ShortString szSubSysVendorName;
22700
22702
22703typedef struct
22704{
22705 NvU32 version;
22706 NvU32 vendorId;
22707 NvU32 deviceId;
22708 NvAPI_ShortString szVendorName;
22709 NvAPI_ShortString szChipsetName;
22710 NvU32 flags;
22713 NvAPI_ShortString szSubSysVendorName;
22715
22716typedef enum
22717{
22718 NV_CHIPSET_INFO_HYBRID = 0x00000001,
22719} NV_CHIPSET_INFO_FLAGS;
22720
22721typedef struct
22722{
22723 NvU32 version;
22724 NvU32 vendorId;
22725 NvU32 deviceId;
22726 NvAPI_ShortString szVendorName;
22727 NvAPI_ShortString szChipsetName;
22728 NvU32 flags;
22730
22731typedef struct
22732{
22733 NvU32 version; //structure version
22734 NvU32 vendorId; //vendor ID
22735 NvU32 deviceId; //device ID
22736 NvAPI_ShortString szVendorName; //vendor Name
22737 NvAPI_ShortString szChipsetName; //device Name
22739
22740#define NV_CHIPSET_INFO_VER_1 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v1,1)
22741#define NV_CHIPSET_INFO_VER_2 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v2,2)
22742#define NV_CHIPSET_INFO_VER_3 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v3,3)
22743#define NV_CHIPSET_INFO_VER_4 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v4,4)
22744
22745#define NV_CHIPSET_INFO NV_CHIPSET_INFO_v4
22746#define NV_CHIPSET_INFO_VER NV_CHIPSET_INFO_VER_4
22747
22749
22751//
22752// FUNCTION NAME: NvAPI_SYS_GetChipSetInfo
22753//
22766NVAPI_INTERFACE NvAPI_SYS_GetChipSetInfo(NV_CHIPSET_INFO *pChipSetInfo);
22767
22768
22771typedef struct
22772{
22773 NvU32 version;
22775 NvU32 currentDockState;
22776 NvU32 currentLidPolicy;
22777 NvU32 currentDockPolicy;
22778 NvU32 forcedLidMechanismPresent;
22779 NvU32 forcedDockMechanismPresent;
22781
22782
22784#define NV_LID_DOCK_PARAMS_VER MAKE_NVAPI_VERSION(NV_LID_DOCK_PARAMS,1)
22786//
22787// FUNCTION NAME: NvAPI_GetLidDockInfo
22788//
22805
22806
22807
22808
22810// FUNCTION NAME: NvAPI_SYS_GetDisplayIdFromGpuAndOutputId
22811//
22831NVAPI_INTERFACE NvAPI_SYS_GetDisplayIdFromGpuAndOutputId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputId, NvU32* displayId);
22832
22833
22835// FUNCTION NAME: NvAPI_SYS_GetGpuAndOutputIdFromDisplayId
22836//
22858NVAPI_INTERFACE NvAPI_SYS_GetGpuAndOutputIdFromDisplayId(NvU32 displayId, NvPhysicalGpuHandle *hPhysicalGpu, NvU32 *outputId);
22859
22860
22862// FUNCTION NAME: NvAPI_SYS_GetPhysicalGpuFromDisplayId
22863//
22884NVAPI_INTERFACE NvAPI_SYS_GetPhysicalGpuFromDisplayId(NvU32 displayId, NvPhysicalGpuHandle *hPhysicalGpu);
22885
22905
22927
22928#define NV_DISPLAY_DRIVER_INFO_VER1 MAKE_NVAPI_VERSION(NV_DISPLAY_DRIVER_INFO_V1, 1)
22929#define NV_DISPLAY_DRIVER_INFO_VER2 MAKE_NVAPI_VERSION(NV_DISPLAY_DRIVER_INFO_V2, 2)
22931#define NV_DISPLAY_DRIVER_INFO_VER NV_DISPLAY_DRIVER_INFO_VER2
22932
22934//
22935// FUNCTION NAME: NvAPI_SYS_GetDisplayDriverInfo
22936//
22954NVAPI_INTERFACE NvAPI_SYS_GetDisplayDriverInfo(__inout NV_DISPLAY_DRIVER_INFO *pDriverInfo);
22955
22956
22972
22974
22975
22999
23015
23016
23021{
23022 NV_GPU_CLIENT_UTIL_DOMAIN_GRAPHICS = 0,
23023 NV_GPU_CLIENT_UTIL_DOMAIN_FRAME_BUFFER = 1,
23024 NV_GPU_CLIENT_UTIL_DOMAIN_VIDEO = 2,
23030
23031#define NV_GPU_CLIENT_UTIL_DOMAINS_MAX_V1 (4)
23032
23054
23087
23091typedef void (__cdecl *NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_V1)(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLIENT_CALLBACK_UTILIZATION_DATA_V1* pData);
23092
23119
23120#define NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_VER1 MAKE_NVAPI_VERSION(NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_V1, 1)
23122#define NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_VER NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_VER1
23123
23125//
23126// FUNCTION NAME: NvAPI_GPU_ClientRegisterForUtilizationSampleUpdates
23127//
23148NVAPI_INTERFACE NvAPI_GPU_ClientRegisterForUtilizationSampleUpdates(__in NvPhysicalGpuHandle hPhysicalGpu, __in NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS* pCallbackSettings);
23149
23150
23151
23152
23153
23154#ifdef __cplusplus
23155}; //extern "C" {
23156
23157#endif
23158
23159#pragma pack(pop)
23160
23161#endif // _NVAPI_H
23162
23163#include"nvapi_lite_salend.h"
NVAPI_INTERFACE NvAPI_DISP_SetDisplayConfig(__in NvU32 pathInfoCount, __in_ecount(pathInfoCount) NV_DISPLAYCONFIG_PATH_INFO *pathInfo, __in NvU32 flags)
enum _NV_DP_LINK_RATE NV_DP_LINK_RATE
_NV_DP_BPC
Definition nvapi.h:257
_NV_DP_COLORIMETRY
Definition nvapi.h:238
NVAPI_INTERFACE NvAPI_DISP_DeleteCustomDisplay(__in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in NV_CUSTOM_DISPLAY *pCustDisp)
NVAPI_INTERFACE NvAPI_DISP_EnumCustomDisplay(__in NvU32 displayId, __in NvU32 index, __inout NV_CUSTOM_DISPLAY *pCustDisp)
NVAPI_INTERFACE NvAPI_DISP_RevertCustomDisplayTrial(__in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count)
enum _NV_DP_LANE_COUNT NV_DP_LANE_COUNT
NVAPI_INTERFACE NvAPI_CreateDisplayFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvDisplayHandle *pNvDisplay)
enum _NV_DP_COLORIMETRY NV_DP_COLORIMETRY
NVAPI_INTERFACE NvAPI_DISP_GetPreferredStereoDisplay(__inout NV_GET_PREFERRED_STEREO_DISPLAY *pPreferredStereoDisplay)
NVAPI_INTERFACE NvAPI_DISP_SaveCustomDisplay(__in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in NvU32 isThisOutputIdOnly, __in NvU32 isThisMonitorIdOnly)
NVAPI_INTERFACE NvAPI_DISP_GetVirtualRefreshRateData(__in NvU32 displayId, __inout NV_GET_VIRTUAL_REFRESH_RATE_DATA *pVirtualRefreshRateData)
enum _NV_DP_DYNAMIC_RANGE NV_DP_DYNAMIC_RANGE
NVAPI_INTERFACE NvAPI_DISP_GetMonitorCapabilities(__in NvU32 displayId, __inout NV_MONITOR_CAPABILITIES *pMonitorCapabilities)
struct _NV_HDMI_SUPPORT_INFO_V1 NV_HDMI_SUPPORT_INFO_V1
struct _NV_TIMING NV_TIMING
_NV_TARGET_VIEW_MODE
Used in NvAPI_SetView().
Definition nvapi.h:486
struct _NV_TIMING_INPUT NV_TIMING_INPUT
NVAPI_INTERFACE NvAPI_DISP_GetDisplayIdByDisplayName(const char *displayName, NvU32 *displayId)
NVAPI_INTERFACE NvAPI_Disp_GetVRRInfo(__in NvU32 displayId, __inout NV_GET_VRR_INFO *pVrrInfo)
NVAPI_INTERFACE NvAPI_DISP_GetMonitorColorCapabilities(__in NvU32 displayId, __inout_ecount_part_opt(*pColorCapsCount, *pColorCapsCount) NV_MONITOR_COLOR_CAPS *pMonitorColorCapabilities, __inout NvU32 *pColorCapsCount)
NVAPI_INTERFACE NvAPI_GetUnAttachedAssociatedDisplayName(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvAPI_ShortString szDisplayName)
NVAPI_INTERFACE NvAPI_Disp_InfoFrameControl(__in NvU32 displayId, __inout NV_INFOFRAME_DATA *pInfoframeData)
struct _NV_DISPLAY_PORT_INFO_V1 NV_DISPLAY_PORT_INFO_V1
enum _NV_TARGET_VIEW_MODE NV_TARGET_VIEW_MODE
Used in NvAPI_SetView().
NVAPI_INTERFACE NvAPI_DISP_TryCustomDisplay(__in_ecount(count) NvU32 *pDisplayIds, __in NvU32 count, __in_ecount(count) NV_CUSTOM_DISPLAY *pCustDisp)
enum _NV_ROTATE NV_ROTATE
Rotate modes- used in NvAPI_SetViewEx().
NVAPI_INTERFACE NvAPI_GetSupportedViews(NvDisplayHandle hNvDisplay, NV_TARGET_VIEW_MODE *pTargetViews, NvU32 *pViewCount)
_NV_ROTATE
Rotate modes- used in NvAPI_SetViewEx().
Definition nvapi.h:528
_NV_DP_LANE_COUNT
Definition nvapi.h:218
NVAPI_INTERFACE NvAPI_GetVBlankCounter(NvDisplayHandle hNvDisplay, NvU32 *pCounter)
_NV_DP_LINK_RATE
Definition nvapi.h:202
struct tagNV_TIMINGEXT NV_TIMINGEXT
NVAPI_INTERFACE NvAPI_GetAssociatedDisplayOutputId(NvDisplayHandle hNvDisplay, NvU32 *pOutputId)
_NV_SCALING
Definition nvapi.h:503
_NV_DP_COLOR_FORMAT
Definition nvapi.h:228
NVAPI_INTERFACE NvAPI_DISP_SetAdaptiveSyncData(__in NvU32 displayId, __in NV_SET_ADAPTIVE_SYNC_DATA *pAdaptiveSyncData)
NVAPI_INTERFACE NvAPI_DisableHWCursor(NvDisplayHandle hNvDisplay)
struct _NV_GET_VRR_INFO_V1 NV_GET_VRR_INFO_V1
_NV_DISPLAYCONFIG_FLAGS
Definition nvapi.h:1049
NVAPI_INTERFACE NvAPI_DISP_GetAdaptiveSyncData(__in NvU32 displayId, __inout NV_GET_ADAPTIVE_SYNC_DATA *pAdaptiveSyncData)
NVAPI_INTERFACE NvAPI_DISP_GetDisplayConfig(__inout NvU32 *pathInfoCount, __out_ecount_full_opt(*pathInfoCount) NV_DISPLAYCONFIG_PATH_INFO *pathInfo)
_NV_TIMING_OVERRIDE
Definition nvapi.h:573
NVAPI_INTERFACE NvAPI_EnableHWCursor(NvDisplayHandle hNvDisplay)
enum _NV_SCALING NV_SCALING
NV_DISPLAYCONFIG_PATH_TARGET_INFO_V2 NV_DISPLAYCONFIG_PATH_TARGET_INFO
Definition nvapi.h:969
enum _NV_FORMAT NV_FORMAT
enum _NV_DP_BPC NV_DP_BPC
_NV_FORMAT
Definition nvapi.h:547
enum _NV_DP_COLOR_FORMAT NV_DP_COLOR_FORMAT
NVAPI_INTERFACE NvAPI_DISP_SetVirtualRefreshRateData(__in NvU32 displayId, __in NV_SET_VIRTUAL_REFRESH_RATE_DATA *pVirtualRefreshRateData)
_NV_DP_DYNAMIC_RANGE
Definition nvapi.h:248
NVAPI_INTERFACE NvAPI_DISP_SetPreferredStereoDisplay(__in NV_SET_PREFERRED_STEREO_DISPLAY *pPreferredStereoDisplay)
NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayName(NvDisplayHandle NvDispHandle, NvAPI_ShortString szDisplayName)
NVAPI_INTERFACE NvAPI_DISP_GetTiming(__in NvU32 displayId, __in NV_TIMING_INPUT *timingInput, __out NV_TIMING *pTiming)
enum _NV_TIMING_OVERRIDE NV_TIMING_OVERRIDE
NVAPI_INTERFACE NvAPI_SetRefreshRateOverride(NvDisplayHandle hNvDisplay, NvU32 outputsMask, float refreshRate, NvU32 bSetDeferred)
NV_INFOFRAME_CMD
Definition nvapi.h:6746
@ NV_SCALING_GPU_INTEGER_ASPECT_SCALING
Force GPU - Integer Scaling.
Definition nvapi.h:513
@ NV_SCALING_CUSTOMIZED
For future use.
Definition nvapi.h:521
@ NV_SCALING_DEFAULT
No change.
Definition nvapi.h:504
@ NV_SCALING_GPU_SCANOUT_TO_NATIVE
Force GPU - Centered\No Scaling.
Definition nvapi.h:509
@ NV_SCALING_GPU_SCALING_TO_CLOSEST
Balanced - Full Screen.
Definition nvapi.h:507
@ NV_SCALING_GPU_SCANOUT_TO_CLOSEST
Balanced - Centered\No Scaling.
Definition nvapi.h:512
@ NV_SCALING_GPU_SCALING_TO_NATIVE
Force GPU - Full Screen.
Definition nvapi.h:508
@ NV_SCALING_GPU_SCALING_TO_ASPECT_SCANOUT_TO_NATIVE
Force GPU - Aspect Ratio.
Definition nvapi.h:510
@ NV_SCALING_GPU_SCALING_TO_ASPECT_SCANOUT_TO_CLOSEST
Balanced - Aspect Ratio.
Definition nvapi.h:511
@ NV_DISPLAYCONFIG_FORCE_MODE_ENUMERATION
Refresh OS mode list.
Definition nvapi.h:1053
@ NV_DISPLAYCONFIG_DRIVER_RELOAD_ALLOWED
Driver reload is permitted if necessary.
Definition nvapi.h:1052
@ NV_FORCE_COMMIT_VIDPN
Tell OS to avoid optimizing CommitVidPn call during a modeset.
Definition nvapi.h:1054
@ NV_TIMING_OVERRIDE_CURRENT
get the current timing
Definition nvapi.h:574
@ NV_TIMING_OVERRIDE_CVT_RB
VESA CVT timing with reduced blanking.
Definition nvapi.h:580
@ NV_TIMING_OVERRIDE_DMT
VESA DMT timing.
Definition nvapi.h:577
@ NV_TIMING_OVERRIDE_DMT_RB
VESA DMT timing with reduced blanking.
Definition nvapi.h:578
@ NV_TIMING_OVERRIDE_EIA861
EIA 861x pre-defined timing.
Definition nvapi.h:582
@ NV_TIMING_OVERRIDE_GTF
VESA GTF timing.
Definition nvapi.h:581
@ NV_TIMING_OVERRIDE_SDI
Override for SDI timing.
Definition nvapi.h:588
@ NV_TIMING_OVERRIDE_CUST
NV custom timings.
Definition nvapi.h:584
@ NV_TIMING_OVERRIDE_CVT
VESA CVT timing.
Definition nvapi.h:579
@ NV_TIMING_OVERRIDE_EDID
EDID timing.
Definition nvapi.h:576
@ NV_TIMING_OVERRIDE_ANALOG_TV
analog SD/HDTV timing
Definition nvapi.h:583
@ NV_TIMING_OVERRIDE_AUTO
the timing the driver will use based the current policy
Definition nvapi.h:575
@ NV_TIMING_OVERRIDE_NV_PREDEFINED
NV pre-defined timing (basically the PsF timings)
Definition nvapi.h:585
@ NV_FORMAT_A16B16G16R16F
for 64bpp(floating point) mode.
Definition nvapi.h:552
@ NV_FORMAT_R5G6B5
for 16bpp mode
Definition nvapi.h:550
@ NV_FORMAT_UNKNOWN
unknown. Driver will choose one as following value.
Definition nvapi.h:548
@ NV_FORMAT_P8
for 8bpp mode
Definition nvapi.h:549
@ NV_FORMAT_A8R8G8B8
for 32bpp mode
Definition nvapi.h:551
@ NV_INFOFRAME_CMD_RESET
Sets the fields in the infoframe to auto, and infoframe to the default infoframe for use in a set.
Definition nvapi.h:6748
@ NV_INFOFRAME_CMD_SET
Set the current infoframe state (flushed to the monitor), the values are one time and do not persist.
Definition nvapi.h:6750
@ NV_INFOFRAME_CMD_SET_PROPERTY
set properties associated with infoframe
Definition nvapi.h:6754
@ NV_INFOFRAME_CMD_SET_OVERRIDE
Set the override infoframe state, non-override fields will be set to value = AUTO,...
Definition nvapi.h:6752
@ NV_INFOFRAME_CMD_GET_OVERRIDE
Get the override infoframe state, non-override fields will be set to value = AUTO,...
Definition nvapi.h:6751
@ NV_INFOFRAME_CMD_GET_PROPERTY
get properties associated with infoframe (each of the infoframe type will have properties)
Definition nvapi.h:6753
@ NV_INFOFRAME_CMD_GET
Get the current infoframe state.
Definition nvapi.h:6749
@ NV_INFOFRAME_CMD_GET_DEFAULT
Returns the fields in the infoframe with values set by the manufacturer - NVIDIA/OEM.
Definition nvapi.h:6747
NVAPI_INTERFACE NvAPI_DRS_EnumProfiles(NvDRSSessionHandle hSession, NvU32 index, NvDRSProfileHandle *phProfile)
NVAPI_INTERFACE NvAPI_DRS_DeleteProfileSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId)
struct _NVDRS_BINARY_SETTING NVDRS_BINARY_SETTING
Enum to decide on the datatype of setting value.
NVAPI_INTERFACE NvAPI_DRS_GetNumProfiles(NvDRSSessionHandle hSession, NvU32 *numProfiles)
NVAPI_INTERFACE NvAPI_DRS_CreateProfile(NvDRSSessionHandle hSession, NVDRS_PROFILE *pProfileInfo, NvDRSProfileHandle *phProfile)
NVAPI_INTERFACE NvAPI_DRS_GetApplicationInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvAPI_UnicodeString appName, NVDRS_APPLICATION *pApplication)
NVAPI_INTERFACE NvAPI_DRS_GetProfileInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_PROFILE *pProfileInfo)
NVAPI_INTERFACE NvAPI_DRS_SetCurrentGlobalProfile(NvDRSSessionHandle hSession, NvAPI_UnicodeString wszGlobalProfileName)
NVAPI_INTERFACE NvAPI_DRS_DeleteApplicationEx(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_APPLICATION *pApp)
NVAPI_INTERFACE NvAPI_DRS_GetBaseProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle *phProfile)
NVAPI_INTERFACE NvAPI_DRS_GetSettingNameFromId(NvU32 settingId, NvAPI_UnicodeString *pSettingName)
NVAPI_INTERFACE NvAPI_DRS_CreateApplication(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_APPLICATION *pApplication)
NVAPI_INTERFACE NvAPI_DRS_EnumSettings(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 startIndex, NvU32 *settingsCount, NVDRS_SETTING *pSetting)
NVAPI_INTERFACE NvAPI_DRS_RestoreAllDefaults(NvDRSSessionHandle hSession)
NVAPI_INTERFACE NvAPI_DRS_GetCurrentGlobalProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle *phProfile)
NVAPI_INTERFACE NvAPI_DRS_EnumApplications(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 startIndex, NvU32 *appCount, NVDRS_APPLICATION *pApplication)
NVAPI_INTERFACE NvAPI_DRS_EnumAvailableSettingValues(NvU32 settingId, NvU32 *pMaxNumValues, NVDRS_SETTING_VALUES *pSettingValues)
NVAPI_INTERFACE NvAPI_DRS_GetSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId, NVDRS_SETTING *pSetting)
NVAPI_INTERFACE NvAPI_DRS_DeleteApplication(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvAPI_UnicodeString appName)
NVAPI_INTERFACE NvAPI_DRS_LoadSettings(NvDRSSessionHandle hSession)
NVAPI_INTERFACE NvAPI_DRS_FindApplicationByName(__in NvDRSSessionHandle hSession, __in NvAPI_UnicodeString appName, __out NvDRSProfileHandle *phProfile, __inout NVDRS_APPLICATION *pApplication)
NVAPI_INTERFACE NvAPI_DRS_RestoreProfileDefaultSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NvU32 settingId)
NVAPI_INTERFACE NvAPI_DRS_RestoreProfileDefault(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile)
NVAPI_INTERFACE NvAPI_DRS_LoadSettingsFromFile(NvDRSSessionHandle hSession, NvAPI_UnicodeString fileName)
NVAPI_INTERFACE NvAPI_DRS_SaveSettings(NvDRSSessionHandle hSession)
NVAPI_INTERFACE NvAPI_DRS_EnumAvailableSettingIds(NvU32 *pSettingIds, NvU32 *pMaxCount)
NVAPI_INTERFACE NvAPI_DRS_SetProfileInfo(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_PROFILE *pProfileInfo)
NVAPI_INTERFACE NvAPI_DRS_DeleteProfile(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile)
NVAPI_INTERFACE NvAPI_DRS_GetSettingIdFromName(NvAPI_UnicodeString settingName, NvU32 *pSettingId)
NVAPI_INTERFACE NvAPI_DRS_FindProfileByName(NvDRSSessionHandle hSession, NvAPI_UnicodeString profileName, NvDRSProfileHandle *phProfile)
NVAPI_INTERFACE NvAPI_DRS_SetSetting(NvDRSSessionHandle hSession, NvDRSProfileHandle hProfile, NVDRS_SETTING *pSetting)
NVAPI_INTERFACE NvAPI_DRS_CreateSession(NvDRSSessionHandle *phSession)
NVAPI_INTERFACE NvAPI_DRS_SaveSettingsToFile(NvDRSSessionHandle hSession, NvAPI_UnicodeString fileName)
NVAPI_INTERFACE NvAPI_DRS_DestroySession(NvDRSSessionHandle hSession)
NVAPI_INTERFACE NvAPI_GPU_GetScanoutConfigurationEx(__in NvU32 displayId, __inout NV_SCANOUT_INFORMATION *pScanoutInformation)
NVAPI_INTERFACE NvAPI_GPU_GetAllDisplayIds(__in NvPhysicalGpuHandle hPhysicalGpu, __inout_ecount_part_opt(*pDisplayIdCount, *pDisplayIdCount) NV_GPU_DISPLAYIDS *pDisplayIds, __inout NvU32 *pDisplayIdCount)
NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromLogicalGPU(NvLogicalGpuHandle hLogicalGPU, NvPhysicalGpuHandle hPhysicalGPU[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount)
NVAPI_INTERFACE NvAPI_GPU_GetScanoutWarpingState(__in NvU32 displayId, __inout NV_SCANOUT_WARPING_STATE_DATA *scanoutWarpingStateData)
_NV_GPU_CHIP_REVISION
Definition nvapi.h:2828
NVAPI_INTERFACE NvAPI_GPU_GetVirtualFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pSize)
NVAPI_INTERFACE NvAPI_GetLogicalGPUFromDisplay(NvDisplayHandle hNvDisp, NvLogicalGpuHandle *pLogicalGPU)
NVAPI_INTERFACE NvAPI_GPU_SetScanoutWarping(NvU32 displayId, NV_SCANOUT_WARPING_DATA *scanoutWarpingData, int *piMaxNumVertices, int *pbSticky)
NVAPI_INTERFACE NvAPI_GPU_SetScanoutIntensity(NvU32 displayId, NV_SCANOUT_INTENSITY_DATA *scanoutIntensityData, int *pbSticky)
NVAPI_INTERFACE NvAPI_GPU_GetBusType(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_BUS_TYPE *pBusType)
NVAPI_INTERFACE NvAPI_GPU_GetVbiosVersionString(NvPhysicalGpuHandle hPhysicalGpu, NvAPI_ShortString szBiosRevision)
NVAPI_INTERFACE NvAPI_GPU_ValidateOutputCombination(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputsMask)
NVAPI_INTERFACE NvAPI_GPU_GetBoardInfo(NvPhysicalGpuHandle hPhysicalGpu, NV_BOARD_INFO *pBoardInfo)
NVAPI_INTERFACE NvAPI_GPU_GetLogicalGpuInfo(__in NvLogicalGpuHandle hLogicalGpu, __inout NV_LOGICAL_GPU_DATA *pLogicalGpuData)
NVAPI_INTERFACE NvAPI_GetGPUIDfromPhysicalGPU(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pGpuId)
Do not use this function for new software development.
NVAPI_INTERFACE NvAPI_Event_UnregisterCallback(NvEventHandle hClient)
NVAPI_INTERFACE NvAPI_GPU_GetHDCPSupportStatus(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_GET_HDCP_SUPPORT_STATUS *pGetHDCPSupportStatus)
_NV_GPU_BUS_TYPE
Definition nvapi.h:2326
enum _NV_GPU_CONNECTOR_TYPE NV_GPU_CONNECTOR_TYPE
NVAPI_INTERFACE NvAPI_GPU_GetIRQ(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pIRQ)
NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromDisplay(NvDisplayHandle hNvDisp, NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount)
NVAPI_INTERFACE NvAPI_I2CRead(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo)
NVAPI_INTERFACE NvAPI_OGL_ExpertModeDefaultsSet(NvU32 expertDetailLevel, NvU32 expertReportMask, NvU32 expertOutputMask)
_NV_GPU_CONNECTOR_TYPE
Definition nvapi.h:361
_NV_GPU_ARCH_IMPLEMENTATION_ID
NV_GPU_ARCH_INFO() values to identify GPU Architecture Implementation.
Definition nvapi.h:2728
NVAPI_INTERFACE NvAPI_GPU_GetPCIIdentifiers(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pDeviceId, NvU32 *pSubSystemId, NvU32 *pRevisionId, NvU32 *pExtDeviceId)
struct _NV_SCANOUT_INFORMATION NV_SCANOUT_INFORMATION
enum _NV_GPU_OUTPUT_TYPE NV_GPU_OUTPUT_TYPE
NVAPI_INTERFACE NvAPI_GPU_GetEDID(NvPhysicalGpuHandle hPhysicalGpu, NvU32 displayOutputId, NV_EDID *pEDID)
_NV_GPU_TYPE
Definition nvapi.h:2290
enum _NV_GPU_ARCH_IMPLEMENTATION_ID NV_GPU_ARCH_IMPLEMENTATION_ID
NV_GPU_ARCH_INFO() values to identify GPU Architecture Implementation.
enum _NV_GPU_HDCP_KEY_SOURCE_STATE NV_GPU_HDCP_KEY_SOURCE_STATE
HDCP key source states - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
NV_SYSTEM_TYPE
Definition nvapi.h:2107
NVAPI_INTERFACE NvAPI_GPU_GetVbiosOEMRevision(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBiosRevision)
NVAPI_INTERFACE NvAPI_GPU_SetEDID(NvPhysicalGpuHandle hPhysicalGpu, NvU32 displayOutputId, NV_EDID *pEDID)
NVAPI_INTERFACE NvAPI_GPU_GetVRReadyData(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_VR_READY *pGpuVrReadyData)
NVAPI_INTERFACE NvAPI_GPU_GetFullName(NvPhysicalGpuHandle hPhysicalGpu, NvAPI_ShortString szName)
NVAPI_INTERFACE NvAPI_GetPhysicalGPUFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvPhysicalGpuHandle *pPhysicalGpu)
NVAPI_INTERFACE NvAPI_SYS_GetDisplayDriverInfo(__inout NV_DISPLAY_DRIVER_INFO *pDriverInfo)
enum _NV_GPU_HDCP_KEY_SOURCE NV_GPU_HDCP_KEY_SOURCE
HDCP key sources - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
NVAPI_INTERFACE NvAPI_GPU_GetScanoutConfiguration(NvU32 displayId, NvSBox *desktopRect, NvSBox *scanoutRect)
NVAPI_INTERFACE NvAPI_GPU_GetActiveOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask)
_NV_GPU_HDCP_FUSE_STATE
HDCP fuse states - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
Definition nvapi.h:3162
enum _NV_GPU_HDCP_FUSE_STATE NV_GPU_HDCP_FUSE_STATE
HDCP fuse states - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
NVAPI_INTERFACE NvAPI_GPU_GetOutputType(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputId, NV_GPU_OUTPUT_TYPE *pOutputType)
NVAPI_INTERFACE NvAPI_GPU_GetBusId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusId)
NVAPI_INTERFACE NvAPI_GPU_GetCurrentPCIEDownstreamWidth(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pWidth)
NVAPI_INTERFACE NvAPI_GPU_GetGPUInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_INFO *pGpuInfo)
_NV_GPU_ARCHITECTURE_ID
NV_GPU_ARCH_INFO() values to identify Architecture level for the GPU.
Definition nvapi.h:2698
_NV_GPU_HDCP_KEY_SOURCE
HDCP key sources - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
Definition nvapi.h:3171
NVAPI_INTERFACE NvAPI_GPU_QueryWorkstationFeatureSupport(NvPhysicalGpuHandle physicalGpu, NV_GPU_WORKSTATION_FEATURE_TYPE gpuWorkstationFeature)
enum _NV_GPU_BUS_TYPE NV_GPU_BUS_TYPE
NVAPI_INTERFACE NvAPI_Event_RegisterCallback(PNV_EVENT_REGISTER_CALLBACK eventCallback, NvEventHandle *phClient)
NVAPI_INTERFACE NvAPI_GetLogicalGPUFromPhysicalGPU(NvPhysicalGpuHandle hPhysicalGPU, NvLogicalGpuHandle *pLogicalGPU)
NVAPI_INTERFACE NvAPI_GPU_GetVbiosRevision(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBiosRevision)
NVAPI_INTERFACE NvAPI_GPU_GetShaderSubPipeCount(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pCount)
NVAPI_INTERFACE NvAPI_GPU_GetScanoutCompositionParameter(__in NvU32 displayId, __in NV_GPU_SCANOUT_COMPOSITION_PARAMETER parameter, __out NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE *parameterData, __out float *pContainer)
NVAPI_INTERFACE NvAPI_GPU_GetSystemType(NvPhysicalGpuHandle hPhysicalGpu, NV_SYSTEM_TYPE *pSystemType)
NVAPI_INTERFACE NvAPI_GPU_GetGpuCoreCount(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pCount)
NVAPI_INTERFACE NvAPI_GPU_GetPhysicalFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pSize)
NVAPI_INTERFACE NvAPI_GPU_GetArchInfo(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_ARCH_INFO *pGpuArchInfo)
_NV_GPU_WORKSTATION_FEATURE_TYPE
Definition nvapi.h:3601
NVAPI_INTERFACE NvAPI_GPU_SetScanoutCompositionParameter(NvU32 displayId, NV_GPU_SCANOUT_COMPOSITION_PARAMETER parameter, NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE parameterValue, float *pContainer)
_NV_GPU_OUTPUT_TYPE
Definition nvapi.h:2195
NVAPI_INTERFACE NvAPI_GPU_GetVirtualizationInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_VIRTUALIZATION_INFO *pVirtualizationInfo)
NV_I2C_SPEED
Definition nvapi.h:2908
NVAPI_INTERFACE NvAPI_GPU_GetScanoutIntensityState(__in NvU32 displayId, __inout NV_SCANOUT_INTENSITY_STATE_DATA *scanoutIntensityStateData)
NVAPI_INTERFACE NvAPI_EnumTCCPhysicalGPUs(NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount)
_NV_VIRTUALIZATION_MODE
Definition nvapi.h:3974
_NV_GPU_HDCP_KEY_SOURCE_STATE
HDCP key source states - used in NV_GPU_GET_HDCP_SUPPORT_STATUS.
Definition nvapi.h:3183
NVAPI_INTERFACE NvAPI_EnumLogicalGPUs(NvLogicalGpuHandle nvGPUHandle[NVAPI_MAX_LOGICAL_GPUS], NvU32 *pGpuCount)
NVAPI_INTERFACE NvAPI_GPU_WorkstationFeatureQuery(__in NvPhysicalGpuHandle hPhysicalGpu, __out_opt NvU32 *pConfiguredFeatureMask, __out_opt NvU32 *pConsistentFeatureMask)
enum _NV_GPU_TYPE NV_GPU_TYPE
NVAPI_INTERFACE NvAPI_GPU_GetRamBusWidth(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusWidth)
enum _NV_GPU_ARCHITECTURE_ID NV_GPU_ARCHITECTURE_ID
NV_GPU_ARCH_INFO() values to identify Architecture level for the GPU.
NVAPI_INTERFACE NvAPI_GetPhysicalGPUFromGPUID(NvU32 gpuId, NvPhysicalGpuHandle *pPhysicalGPU)
NVAPI_INTERFACE NvAPI_I2CWrite(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo)
NVAPI_INTERFACE NvAPI_GPU_GetConnectedDisplayIds(__in NvPhysicalGpuHandle hPhysicalGpu, __inout_ecount_part_opt(*pDisplayIdCount, *pDisplayIdCount) NV_GPU_DISPLAYIDS *pDisplayIds, __inout NvU32 *pDisplayIdCount, __in NvU32 flags)
NVAPI_INTERFACE NvAPI_GPU_GetBusSlotId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusSlotId)
NVAPI_INTERFACE NvAPI_GPU_GetGPUType(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_TYPE *pGpuType)
@ NV_GPU_CHIP_REV_EMULATION_FPGA
FPGA implementation of the chipset.
Definition nvapi.h:2830
@ NV_GPU_CHIP_REV_UNKNOWN
Unknown chip revision.
Definition nvapi.h:2834
@ NV_GPU_CHIP_REV_A01
First silicon chipset revision.
Definition nvapi.h:2831
@ NV_GPU_CHIP_REV_EMULATION_QT
QT chip.
Definition nvapi.h:2829
@ NV_GPU_CHIP_REV_A02
Second Silicon chipset revision.
Definition nvapi.h:2832
@ NV_GPU_CHIP_REV_A03
Third Silicon chipset revision.
Definition nvapi.h:2833
@ NVAPI_GPU_CONNECTOR_VIRTUAL_WFD
Deprecated.
Definition nvapi.h:388
@ NV_SYSTEM_TYPE_DGPU
Discrete GPU.
Definition nvapi.h:2293
@ NV_SYSTEM_TYPE_IGPU
Integrated GPU.
Definition nvapi.h:2292
@ NV_GPU_WORKSTATION_FEATURE_TYPE_QUADRO_VR_READY
DEPRECATED name - do not use.
Definition nvapi.h:3603
@ NV_GPU_WORKSTATION_FEATURE_TYPE_NVIDIA_RTX_VR_READY
NVIDIA RTX VR Ready.
Definition nvapi.h:3602
@ NVAPI_GPU_OUTPUT_CRT
CRT display device.
Definition nvapi.h:2197
@ NVAPI_GPU_OUTPUT_DFP
Digital Flat Panel display device.
Definition nvapi.h:2198
@ NVAPI_GPU_OUTPUT_TV
TV display device.
Definition nvapi.h:2199
@ NVAPI_I2C_SPEED_DEFAULT
Set i2cSpeedKhz to I2C_SPEED_DEFAULT if default I2C speed is to be chosen, ie.use the current frequen...
Definition nvapi.h:2909
@ NV_VIRTUALIZATION_MODE_VGX
Represents vGPU inside virtual machine.
Definition nvapi.h:3977
@ NV_VIRTUALIZATION_MODE_NMOS
Represents GPU-Passthrough.
Definition nvapi.h:3976
@ NV_VIRTUALIZATION_MODE_NONE
Represents Bare Metal GPU.
Definition nvapi.h:3975
@ NV_VIRTUALIZATION_MODE_HOST_VGPU
Represents VGX hypervisor in vGPU mode.
Definition nvapi.h:3978
NVAPI_INTERFACE NvAPI_GPU_GetAllClockFrequencies(__in NvPhysicalGpuHandle hPhysicalGPU, __inout NV_GPU_CLOCK_FREQUENCIES *pClkFreqs)
NV_GPU_CLOCK_FREQUENCIES_V2 NV_GPU_CLOCK_FREQUENCIES
Definition nvapi.h:5068
NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE
Definition nvapi.h:5043
NVAPI_INTERFACE NvAPI_GPU_ResetECCErrorInfo(NvPhysicalGpuHandle hPhysicalGpu, NvU8 bResetCurrent, NvU8 bResetAggregate)
NVAPI_INTERFACE NvAPI_GPU_SetECCConfiguration(NvPhysicalGpuHandle hPhysicalGpu, NvU8 bEnable, NvU8 bEnableImmediately)
struct _NV_GPU_PERF_PSTATES20_INFO_V2 NV_GPU_PERF_PSTATES20_INFO_V2
Used in NvAPI_GPU_GetPstates20() interface call.
NV_GPU_PERF_PSTATE20_CLOCK_TYPE_ID
Used to identify clock type.
Definition nvapi.h:1134
NVAPI_INTERFACE NvAPI_GPU_GetDynamicPstatesInfoEx(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_DYNAMIC_PSTATES_INFO_EX *pDynamicPstatesInfoEx)
NVAPI_INTERFACE NvAPI_GPU_GetCurrentPstate(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_PERF_PSTATE_ID *pCurrentPstate)
NVAPI_INTERFACE NvAPI_GPU_GetPstates20(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_PERF_PSTATES20_INFO *pPstatesInfo)
@ NVAPI_GPU_PERF_PSTATE20_CLOCK_TYPE_SINGLE
Clock domains that use single frequency value within given pstate.
Definition nvapi.h:1136
@ NVAPI_GPU_PERF_PSTATE20_CLOCK_TYPE_RANGE
Clock domains that allow range of frequency values within given pstate.
Definition nvapi.h:1139
#define NV_MOSAIC_MAX_TOPO_PER_TOPO_GROUP
Definition nvapi.h:9297
struct _NV_MOSAIC_DISPLAY_SETTING_V1 NV_MOSAIC_DISPLAY_SETTING_V1
Basic per-display settings that are used in setting/getting the Mosaic mode.
NVAPI_INTERFACE NvAPI_GetSupportedMosaicTopologies(NV_MOSAIC_SUPPORTED_TOPOLOGIES *pMosaicTopos)
#define NV_MOSAIC_DISPLAY_SETTINGS_MAX
Definition nvapi.h:9246
NVAPI_INTERFACE NvAPI_Mosaic_GetOverlapLimits(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 *pMinOverlapX, NvS32 *pMaxOverlapX, NvS32 *pMinOverlapY, NvS32 *pMaxOverlapY)
NVAPI_INTERFACE NvAPI_Mosaic_EnableCurrentTopo(NvU32 enable)
NVAPI_INTERFACE NvAPI_GetCurrentMosaicTopology(NV_MOSAIC_TOPOLOGY *pMosaicTopo, NvU32 *pEnabled)
NVAPI_INTERFACE NvAPI_Mosaic_ValidateDisplayGrids(__in NvU32 setTopoFlags, __in_ecount(gridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies, __inout_ecount_full(gridCount) NV_MOSAIC_DISPLAY_TOPO_STATUS *pTopoStatus, __in NvU32 gridCount)
NVAPI_INTERFACE NvAPI_Mosaic_EnumDisplayGrids(__inout_ecount_part_opt(*pGridCount, *pGridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies, __inout NvU32 *pGridCount)
NVAPI_INTERFACE NvAPI_Mosaic_GetTopoGroup(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_TOPO_GROUP *pTopoGroup)
#define NVAPI_MAX_MOSAIC_TOPOS
Used in NV_MOSAIC_TOPOLOGY.
Definition nvapi.h:9931
NVAPI_INTERFACE NvAPI_Mosaic_SetDisplayGrids(__in_ecount(gridCount) NV_MOSAIC_GRID_TOPO *pGridTopologies, __in NvU32 gridCount, __in NvU32 setTopoFlags)
NVAPI_INTERFACE NvAPI_Mosaic_SetCurrentTopo(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 overlapX, NvS32 overlapY, NvU32 enable)
NVAPI_INTERFACE NvAPI_SetCurrentMosaicTopology(NV_MOSAIC_TOPOLOGY *pMosaicTopo)
NVAPI_INTERFACE NvAPI_Mosaic_GetSupportedTopoInfo(NV_MOSAIC_SUPPORTED_TOPO_INFO *pSupportedTopoInfo, NV_MOSAIC_TOPO_TYPE type)
NVAPI_INTERFACE NvAPI_Mosaic_GetCurrentTopo(NV_MOSAIC_TOPO_BRIEF *pTopoBrief, NV_MOSAIC_DISPLAY_SETTING *pDisplaySetting, NvS32 *pOverlapX, NvS32 *pOverlapY)
struct _NV_MOSAIC_SUPPORTED_TOPO_INFO_V1 NV_MOSAIC_SUPPORTED_TOPO_INFO_V1
NVAPI_INTERFACE NvAPI_EnableCurrentMosaicTopology(NvU32 enable)
#define NVAPI_MAX_MOSAIC_DISPLAY_ROWS
Used in NV_MOSAIC_TOPOLOGY.
Definition nvapi.h:9069
NV_MOSAIC_TOPO
Definition nvapi.h:9136
#define NVAPI_MAX_MOSAIC_DISPLAY_COLUMNS
Used in NV_MOSAIC_TOPOLOGY.
Definition nvapi.h:9070
NV_MOSAIC_TOPO_TYPE
Definition nvapi.h:9115
@ NV_MOSAIC_TOPO_MAX
Total number of topologies.
Definition nvapi.h:9188
@ NV_MOSAIC_TOPO_TYPE_PASSIVE_STEREO
Passive Stereo topologies.
Definition nvapi.h:9118
@ NV_MOSAIC_TOPO_TYPE_ALL
All mosaic topologies.
Definition nvapi.h:9116
@ NV_MOSAIC_TOPO_TYPE_BASIC
Basic Mosaic topologies.
Definition nvapi.h:9117
@ NV_MOSAIC_TOPO_TYPE_PASSIVE_STEREO_SCALED_CLONE
Not supported at this time.
Definition nvapi.h:9120
@ NV_MOSAIC_TOPO_TYPE_SCALED_CLONE
Not supported at this time.
Definition nvapi.h:9119
@ NV_MOSAIC_TOPO_TYPE_MAX
Always leave this at end of the enum.
Definition nvapi.h:9121
void * StereoHandle
A stereo handle, that corresponds to the device interface.
Definition nvapi_lite_common.h:146
void(* NVAPI_OGLEXPERT_CALLBACK)(unsigned int categoryId, unsigned int messageId, unsigned int detailLevel, int objectId, const char *messageStr)
Definition nvapi.h:1488
_NVAPI_GSYNC_DISPLAY_SYNC_STATE
Display sync states. Used in NV_GSYNC_DISPLAY.
Definition nvapi.h:10194
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_COLOR_FIXED NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_COLOR_FIXED
struct _NV_GSYNC_DELAY NV_GSYNC_DELAY
Used in NV_GSYNC_CONTROL_PARAMS.
NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesSetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS *pClientIllumDevicesControl)
struct _NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_GPIO_PWM_SINGLE_COLOR NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_GPIO_PWM_SINGLE_COLOR
_NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR
Connector values for a GPU. Used in NV_GSYNC_GPU.
Definition nvapi.h:10184
struct _NV_GSYNC_CONTROL_PARAMS_V1 NV_GSYNC_CONTROL_PARAMS_V1
Used in NvAPI_GSync_GetControlParameters() and NvAPI_GSync_SetControlParameters().
#define NV_LICENSE_INFO_MAX_LENGTH
Length for Grid License.
Definition nvapi.h:4076
struct _NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_MCUV10 NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_MCUV10
NV_INFOFRAME_PROPERTY_MODE
Definition nvapi.h:6759
_NVAPI_GSYNC_RJ45_IO
Used in NV_GSYNC_STATUS_PARAMS.
Definition nvapi.h:10512
NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesGetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_CONTROL_PARAMS *pClientIllumDevicesControl)
struct _NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_GPIO_PWM_RGBW NV_GPU_CLIENT_ILLUM_DEVICE_INFO_DATA_GPIO_PWM_RGBW
struct _NV_GSYNC_STATUS_PARAMS_V1 NV_GSYNC_STATUS_PARAMS_V1
NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELCOUNT
Byte 1 related.
Definition nvapi.h:6976
NVAPI_INTERFACE NvAPI_Mosaic_EnumDisplayModes(__in NV_MOSAIC_GRID_TOPO *pGridTopology, __inout_ecount_part_opt(*pDisplayCount, *pDisplayCount) NV_MOSAIC_DISPLAY_SETTING *pDisplaySettings, __inout NvU32 *pDisplayCount)
NV_HDR_MODE
Definition nvapi.h:7625
char NvAPI_LicenseString[NV_LICENSE_INFO_MAX_LENGTH]
License string.
Definition nvapi.h:4079
NVAPI_INTERFACE NvAPI_Disp_GetHdrToneMapping(__in NvU32 displayId, __inout NV_HDR_TONEMAPPING_METHOD *pHdrTonemapping)
NV_INFOFRAME_FIELD_VALUE_AVI_NONUNIFORMPICTURESCALING
Byte 3 related.
Definition nvapi.h:6870
_NV_ECC_CONFIGURATION
Definition nvapi.h:3360
NV_INFOFRAME_FIELD_VALUE_AUDIO_CODINGEXTENSIONTYPE
Byte 3 related.
Definition nvapi.h:7036
NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesSetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS *pIllumZonesControl)
#define NV_LICENSE_SIGNATURE_SIZE
Signature length for GRID License.
Definition nvapi.h:4073
NVAPI_INTERFACE NvAPI_GPU_GetThermalSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 sensorIndex, NV_GPU_THERMAL_SETTINGS *pThermalSettings)
NV_INFOFRAME_FIELD_VALUE_AVI_SCANINFO
Byte1 related.
Definition nvapi.h:6785
_NV_COLOR_SELECTION_POLICY
Definition nvapi.h:7312
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW_PARAMS NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW_PARAMS
struct _NV_LICENSABLE_FEATURES_V1 NV_LICENSABLE_FEATURES_V1
Licensable features.
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB
NVAPI_INTERFACE NvAPI_GPU_ClientIllumDevicesGetInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_DEVICE_INFO_PARAMS *pIllumDevicesInfo)
_NV_LICENSE_FEATURE_TYPE
Used in NV_LICENSE_FEATURE_DETAILS.
Definition nvapi.h:4083
enum _NVAPI_GSYNC_DISPLAY_SYNC_STATE NVAPI_GSYNC_DISPLAY_SYNC_STATE
Display sync states. Used in NV_GSYNC_DISPLAY.
void(__cdecl * NVAPI_CALLBACK_QSYNCEVENT)(NV_QSYNC_EVENT_DATA qyncEventData, void *callbackParam)
Callback for QSYNC event.
Definition nvapi.h:3572
enum _NVAPI_GPU_PERF_DECREASE NVAPI_GPU_PERF_DECREASE
NVAPI_INTERFACE NvAPI_GSync_GetTopology(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout_opt NvU32 *gsyncGpuCount, __inout_ecount_part_opt(*gsyncGpuCount, *gsyncGpuCount) NV_GSYNC_GPU *gsyncGPUs, __inout_opt NvU32 *gsyncDisplayCount, __inout_ecount_part_opt(*gsyncDisplayCount, *gsyncDisplayCount) NV_GSYNC_DISPLAY *gsyncDisplays)
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB_PARAMS NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB_PARAMS
enum _NVAPI_GSYNC_DELAY_TYPE NVAPI_GSYNC_DELAY_TYPE
Used in NvAPI_GSync_AdjustSyncDelay()
NV_INFOFRAME_FIELD_VALUE_AUDIO_SAMPLESIZE
Byte 2 related.
Definition nvapi.h:7011
NVAPI_INTERFACE NvAPI_GPU_NVLINK_GetStatus(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NVLINK_GET_STATUS *statusParams)
_NVAPI_GSYNC_POLARITY
Definition nvapi.h:10298
NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_TYPE
Definition nvapi.h:5372
NVAPI_INTERFACE NvAPI_GSync_AdjustSyncDelay(__in NvGSyncDeviceHandle hNvGSyncDevice, __in NVAPI_GSYNC_DELAY_TYPE delayType, __inout NV_GSYNC_DELAY *pGsyncDelay, __out_opt NvU32 *syncSteps)
NVAPI_INTERFACE NvAPI_GPU_GetPerfDecreaseInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NvU32 *pPerfDecrInfo)
NVAPI_INTERFACE NvAPI_GSync_SetSyncStateSettings(__in NvU32 gsyncDisplayCount, __in_ecount(gsyncDisplayCount) NV_GSYNC_DISPLAY *pGsyncDisplays, __in NvU32 flags)
NVAPI_INTERFACE NvAPI_GPU_GetTachReading(NvPhysicalGpuHandle hPhysicalGPU, NvU32 *pValue)
NVAPI_INTERFACE NvAPI_GPU_GetLicensableFeatures(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_LICENSABLE_FEATURES *pLicensableFeatures)
struct _NV_GSYNC_STATUS NV_GSYNC_STATUS
Used in NvAPI_GSync_GetSyncStatus().
NVAPI_INTERFACE NvAPI_OGL_ExpertModeSet(NvU32 expertDetailLevel, NvU32 expertReportMask, NvU32 expertOutputMask, NVAPI_OGLEXPERT_CALLBACK expertCallback)
struct _NV_MONITOR_CAPABILITIES_V1 NV_MONITOR_CAPABILITIES_V1
See NvAPI_DISP_GetMonitorCapabilities().
enum _NV_LICENSE_FEATURE_TYPE NV_LICENSE_FEATURE_TYPE
Used in NV_LICENSE_FEATURE_DETAILS.
NV_INFOFRAME_PROPERTY_BLACKLIST
Returns whether the current monitor is in blacklist or force this monitor to be in blacklist.
Definition nvapi.h:6769
NV_MONITOR_CAPS_TYPE
HDMI-related and extended CAPs.
Definition nvapi.h:8034
struct _NV_MONITOR_CAPS_VSDB NV_MONITOR_CAPS_VSDB
See NvAPI_DISP_GetMonitorCapabilities().
enum _NVAPI_GSYNC_RJ45_IO NVAPI_GSYNC_RJ45_IO
Used in NV_GSYNC_STATUS_PARAMS.
NVAPI_INTERFACE NvAPI_GSync_GetStatusParameters(NvGSyncDeviceHandle hNvGSyncDevice, NV_GSYNC_STATUS_PARAMS *pStatusParams)
struct _NV_GPU_CLIENT_ILLUM_ZONE_INFO_DATA_SINGLE_COLOR NV_GPU_CLIENT_ILLUM_ZONE_INFO_DATA_SINGLE_COLOR
NVAPI_INTERFACE NvAPI_Disp_SetOutputMode(__in NvU32 displayId, __inout NV_DISPLAY_OUTPUT_MODE *pDisplayMode)
enum _NVAPI_GSYNC_SYNC_SOURCE NVAPI_GSYNC_SYNC_SOURCE
Used in NV_GSYNC_CONTROL_PARAMS.
_NV_PIXEL_SHIFT_TYPE
Definition nvapi.h:9603
_NVAPI_GSYNC_DELAY_TYPE
Used in NvAPI_GSync_AdjustSyncDelay()
Definition nvapi.h:10437
NVAPI_INTERFACE NvAPI_EnumNvidiaDisplayHandle(NvU32 thisEnum, NvDisplayHandle *pNvDispHandle)
NVAPI_INTERFACE NvAPI_DISP_GetAssociatedUnAttachedNvidiaDisplayHandle(const char *szDisplayName, NvUnAttachedDisplayHandle *pNvUnAttachedDispHandle)
NV_EVENT_TYPE
Enum for Event IDs.
Definition nvapi.h:3577
NV_INFOFRAME_FIELD_VALUE_AVI_PIXELREPETITION
Byte 4 related.
Definition nvapi.h:6909
struct _NV_GSYNC_CAPABILITIES_V1 NV_GSYNC_CAPABILITIES_V1
Used in NvAPI_GSync_QueryCapabilities().
NVAPI_INTERFACE NvAPI_Disp_SetSourceHdrMetadata(__in NvU32 displayId, __in NV_HDR_METADATA *pMetadata)
NV_GPU_CLIENT_ILLUM_DEVICE_TYPE
Definition nvapi.h:5344
struct _NV_LICENSE_FEATURE_DETAILS_V1 NV_LICENSE_FEATURE_DETAILS_V1
Used in NV_LICENSABLE_FEATURES.
NV_GPU_CLIENT_ILLUM_ZONE_LOCATION
Definition nvapi.h:5332
enum _NVAPI_GSYNC_POLARITY NVAPI_GSYNC_POLARITY
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED
NV_HDR_CMD
Definition nvapi.h:7619
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_SINGLE_COLOR NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_SINGLE_COLOR
struct _NV_LICENSE_EXPIRY_DETAILS NV_LICENSE_EXPIRY_DETAILS
NVAPI_INTERFACE NvAPI_GSync_GetControlParameters(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CONTROL_PARAMS *pGsyncControls)
NV_INFOFRAME_FIELD_VALUE_AUDIO_CHANNELALLOCATION
Byte 4 related.
Definition nvapi.h:7075
NV_GPU_SCANOUT_COMPOSITION_PARAMETER_VALUE
Definition nvapi.h:3815
NVAPI_INTERFACE NvAPI_GPU_NVLINK_GetCaps(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NVLINK_GET_CAPS *capsParams)
struct _NV_GPU_CLIENT_ILLUM_ZONE_INFO_DATA_RGBW NV_GPU_CLIENT_ILLUM_ZONE_INFO_DATA_RGBW
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR_PARAMS NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR_PARAMS
_NV_COLORSPACE_TYPE
Definition nvapi.h:7736
NV_COLOR_FORMAT
See Table 14 of CEA-861E. Not all of this is supported by the GPU.
Definition nvapi.h:7263
enum _NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR
Connector values for a GPU. Used in NV_GSYNC_GPU.
NVAPI_INTERFACE NvAPI_Disp_GetOutputMode(__in NvU32 displayId, __inout NV_DISPLAY_OUTPUT_MODE *pDisplayMode)
NVAPI_INTERFACE NvAPI_Disp_SetHdrToneMapping(__in NvU32 displayId, __in NV_HDR_TONEMAPPING_METHOD hdrTonemapping)
NV_THERMAL_TARGET
Definition nvapi.h:4906
NV_THERMAL_CONTROLLER
Definition nvapi.h:4923
_NVAPI_GSYNC_SYNC_SOURCE
Used in NV_GSYNC_CONTROL_PARAMS.
Definition nvapi.h:10316
NV_INFOFRAME_FIELD_VALUE_AVI_ASPECTRATIOACTIVEPORTION
Byte2 related.
Definition nvapi.h:6829
_NVAPI_GSYNC_MULTIPLY_DIVIDE_MODE
Used in NV_GSYNC_CONTROL_PARAMS.
Definition nvapi.h:10351
NV_GPU_CLIENT_ILLUM_ZONE_TYPE
Definition nvapi.h:5355
_NVAPI_GPU_PERF_DECREASE
Definition nvapi.h:4599
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGB NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGB
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_RGBW NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_RGBW
enum _NVAPI_GSYNC_VIDEO_MODE NVAPI_GSYNC_VIDEO_MODE
Used in NV_GSYNC_CONTROL_PARAMS.
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_SINGLE_COLOR NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_SINGLE_COLOR
NVAPI_INTERFACE NvAPI_GSync_GetSyncStatus(__in NvGSyncDeviceHandle hNvGSyncDevice, __in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GSYNC_STATUS *status)
enum _NVAPI_GSYNC_MULTIPLY_DIVIDE_MODE NVAPI_GSYNC_MULTIPLY_DIVIDE_MODE
Used in NV_GSYNC_CONTROL_PARAMS.
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_COLOR_FIXED NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_COLOR_FIXED
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_RGB NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR_RGB
NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesGetControl(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_PARAMS *pIllumZonesControl)
NVAPI_INTERFACE NvAPI_GSync_QueryCapabilities(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CAPABILITIES *pNvGSyncCapabilities)
NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayHandle(const char *szDisplayName, NvDisplayHandle *pNvDispHandle)
#define NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS
Definition nvapi.h:5366
NVAPI_INTERFACE NvAPI_Disp_ColorControl(NvU32 displayId, NV_COLOR_DATA *pColorData)
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED_PARAMS NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED_PARAMS
NV_STATIC_METADATA_DESCRIPTOR_ID
Definition nvapi.h:7415
_NVAPI_GSYNC_VIDEO_MODE
Used in NV_GSYNC_CONTROL_PARAMS.
Definition nvapi.h:10306
NVAPI_INTERFACE NvAPI_DISP_GetEdidData(__in NvU32 displayId, __inout NV_EDID_DATA *pEdidParams, __inout NV_EDID_FLAG *pFlag)
NVAPI_INTERFACE NvAPI_EnumNvidiaUnAttachedDisplayHandle(NvU32 thisEnum, NvUnAttachedDisplayHandle *pNvUnAttachedDispHandle)
NV_INFOFRAME_FIELD_VALUE_AUDIO_LFEPLAYBACKLEVEL
Byte 5 related.
Definition nvapi.h:7132
#define NV_LICENSE_MAX_COUNT
Maximum number of supported Feature License.
Definition nvapi.h:4070
NV_GPU_CLIENT_ILLUM_CTRL_MODE
Definition nvapi.h:5313
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_PIECEWISE_LINEAR
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGBW NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGBW
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR
NVAPI_INTERFACE NvAPI_GSync_SetControlParameters(__in NvGSyncDeviceHandle hNvGSyncDevice, __inout NV_GSYNC_CONTROL_PARAMS *pGsyncControls)
NVAPI_INTERFACE NvAPI_GSync_EnumSyncDevices(__out NvGSyncDeviceHandle nvGSyncHandles[NVAPI_MAX_GSYNC_DEVICES], __out NvU32 *gsyncCount)
NVAPI_INTERFACE NvAPI_GPU_ClientIllumZonesGetInfo(__in NvPhysicalGpuHandle hPhysicalGpu, __inout NV_GPU_CLIENT_ILLUM_ZONE_INFO_PARAMS *pIllumZonesInfo)
struct _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW
@ NV_INFOFRAME_PROPERTY_MODE_ALLOW_OVERRIDE
Driver only sends infoframe when client requests it via infoframe escape call.
Definition nvapi.h:6763
@ NV_INFOFRAME_PROPERTY_MODE_DISABLE
Driver never sends infoframe.
Definition nvapi.h:6762
@ NV_INFOFRAME_PROPERTY_MODE_AUTO
Driver determines whether to send infoframes.
Definition nvapi.h:6760
@ NV_INFOFRAME_PROPERTY_MODE_ENABLE
Driver always sends infoframe.
Definition nvapi.h:6761
@ NVAPI_GSYNC_RJ45_UNUSED
This field is used to notify that the framelock is not actually present.
Definition nvapi.h:10515
@ NV_HDR_MODE_UHDA_NB
Do not use! Internal test mode only, to be removed. Source: CCCS (a.k.a FP16 scRGB) Output : notebook...
Definition nvapi.h:7637
@ NV_HDR_MODE_OFF
Turn off HDR.
Definition nvapi.h:7627
@ NV_HDR_MODE_EDR
Do not use! Internal test mode only, to be removed. Source: CCCS (a.k.a FP16 scRGB) Output : EDR (Ext...
Definition nvapi.h:7635
@ NV_HDR_MODE_DOLBY_VISION
Experimental mode only, not for production! Source: RGB8 Dolby Vision encoded (12 bpc YCbCr422 packed...
Definition nvapi.h:7632
@ NV_HDR_MODE_UHDBD
Do not use! Obsolete, to be removed. NV_HDR_MODE_UHDBD == NV_HDR_MODE_UHDA, reflects obsolete pre-UHD...
Definition nvapi.h:7638
@ NV_HDR_MODE_UHDA_PASSTHROUGH
Experimental mode only, not for production! Source: HDR10 RGB 10bpc Output: HDR10 RGB 10 bpc - signal...
Definition nvapi.h:7631
@ NV_HDR_MODE_UHDA
Source: CCCS [a.k.a FP16 scRGB, linear, sRGB primaries, [-65504,0, 65504] range, RGB(1,...
Definition nvapi.h:7628
@ NV_HDR_MODE_SDR
Do not use! Internal test mode only, to be removed. Source: any Output: SDR (Standard Dynamic Range),...
Definition nvapi.h:7636
@ NV_ECC_CONFIGURATION_DEFERRED
Changes require a POST to take effect.
Definition nvapi.h:3362
@ NV_ECC_CONFIGURATION_IMMEDIATE
Changes can optionally be made to take effect immediately.
Definition nvapi.h:3363
@ NV_COLOR_SELECTION_POLICY_BEST_QUALITY
driver/ OS make decision to select the best color format
Definition nvapi.h:7314
@ NV_COLOR_SELECTION_POLICY_USER
app/nvcpl make decision to select the desire color format
Definition nvapi.h:7313
@ NV_LICENSE_FEATURE_QUADRO
DEPRECATED name - do not use.
Definition nvapi.h:4087
@ NV_PIXEL_SHIFT_TYPE_NO_PIXEL_SHIFT
No pixel shift will be applied to this display.
Definition nvapi.h:9604
@ NV_PIXEL_SHIFT_TYPE_2x2_TOP_RIGHT_PIXELS
This display will be used to scanout top right pixels in 2x2 PixelShift configuration.
Definition nvapi.h:9607
@ NV_PIXEL_SHIFT_TYPE_2x2_BOTTOM_RIGHT_PIXELS
This display will be used to scanout bottom right pixels in 2x2 PixelShift configuration.
Definition nvapi.h:9606
@ NV_PIXEL_SHIFT_TYPE_2x2_BOTTOM_LEFT_PIXELS
This display will be used to scanout bottom left pixels in 2x2 PixelShift configuration.
Definition nvapi.h:9608
@ NV_PIXEL_SHIFT_TYPE_2x2_TOP_LEFT_PIXELS
This display will be used to scanout top left pixels in 2x2 PixelShift configuration.
Definition nvapi.h:9605
@ NV_HDR_CMD_SET
Set HDR output configuration.
Definition nvapi.h:7621
@ NV_HDR_CMD_GET
Get current HDR output configuration.
Definition nvapi.h:7620
@ NV_COLORSPACE_xRGB
FP16 linear with sRGB color primaries == DXGI_COLOR_SPACE_RGB_FULL_G10_NONE_P709.
Definition nvapi.h:7738
@ NV_COLORSPACE_sRGB
sRGB IEC 61966-2-1:1999 == DXGI_COLOR_SPACE_RGB_FULL_G22_NONE_P709
Definition nvapi.h:7737
@ NV_COLORSPACE_REC2100
ITU-R Rec BT.2100 (HDR10) == DXGI_COLOR_SPACE_RGB_FULL_G2084_NONE_P2020.
Definition nvapi.h:7739
@ NVAPI_THERMAL_TARGET_POWER_SUPPLY
GPU power supply temperature requires NvPhysicalGpuHandle.
Definition nvapi.h:4910
@ NVAPI_THERMAL_TARGET_VCD_INLET
Visual Computing Device Inlet temperature requires NvVisualComputingDeviceHandle.
Definition nvapi.h:4913
@ NVAPI_THERMAL_TARGET_MEMORY
GPU memory temperature requires NvPhysicalGpuHandle.
Definition nvapi.h:4909
@ NVAPI_THERMAL_TARGET_VCD_BOARD
Visual Computing Device Board temperature requires NvVisualComputingDeviceHandle.
Definition nvapi.h:4912
@ NVAPI_THERMAL_TARGET_GPU
GPU core temperature requires NvPhysicalGpuHandle.
Definition nvapi.h:4908
@ NVAPI_THERMAL_TARGET_BOARD
GPU board ambient temperature requires NvPhysicalGpuHandle.
Definition nvapi.h:4911
@ NVAPI_THERMAL_TARGET_VCD_OUTLET
Visual Computing Device Outlet temperature requires NvVisualComputingDeviceHandle.
Definition nvapi.h:4914
@ NV_GPU_PERF_DECREASE_REASON_POWER_CONTROL
Power capping / pstate cap.
Definition nvapi.h:4602
@ NV_GPU_PERF_DECREASE_REASON_API_TRIGGERED
API triggered slowdown.
Definition nvapi.h:4604
@ NV_GPU_PERF_DECREASE_REASON_THERMAL_PROTECTION
Thermal slowdown/shutdown/POR thermal protection.
Definition nvapi.h:4601
@ NV_GPU_PERF_DECREASE_REASON_UNKNOWN
Unknown reason.
Definition nvapi.h:4606
@ NV_GPU_PERF_DECREASE_REASON_INSUFFICIENT_POWER
Power connector missing.
Definition nvapi.h:4605
@ NV_GPU_PERF_DECREASE_REASON_AC_BATT
AC->BATT event.
Definition nvapi.h:4603
@ NV_GPU_PERF_DECREASE_NONE
No Slowdown detected.
Definition nvapi.h:4600
@ NV_STATIC_METADATA_TYPE_1
Tells the type of structure used to define the Static Metadata Descriptor block.
Definition nvapi.h:7416
NVAPI_INTERFACE NvAPI_Stereo_SetNotificationMessage(StereoHandle hStereoHandle, NvU64 hWnd, NvU64 messageID)
_NVAPI_STEREO_INIT_ACTIVATION_FLAGS
InitActivation Flags.
Definition nvapi.h:21534
NVAPI_INTERFACE NvAPI_Stereo_IncreaseSeparation(StereoHandle stereoHandle)
NVAPI_INTERFACE NvAPI_Stereo_DecreaseSeparation(StereoHandle stereoHandle)
NVAPI_INTERFACE NvAPI_Stereo_DeleteConfigurationProfileRegistryKey(NV_STEREO_REGISTRY_PROFILE_TYPE registryProfileType)
NVAPI_INTERFACE NvAPI_Stereo_IncreaseConvergence(StereoHandle stereoHandle)
NVAPI_INTERFACE NvAPI_Stereo_SetFrustumAdjustMode(StereoHandle stereoHandle, NV_FRUSTUM_ADJUST_MODE newFrustumAdjustModeValue)
enum _NV_StereoRegistryID NV_STEREO_REGISTRY_ID
NVAPI_INTERFACE NvAPI_Stereo_GetStereoSupport(__in NvMonitorHandle hMonitor, __out NVAPI_STEREO_CAPS *pCaps)
NVAPI_INTERFACE NvAPI_Stereo_CaptureJpegImage(StereoHandle stereoHandle, NvU32 quality)
_NV_FrustumAdjustMode
Definition nvapi.h:21432
_NV_StereoRegistryProfileType
Definition nvapi.h:21112
NVAPI_INTERFACE NvAPI_Stereo_Trigger_Activation(__in StereoHandle hStereoHandle)
NVAPI_INTERFACE NvAPI_Stereo_DecreaseConvergence(StereoHandle stereoHandle)
enum _NV_StereoRegistryProfileType NV_STEREO_REGISTRY_PROFILE_TYPE
NVAPI_INTERFACE NvAPI_Stereo_CapturePngImage(StereoHandle stereoHandle)
_NV_StereoRegistryID
Definition nvapi.h:21196
enum _NVAPI_STEREO_INIT_ACTIVATION_FLAGS NVAPI_STEREO_INIT_ACTIVATION_FLAGS
InitActivation Flags.
NVAPI_INTERFACE NvAPI_Stereo_ReverseStereoBlitControl(StereoHandle hStereoHandle, NvU8 TurnOn)
enum _NV_FrustumAdjustMode NV_FRUSTUM_ADJUST_MODE
NVAPI_INTERFACE NvAPI_Stereo_DeleteConfigurationProfileValue(NV_STEREO_REGISTRY_PROFILE_TYPE registryProfileType, NV_STEREO_REGISTRY_ID valueRegistryID)
@ NVAPI_FRUSTUM_STRETCH
Stretch images in X.
Definition nvapi.h:21434
@ NVAPI_NO_FRUSTUM_ADJUST
Do not adjust frustum.
Definition nvapi.h:21433
@ NVAPI_FRUSTUM_CLEAR_EDGES
Clear corresponding edges for each eye.
Definition nvapi.h:21435
@ NVAPI_STEREO_DEFAULT_REGISTRY_PROFILE
Default registry configuration profile.
Definition nvapi.h:21113
@ NVAPI_STEREO_DX10_REGISTRY_PROFILE
Separate registry configuration profile for a DirectX 10 executable.
Definition nvapi.h:21115
@ NVAPI_STEREO_DX9_REGISTRY_PROFILE
Separate registry configuration profile for a DirectX 9 executable.
Definition nvapi.h:21114
@ NVAPI_FRUSTUM_ADJUST_MODE_ID
Symbolic constant for frustum adjust mode registry ID.
Definition nvapi.h:21198
@ NVAPI_CONVERGENCE_ID
Symbolic constant for convergence registry ID.
Definition nvapi.h:21197
NVAPI_INTERFACE NvAPI_SYS_GetDisplayIdFromGpuAndOutputId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputId, NvU32 *displayId)
NVAPI_INTERFACE NvAPI_SYS_GetLidAndDockInfo(NV_LID_DOCK_PARAMS *pLidAndDock)
NVAPI_INTERFACE NvAPI_SYS_GetChipSetInfo(NV_CHIPSET_INFO *pChipSetInfo)
NVAPI_INTERFACE NvAPI_SYS_GetPhysicalGpuFromDisplayId(NvU32 displayId, NvPhysicalGpuHandle *hPhysicalGpu)
NVAPI_INTERFACE NvAPI_SYS_GetGpuAndOutputIdFromDisplayId(NvU32 displayId, NvPhysicalGpuHandle *hPhysicalGpu, NvU32 *outputId)
_NVVIOCOMPSYNCTYPE
Composite synchronization type.
Definition nvapi.h:19819
NV_DP_COLORIMETRY colorimetry
Ignored in RGB space.
Definition nvapi.h:6636
NVVIOCOLORCONVERSION colorConversion
Color conversion.
Definition nvapi.h:20420
enum _NVVIOVIDEOTYPE NVVIOVIDEOTYPE
HD or SD video type.
NvU32 capsTbl
This is bit field for getting different global caps.The individual bitfields are specified by NVAPI_N...
Definition nvapi.h:4420
NvAPI_LicenseString licenseInfo
Deprecated.
Definition nvapi.h:4119
float yRatio
Vertical scaling ratio.
Definition nvapi.h:8210
NvU32 version
(IN) Structure version
Definition nvapi.h:19449
NvU16 max_content_light_level
Maximum Content Light level (MaxCLL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7666
NvU32 bInternalSlave
Definition nvapi.h:10539
NvU32 connectorType
Out: VGA, TV, DVI, HDMI, DP.
Definition nvapi.h:8117
NVAPI_GSYNC_SYNC_SOURCE source
VSync/House sync.
Definition nvapi.h:10340
NvU32 isMonYCbCr444Capable
If YCbCr 4:4:4 is supported.
Definition nvapi.h:6673
NVVIOLINKID linkID
Link ID.
Definition nvapi.h:20037
NvU32 driverVersion
Contains the driver version after successful return.
Definition nvapi.h:22889
NvS32 overlapY
(+overlap, -gap)
Definition nvapi.h:9617
NV_TIMING_OVERRIDE timingOverride
Ignored if timingOverride == NV_TIMING_OVERRIDE_CURRENT.
Definition nvapi.h:936
NvU32 isDp
If the monitor is driven by a DisplayPort.
Definition nvapi.h:6539
NvU32 isOSVisible
if bit is set, then this display is reported to the OS
Definition nvapi.h:1935
NvU32 numBaseVoltages
Number of populated base voltages (per pstate)
Definition nvapi.h:1234
NvU32 reserved
Must be 0.
Definition nvapi.h:991
NVVIOINPUTCONFIG inConfig
Input device configuration.
Definition nvapi.h:20479
NvU32 version
[in] structure version
Definition nvapi.h:8591
NVVIOSYNCSOURCE syncSource
Sync source.
Definition nvapi.h:20394
NvU32 capFlags
Capabilities of the Sync board. Reserved for future use.
Definition nvapi.h:10126
NvU32 version
structure version
Definition nvapi.h:4959
NvU32 expansionEnable
Enable/disable 4:2:2->4:4:4 expansion.
Definition nvapi.h:20449
NvU32 version
Structure version.
Definition nvapi.h:20474
NvU32 verticalDelay
Vertical delay in lines.
Definition nvapi.h:20112
NVDRS_BINARY_SETTING binaryCurrentValue
Definition nvapi.h:21906
NvU8 rsvd[64]
Definition nvapi.h:6046
NvU32 cbSize
The size of the data buffer, pbData, to be read or written.
Definition nvapi.h:2975
NvU32 version
IN - Structure version.
Definition nvapi.h:4174
NvU32 dataIntegrityCheckFailed
Data integrity check status failed.
Definition nvapi.h:20061
NvU32 version
Version of this structure.
Definition nvapi.h:5278
NvU32 posx
(IN/OUT) X-offset of this display on the Windows desktop
Definition nvapi.h:809
NvU8 reserved13
Byte 10.
Definition nvapi.h:8091
void * pOSAdapterID
Definition nvapi.h:1026
NvU32 implementation
implementation and implementation_id are the same. The former is NvU32 while the latter is an enum ma...
Definition nvapi.h:2850
NvU32 isYCrCb444Supported
If YCrCb444 is supported.
Definition nvapi.h:6549
NvU32 uSyncSourceLocked
genlocked to framelocked to ref signal
Definition nvapi.h:20062
NV_GPU_PSTATE20_BASE_VOLTAGE_ENTRY_V1 baseVoltages[NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES]
Definition nvapi.h:1297
NvU32 bpp
Bits per pixel.
Definition nvapi.h:9229
NvU32 displayId
Display ID.
Definition nvapi.h:954
NV_GPU_CONNECTOR_TYPE connector
(IN) Specify connector type. For TV only.
Definition nvapi.h:788
NvAPI_ShortString szBuildBaseBranch
(OUT) Contains the driver base branch string after successful return.
Definition nvapi.h:22924
NvU32 topoBriefsCount
Number of topologies in below array.
Definition nvapi.h:9256
NvS32 value
Value of parameter delta (in respective units [kHz, uV])
Definition nvapi.h:1146
NV_GPU_PERF_PSTATE_ID pstateId
ID of the P-State.
Definition nvapi.h:1241
NvU16 displayWhitePoint_y
y coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7544
NV_DP_LINK_RATE curLinkRate
Current link rate.
Definition nvapi.h:6533
NvU32 enableDataIntegrityCheck
Enable data integrity check: true - enable, false - disable.
Definition nvapi.h:20401
NvU8 phyVersion
This field specifies the version of PHY being used by the link.
Definition nvapi.h:4450
struct _NVVIOOUTPUTSTATUS NVVIOOUTPUTSTATUS
Output device status.
NvU32 count
Number of topos in array below.
Definition nvapi.h:9321
#define NVAPI_MAX_VIO_JACKS
4 physical jacks supported on each SDI input card.
Definition nvapi.h:19865
NVVIOCOLORSPACE colorSpace
Color space.
Definition nvapi.h:20036
NvAPI_ShortString szBuildBranch
Contains the driver-branch string after successful return.
Definition nvapi.h:22890
NvU32 cloneGroup
Reserved, must be 0.
Definition nvapi.h:9599
NVDRS_BINARY_SETTING binaryPredefinedValue
Definition nvapi.h:21898
NvU32 height
Source surface(source mode) height.
Definition nvapi.h:8203
NVVIOINTERLACEMODE interlaceMode
Interlace mode.
Definition nvapi.h:20125
NvU32 version
Structure version.
Definition nvapi.h:4856
NVVIOSYNCDELAY syncDelay
Sync delay.
Definition nvapi.h:20367
NV_DP_LINK_RATE maxLinkRate
Maximum supported link rate.
Definition nvapi.h:6531
NvU32 version
(IN) Structure version
Definition nvapi.h:17660
NV_I2C_SPEED i2cSpeedKhz
The target speed of the transaction in (kHz) (Chosen from the enum NV_I2C_SPEED).
Definition nvapi.h:2956
NvU8 currentlyCapableOfVRR
monitor currently supports VRR on applied display settings. Valid for NV_MONITOR_CAPS_TYPE_GENERIC on...
Definition nvapi.h:8107
NV_EVENT_TYPE eventId
ID of the event being sent.
Definition nvapi.h:3586
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7438
NvAPI_UnicodeString userFriendlyName
UserFriendly name of the Application.
Definition nvapi.h:21958
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7537
NvU32 HBdeviceId
Host bridge device identification.
Definition nvapi.h:22697
NvU32 bForceModeSet
(IN) Used only on Win7 and higher during a call to NvAPI_SetView(). Turns off optimization & forces O...
Definition nvapi.h:730
NV_MOSAIC_GRID_TOPO_DISPLAY_V1 displays[NV_MOSAIC_MAX_DISPLAYS]
Displays are done as [(row * columns) + column].
Definition nvapi.h:9641
NvU32 bIsSynced
Is timing in sync?
Definition nvapi.h:10472
NvU32 columns
Number of columns.
Definition nvapi.h:9649
NV_BPC hdrBpc
Definition nvapi.h:7701
NV_GPU_PERF_PSTATE_ID pstateId
ID of the p-state.
Definition nvapi.h:4641
NvU32 enabled
1 if topo is enabled, else 0
Definition nvapi.h:9204
NvU16 cc_red_y
Red primary chromaticity coordinate y.
Definition nvapi.h:7504
NvU16 target_max_luminance
Represents max luminance level of sink.
Definition nvapi.h:7502
struct _NVVIOSYNCDELAY NVVIOSYNCDELAY
Sync delay.
NvU32 width
Per-display width.
Definition nvapi.h:9218
NvU32 version
Version of this structure. Must always be first element in this structure.
Definition nvapi.h:4271
NvU32 rayTracingCores
Number of "Ray Tracing Cores" supported by the GPU.
Definition nvapi.h:4527
NvU32 frameIntervalUs
[in] frame interval in micro seconds if Virtual RR is currently applied
Definition nvapi.h:8705
NvU16 max_display_mastering_luminance
Maximum display mastering luminance ([0x0000-0xFFFF] = [0.0 - 65535.0] cd/m^2, in units of 1 cd/m^2)
Definition nvapi.h:7801
NvU8 * pEDID
Pointer to EDID data.
Definition nvapi.h:8535
NVVIOINPUTCONFIG inConfig
Input device configuration.
Definition nvapi.h:20492
NvU32 fields
Caller sets to NVVIOCONFIG_* mask for fields to use.
Definition nvapi.h:20475
struct _NVVIOGAMMACORRECTION NVVIOGAMMACORRECTION
Gamma correction.
NvU64 lastFlipTimeStamp
[out] Timestamp for the lastest flip on the screen
Definition nvapi.h:8598
NvU8 rsvd[64]
Definition nvapi.h:5462
NvU32 linkMask
This parameter specifies for which links we want the status.
Definition nvapi.h:4469
NVVIOGAMMARAMP10 gammaRamp10
Gamma ramp (10-bit index, 16-bit values)
Definition nvapi.h:20198
NvU32 cloneImportance
If targets are cloned views of the sourceDesktopRect the cloned targets have an importance assigned (...
Definition nvapi.h:3919
enum _NVVIODATAFORMAT NVVIODATAFORMAT
Video data format.
NvU8 supportDeepColor30bits
Byte 3.
Definition nvapi.h:8067
NvAPI_UnicodeString launcher
Indicates the name (if any) of the launcher that starts the Application.
Definition nvapi.h:21959
NvU8 colorFormat
One of NV_COLOR_FORMAT enum values.
Definition nvapi.h:7337
NvU32 reserved2[14]
Reserved for future use.
Definition nvapi.h:4529
NVVIOINPUTOUTPUTSTATUS vid1Out
Video 1 output status.
Definition nvapi.h:20050
NvU8 reservedData[256]
Indicates last stored SDI output state TRUE-ON / FALSE-OFF.
Definition nvapi.h:20408
NvU32 pciRevisionId
specifies the internal PCI device-specific revision identifier for the GVI.
Definition nvapi.h:20850
NvU32 reserved
Reserved for future use.
Definition nvapi.h:9018
NvU32 linkMask
This parameter specifies for which links we want the status.
Definition nvapi.h:4476
NvU32 version
version field to ensure minimum version compatibility
Definition nvapi.h:3585
NvU32 freq
Clock frequency in kHz.
Definition nvapi.h:4650
NvU8 rsvd[64]
Definition nvapi.h:5697
NvU32 version
Structure Version.
Definition nvapi.h:21979
NvAPI_UnicodeString appName
String name of the Application.
Definition nvapi.h:21943
NvU32 adapterClass
Graphics adapter classes (NVVIOCLASS_SDI mask)
Definition nvapi.h:20003
NvU32 isSynced
Whether this GPU is sync'd or not.
Definition nvapi.h:10207
NvU32 reservedEx[4]
reserved for future use.
Definition nvapi.h:8599
NvU8 bIsDDCPort
Definition nvapi.h:2943
NvU32 displaySettingsCount
Number of display settings in below array.
Definition nvapi.h:9258
NvU32 deviceMask
(IN) Device mask
Definition nvapi.h:784
NvU32 parity
resolution and frame-rate relationships between Dolby Vision and other video processing
Definition nvapi.h:7563
NvU8 subLinkWidth
This field specifies the no. of lanes per sublink.
Definition nvapi.h:4444
NVVIOOWNERTYPE ownerType
Owner type (OpenGL application or Desktop mode)
Definition nvapi.h:20021
NvU32 numPstates
Number of populated pstates.
Definition nvapi.h:1271
NvS32 overlapY
Pixels of overlap on the top of target: (+overlap, -gap)
Definition nvapi.h:9945
NvU32 reservedEx[8]
reserved for future use.
Definition nvapi.h:8706
NVAPI_GSYNC_POLARITY polarity
Leading edge / Falling edge / both.
Definition nvapi.h:10337
NvU8 colorFormat
One of NV_COLOR_FORMAT enum values.
Definition nvapi.h:7349
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7681
NvU32 numVoltages
Number of populated voltages.
Definition nvapi.h:1305
NvU32 isPredefined
Is the Profile user-defined, or predefined.
Definition nvapi.h:21983
NvU32 isPhysicallyConnected
if bit is set, then this display is a phycially connected display; Valid only when isConnected bit is...
Definition nvapi.h:1940
NvPhysicalGpuHandle hPhysicalGpu
Compute-capable physical GPU handle.
Definition nvapi.h:3238
NvU32 version
Version of this structure.
Definition nvapi.h:7644
@ NV_EDID_FLAG_FORCED
the EDID is forced by the end-user over s/w interface,
Definition nvapi.h:353
@ NV_EDID_FLAG_RAW
Definition nvapi.h:350
@ NV_EDID_FLAG_COOKED
the EDID has been modified by the driver for compatibility
Definition nvapi.h:352
@ NV_EDID_FLAG_HW
the EDID is from the monitor over I2C bus without any modification.
Definition nvapi.h:355
@ NV_EDID_FLAG_DEFAULT
the EDID which is actively used by the driver, it could be _RAW/_COOKED/_FORCED/_INF.
Definition nvapi.h:349
@ NV_EDID_FLAG_INF
the EDID is from monitor INF
Definition nvapi.h:354
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7790
NvU16 max_frame_average_light_level
Maximum Frame-Average Light Level (MaxFALL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7667
NvU32 version
Structure version, needs to be initialized with NV_SCANOUT_INFORMATION_VER.
Definition nvapi.h:3912
NvU32 isEnabled
The current state of license, true=licensed, false=unlicensed.
Definition nvapi.h:4135
NvAPI_UnicodeString wszPredefinedValue
Accessing default unicode string value of this setting.
Definition nvapi.h:21901
NvU32 bPrimary
Definition nvapi.h:726
NV_GPU_CLIENT_ILLUM_DEVICE_TYPE type
Definition nvapi.h:5551
NvU32 reserved
Reserved. Should be 0.
Definition nvapi.h:21950
_NVVIOOUTPUTAREA
Video output area.
Definition nvapi.h:19804
NvU32 i2cSpeed
Deprecated, Must be set to NVAPI_I2C_SPEED_DEPRECATED.
Definition nvapi.h:2955
NV_ROTATE rotation
Rotation of display.
Definition nvapi.h:9618
NvU32 majorVersion
Major version. For GVI, majorVersion contains MajorVersion(HIWORD) And MinorVersion(LOWORD)
Definition nvapi.h:20011
NvU16 desired_content_max_luminance
Maximum display luminance = desired max luminance of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7447
NvU32 isTraditionalHdrGammaSupported
HDMI2.0a traditional HDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7424
NvU16 displayWhitePoint_x
x coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7543
NVVIOOUTPUTAREA outputArea
Usable resolution for video output (safe area)
Definition nvapi.h:20390
NV_GPU_ILLUMINATION_ATTRIB Attribute
Definition nvapi.h:5286
struct _NVVIOCHANNELSTATUS NVVIOCHANNELSTATUS
Input channel status.
NvU16 max_frame_average_light_level
Maximum Frame-Average Light Level (MaxFALL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7696
NvU32 isMultiStreamRootNode
Definition nvapi.h:1930
NVVIOOUTPUTREGION outputRegion
Region for video output (Desktop mode)
Definition nvapi.h:20361
NV_THERMAL_TARGET target
Thermal sensor targeted - GPU, memory, chipset, powersupply, Visual Computing Device,...
Definition nvapi.h:4967
void(__cdecl * NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_V1)(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_CLIENT_CALLBACK_UTILIZATION_DATA_V1 *pData)
Definition nvapi.h:23091
NVAPI_GSYNC_RJ45_IO RJ45_IO[NVAPI_MAX_RJ45_PER_GSYNC]
Configured as input / output.
Definition nvapi.h:10525
NvU8 cnc1SupportPhotoContent
Byte 5.
Definition nvapi.h:8075
NV_STATIC_METADATA_DESCRIPTOR_ID static_metadata_descriptor_id
Static Metadata Descriptor Id (0 for static metadata type 1)
Definition nvapi.h:7647
NvU32 version
Version of this structure.
Definition nvapi.h:9319
NvU16 rep
Bit-wise pixel repetition factor: 0x1:no pixel repetition; 0x2:each pixel repeats twice horizontally,...
Definition nvapi.h:610
NvU32 reserved
Definition nvapi.h:7499
NV_STATIC_METADATA_DESCRIPTOR_ID static_metadata_descriptor_id
Static Metadata Descriptor Id (0 for static metadata type 1)
Definition nvapi.h:7676
NvU32 ClockType
One of NV_GPU_CLOCK_FREQUENCIES_CLOCK_TYPE. Used to specify the type of clock to be returned.
Definition nvapi.h:5055
NvU32 numClocks
Number of populated clocks (per pstate)
Definition nvapi.h:1274
NvU32 bPrimary
Definition nvapi.h:786
NvU16 cc_white_y
White primary chromaticity coordinate y.
Definition nvapi.h:7576
NV_LICENSE_FEATURE_TYPE featureCode
Feature code that corresponds to the licensable feature.
Definition nvapi.h:4138
NvU32 frameLockEnable
Flag indicating whether framelock was on/off.
Definition nvapi.h:20369
NvU8 nvlinkRefClkType
This field specifies whether refclk is taken from NVHS reflck or PEX refclk for the current GPU....
Definition nvapi.h:4453
NvU16 cc_blue_y
Blue primary chromaticity coordinate y.
Definition nvapi.h:7508
NvU8 signature[NV_LICENSE_SIGNATURE_SIZE]
Definition nvapi.h:4200
NvU32 architecture
architecture and architecture_id are the same. The former is NvU32 while the latter is an enum made f...
Definition nvapi.h:2845
NvU32 isConnected
if bit is set, then this display is connected
Definition nvapi.h:1937
NvU32 version
Version of this structure.
Definition nvapi.h:9088
NvU32 version
Structure version.
Definition nvapi.h:8541
NvU32 isDolbyVisionSupported
Dolby Vision Support. Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7525
NvU32 width
(IN) Width of the mode
Definition nvapi.h:791
NvU32 reserved[8]
Reserved for future use.
Definition nvapi.h:8544
NvU16 min_display_mastering_luminance
Minimum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 6.55350] cd/m^2)
Definition nvapi.h:7664
NvU8 bIsValidInfo
Boolean : Returns invalid if requested info is not present such as VCDB not present.
Definition nvapi.h:8118
NvU32 capsTbl
This is bit field for getting different global caps.The individual bitfields are specified by NVAPI_N...
Definition nvapi.h:4272
NvU16 max_display_mastering_luminance
Maximum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7663
NvU32 bIsMulDivSupported
Indicates if multiplication/division of the frequency of house sync signal is supported.
Definition nvapi.h:10137
NvU32 tvFormat
Definition nvapi.h:7958
NV_FORMAT colorFormat
Ignored at present, must be NV_FORMAT_UNKNOWN (0)
Definition nvapi.h:984
NvU32 version
version of this structure
Definition nvapi.h:3776
NvU32 numPixels
delay to be induced in number of pixels.
Definition nvapi.h:10326
NvU16 target_max_luminance
Represents max luminance level of sink.
Definition nvapi.h:7568
NvU8 * pbData
The buffer of data which is to be read or written (depending on the command).
Definition nvapi.h:2933
NV_GPU_ARCHITECTURE_ID architecture_id
specifies the architecture level for the GPU.
Definition nvapi.h:2846
NvU16 HSyncWidth
horizontal sync width
Definition nvapi.h:650
NvU32 isTraditionalSdrGammaSupported
HDMI2.0a traditional SDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7524
NvU32 maxLines
maximum number of lines supported at current display mode to induce delay. Updated by NvAPI_GSync_Get...
Definition nvapi.h:10327
NvU8 txSublinkStatus
This field specifies the current state of TX sublink.See NVAPI_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_ST...
Definition nvapi.h:4425
NvU32 version
[in] Structure version
Definition nvapi.h:8739
struct _NVVIOGAMMARAMP10 NVVIOGAMMARAMP10
Gamma ramp (10-bit index)
NvU32 hwModeSetOnly
If set, it means a hardware modeset without OS update.
Definition nvapi.h:8213
NvU32 bIsPresent
Set if this domain is present on this GPU.
Definition nvapi.h:5030
NvU32 deviceId
device ID
Definition nvapi.h:22707
NvU16 HFrontPorch
horizontal front porch
Definition nvapi.h:649
NvBool bLowLatencyBoost
(IN) Request maximum GPU clock frequency regardless of workload.
Definition nvapi.h:17533
NV_ROTATE rotation
(IN) Rotation setting.
Definition nvapi.h:797
NvU16 max_content_light_level
Maximum Content Light level (MaxCLL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7695
NvU32 vendorId
vendor ID
Definition nvapi.h:22706
NvU32 version
Version of this structure.
Definition nvapi.h:7386
NvU32 reservedEx
Reserved for future use.
Definition nvapi.h:22925
NvAPI_UnicodeString fileInFolder
Definition nvapi.h:21935
float * vertices
width of the input texture
Definition nvapi.h:3737
NV_ROTATE rotation
Rotation of display.
Definition nvapi.h:9598
NvU32 isMetro
Windows 8 style app.
Definition nvapi.h:21948
NvU32 is8BPCSupported
If 8 bpc is supported.
Definition nvapi.h:6543
_NVVIODATAFORMAT
Video data format.
Definition nvapi.h:19773
NvU32 errorFlags
(OUT) Any of the NV_MOSAIC_DISPLAYCAPS_PROBLEM_* flags.
Definition nvapi.h:9765
NvAPI_LicenseString licenseInfo
Deprecated.
Definition nvapi.h:4150
NvU32 version
(IN) Structure version
Definition nvapi.h:832
NvU32 version
Structure version.
Definition nvapi.h:3984
NvU32 enableAudioBlanking
Enable HANC audio blanking on repeat frames.
Definition nvapi.h:20441
NvAPI_ShortString szVendorName
vendor Name
Definition nvapi.h:22726
NvU8 dynamicRange
One of NV_DYNAMIC_RANGE enum values.
Definition nvapi.h:7393
NvU32 capFlags
Capabilities of the Sync board. Reserved for future use.
Definition nvapi.h:10118
_NVVIOOWNERTYPE
Owner type for device.
Definition nvapi.h:19628
NvU32 version
Version of this structure.
Definition nvapi.h:7344
NV_ROTATE sourceToTargetRotation
Rotation performed between the sourceViewportRect and the targetViewportRect.
Definition nvapi.h:3920
_NV_GPU_CLIENT_UTIL_DOMAIN_ID
Definition nvapi.h:23021
NvU32 numOfApps
Total number of applications that belong to this profile. Read-only.
Definition nvapi.h:21984
NV_LICENSE_FEATURE_DETAILS_V1 licenseDetails[NV_LICENSE_MAX_COUNT]
Array of licensable features.
Definition nvapi.h:4169
NvU32 width
width of the input texture
Definition nvapi.h:3652
NvU32 reserved
Reserved for future use.
Definition nvapi.h:4434
NvU32 driverExpandDefaultHdrParameters
Definition nvapi.h:7460
NvU32 enableAlphaKeyComposite
Enable Alpha key composite.
Definition nvapi.h:20378
NvU32 IsNonNVIDIAAdapter
True for non-NVIDIA adapter.
Definition nvapi.h:1024
NvU32 version
Version number of the mosaic topology.
Definition nvapi.h:9936
NVAPI_GSYNC_POLARITY polarity
Leading edge / Falling edge / both.
Definition nvapi.h:10360
NV_MOSAIC_DISPLAY_SETTING_V2 displaySettings[NV_MOSAIC_DISPLAY_SETTINGS_MAX]
List of per display settings possible.
Definition nvapi.h:9269
NV_DISPLAYCONFIG_SOURCE_MODE_INFO_V1 * sourceModeInfo
May be NULL if mode info is not important.
Definition nvapi.h:1023
NvU32 isYCbCr444SupportedOnCurrentMode
If YCbCr444 is supported on the current mode.
Definition nvapi.h:6551
NvU32 extendedRevision
FPGA minor revision.
Definition nvapi.h:10127
NvU8 type
type of infoframe
Definition nvapi.h:7196
NvU32 isGpuHDMICapable
If the GPU can handle HDMI.
Definition nvapi.h:6687
NvU32 reserved
These bits are reserved for future use.
Definition nvapi.h:5031
NvU16 cc_red_x
Red primary chromaticity coordinate x.
Definition nvapi.h:7503
NvU32 version
(IN) Structure version
Definition nvapi.h:823
NvU32 nvlinkRefClkSpeedMhz
This field gives the value of nvlink refclk clock in MHz.
Definition nvapi.h:4430
NvU32 pciSubSystemId
specifies the internal PCI subsystem identifier for the GVI.
Definition nvapi.h:20849
NvU32 acceleratePrimaryDisplay
Enable SLI acceleration on the primary display while in single-wide mode (For Immersive Gaming only)....
Definition nvapi.h:9655
NvU8 highestNvlinkVersion
This field specifies the highest supported NVLink version for this GPU.
Definition nvapi.h:4274
NvU32 supports_2160p60hz
If set sink is capable of 4kx2k @ 60hz.
Definition nvapi.h:7491
NvU32 isMonBasicAudioCapable
If the monitor supports basic audio.
Definition nvapi.h:6672
NvU32 jack
This stream's link[i] will use the specified (0-based) channel within the.
Definition nvapi.h:20453
NvU32 numOfSettings
Total number of settings applied for this Profile. Read-only.
Definition nvapi.h:21985
NvU16 uBlue[1024]
Blue channel gamma ramp (10-bit index, 16-bit values)
Definition nvapi.h:20103
NvU32 version
Structure version - 2 is the latest.
Definition nvapi.h:6631
NVDRS_GPU_SUPPORT gpuSupport
Definition nvapi.h:21981
NvU32 gpuFrameTimeUs
(OUT) Difference between previous and current frame's gpuRenderEndTime, in microseconds.
Definition nvapi.h:17677
NvU32 testColorChange
If testing mode, skip validation.
Definition nvapi.h:6643
NV_TIMING timing
Definition nvapi.h:937
NvU32 houseSyncIncoming
Incoming house sync frequency in Hz.
Definition nvapi.h:10537
NvU32 adapterCaps
Graphics adapter capabilities (NVVIOCAPS_* mask)
Definition nvapi.h:20004
NvU32 displayCount
Number of display details.
Definition nvapi.h:9650
NvU32 interlaced
(IN) Interlaced mode flag, ignored if refreshRate == 0
Definition nvapi.h:914
NV_LICENSE_FEATURE_DETAILS_V3 licenseDetails[NV_LICENSE_MAX_COUNT]
Array of licensable features.
Definition nvapi.h:4191
NvU8 reserved6
Byte 3.
Definition nvapi.h:8065
NvU8 supportAI
Byte 3.
Definition nvapi.h:8070
#define NVAPI_MAX_VIO_LINKS_PER_STREAM
SDI input supports a max of 2 links per stream.
Definition nvapi.h:19880
NV_DP_BPC bpc
Current bit-per-component.
Definition nvapi.h:6538
NvU32 version
version of this structure
Definition nvapi.h:3642
NV_DESKTOP_COLOR_DEPTH depth
One of NV_DESKTOP_COLOR_DEPTH enum values.
Definition nvapi.h:7396
NvU32 sourceId
(IN) Values will be based on the number of heads exposed per GPU(0, 1?)
Definition nvapi.h:785
NvU32 vioGammaCorrectionType
Definition nvapi.h:20193
NvU32 psfSignalFormat
Indicates whether contained format is PSF Signal format.
Definition nvapi.h:20370
NvU32 reserved
reserved
Definition nvapi.h:6568
NvU32 reserved
Reserved for future use.
Definition nvapi.h:22923
NvU32 reserved
should be set zero
Definition nvapi.h:10367
NvU32 width
Width of region in pixels.
Definition nvapi.h:20086
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7658
NvS32 defaultMaxTemp
Maximum default temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4965
NvU32 width
Per-display width.
Definition nvapi.h:9227
NVLINK_DEVICE_INFO_V1 localDeviceInfo
This field stores the device information for the local end of the link.
Definition nvapi.h:4461
float y
y-coordinate of the viewport top-left point
Definition nvapi.h:561
NvU32 flags
Reserved for future use. Must be set to 0.
Definition nvapi.h:4662
NvU32 bIsExternalGpu
This flag is set for external GPU.
Definition nvapi.h:4517
NV_FORMAT colorFormat
Color format (optional)
Definition nvapi.h:8205
NvU32 version
version of this structure
Definition nvapi.h:7193
NvU32 reserved_sourceId
Only for compatibility.
Definition nvapi.h:1018
NvU32 version
Version of this structure.
Definition nvapi.h:5210
NvU32 version
Structure Version.
Definition nvapi.h:4516
NvU32 maxMulDivValue
Definition nvapi.h:10139
NvU16 VFrontPorch
vertical front porch
Definition nvapi.h:656
NVVIOOUTPUTREGION outputRegion
Region for video output (Desktop mode)
Definition nvapi.h:20389
NvU32 numClocks
The number of clock domains supported by each P-State.
Definition nvapi.h:4667
NVVIOCONFIGTYPE nvvioConfigType
Input or Output configuration.
Definition nvapi.h:20476
NvU32 version
[in] Structure version
Definition nvapi.h:9016
NvU32 version
Version of this structure.
Definition nvapi.h:7787
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1289
NvU32 width
Visible horizontal size.
Definition nvapi.h:7975
NvU64 doubleBitErrors
Number of double-bit ECC errors detected since last counter reset.
Definition nvapi.h:3397
NvU32 volt_uV
Current base voltage settings in [uV].
Definition nvapi.h:1210
NvU32 supports_10b_12b_444
It is set when interface supported is low latency, it tells whether it supports 10 bit or 12 bit RGB ...
Definition nvapi.h:7498
NvU32 enableAlphaKeyComposite
Enable Alpha key composite.
Definition nvapi.h:20435
NvU32 version
Version of this structure.
Definition nvapi.h:9202
NvU32 reserved
Reserved for future use.
Definition nvapi.h:4456
NvU32 isVRReady
Is the requested GPU VR ready.
Definition nvapi.h:4565
NvU8 hdmi3dLength
Byte 11.
Definition nvapi.h:8094
NvAPI_UnicodeString userFriendlyName
UserFriendly name of the Application.
Definition nvapi.h:21924
enum _NV_GPU_CLIENT_UTIL_DOMAIN_ID NV_GPU_CLIENT_UTIL_DOMAIN_ID
NvU32 nvlinkLinkClockMhz
This field gives the actual clock/speed at which links is running in MHz.
Definition nvapi.h:4454
NvU32 rrx1k
Display frequency in x1k.
Definition nvapi.h:9231
NvU32 supports_10b_12b_444
It is set when interface supported is low latency, it tells whether it supports 10 bit or 12 bit RGB ...
Definition nvapi.h:7562
NvU32 isMonxvYCC709Capable
If xvYCC 709 is supported.
Definition nvapi.h:6676
NvU32 count
(IN) Path count
Definition nvapi.h:833
NvU32 supports_backlight_control
This is set when sink is using lowlatency interface and can control its backlight.
Definition nvapi.h:7495
NVVIOSIGNALFORMAT signalFormat
Signal format for video output.
Definition nvapi.h:20387
enum _NVVIOCONFIGTYPE NVVIOCONFIGTYPE
Device configuration.
NvU32 enableFullColorRange
Flag indicating Full Color Range.
Definition nvapi.h:20409
NvU32 bEnable
(IN) Enable Reflex Sync
Definition nvapi.h:17619
NvBool bUseMarkersToOptimize
(IN) Allow latency markers to be used for runtime optimizations.
Definition nvapi.h:17535
NV_HDR_CMD cmd
Command get/set.
Definition nvapi.h:7674
NvU32 mvolt
Voltage in mV.
Definition nvapi.h:4688
NV_DP_BPC backendBitDepths
One of the supported bit depths.
Definition nvapi.h:8145
NvU16 max_content_light_level
Maximum Content Light level (MaxCLL) ([0x0000-0xFFFF] = [0.0 - 65535.0] cd/m^2, in units of 1 cd/m^2)
Definition nvapi.h:7804
NVVIOANCPARITYCOMPUTATION ancParityComputation
Enable HW ANC parity bit computation (auto/on/off)
Definition nvapi.h:20411
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7470
NvU32 version
Version info of the structure (NV_GPU_PERF_PSTATES20_INFO_VER<n>)
Definition nvapi.h:1263
NvU32 enableFullColorRange
Flag indicating Full Color Range.
Definition nvapi.h:20381
NvU32 bGDIPrimary
(IN/OUT) Indicates if this is the desktop GDI primary.
Definition nvapi.h:811
NvU32 enableDataIntegrityCheck
Enable data integrity check: true - enable, false - disable.
Definition nvapi.h:20430
NV_LICENSE_FEATURE_TYPE featureCode
Feature code that corresponds to the licensable feature.
Definition nvapi.h:4118
NvU32 maxFreq_kHz
Max clock frequency within given pstate in (kHz)
Definition nvapi.h:1189
NvU32 bIsVRREnabled
[out] Set if VRR Mode is currently enabled on given display.
Definition nvapi.h:9017
NvU8 rsvd[31]
(IN) Reserved. Must be set to 0s.
Definition nvapi.h:17536
NvU32 version
Structure version.
Definition nvapi.h:6668
NvU32 minimumIntervalUs
(IN) Minimum frame interval in microseconds. 0 = no frame rate limit.
Definition nvapi.h:17534
NVVIOOUTPUTREGION outputRegion
Region for video output (Desktop mode)
Definition nvapi.h:20418
NvU32 cbSize
The size of the data buffer, pbData, to be read or written.
Definition nvapi.h:2934
NvPhysicalGpuHandle hPhysicalGpu
Definition nvapi.h:5211
NvU32 depth
(IN) Depth of the mode
Definition nvapi.h:793
NvU16 desired_content_max_frame_average_luminance
Desired maximum Frame-Average Light Level (MaxFALL) of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7449
_NVVIOSTATUSTYPE
Video Capture Status.
Definition nvapi.h:19855
NvU32 displayOutputId
Connected display target (0 if no display connected)
Definition nvapi.h:9098
NvU8 reservedData[256]
Inicates last stored SDI output state TRUE-ON / FALSE-OFF.
Definition nvapi.h:20380
NVVIOSIGNALFORMAT signalFormat
Signal format.
Definition nvapi.h:20033
NvAPI_UnicodeString appName
String name of the Application.
Definition nvapi.h:21923
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7476
NvU32 syncSourceIsOutput
Definition nvapi.h:10365
NvS32 overlapY
(+overlap, -gap)
Definition nvapi.h:9597
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7473
NvU32 reservedInternal
Do not use.
Definition nvapi.h:1939
NvAPI_UnicodeString userFriendlyName
UserFriendly name of the Application.
Definition nvapi.h:21933
NvU32 bTestMode
Definition nvapi.h:20467
NvU16 displayWhitePoint_x
x coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7798
NV_DISPLAYCONFIG_SOURCE_MODE_INFO_V1 * sourceModeInfo
May be NULL if mode info is not important.
Definition nvapi.h:1005
NvU32 isTraditionalHdrGammaSupported
HDMI2.0a traditional HDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7520
NvU32 posy
(IN/OUT) Y-offset of this display on the Windows desktop
Definition nvapi.h:810
NvU32 year
Year value of license expiry.
Definition nvapi.h:4102
NvU32 sizeOfEDID
Size of EDID data.
Definition nvapi.h:8543
NvU32 version
Version of this structure. Must always be first element in this structure.
Definition nvapi.h:4475
struct _NVVIOSTREAM NVVIOSTREAM
Stream configuration.
NVVIOOWNERID ownerId
Unique identifier for owner of video output (NVVIOOWNERID_INVALID if free running)
Definition nvapi.h:20020
NvU32 Value
Definition nvapi.h:5222
NvBool bFsVrr
(OUT) Is fullscreen VRR enabled?
Definition nvapi.h:17487
NV_GSYNC_DELAY syncSkew
The time delay between the frame sync signal and the GPUs signal.
Definition nvapi.h:10345
NvU32 enableDataIntegrityCheck
Enable data integrity check: true - enable, false - disable.
Definition nvapi.h:20373
NvU32 enableANCTimeCodeGeneration
Enable SDI ANC time code generation.
Definition nvapi.h:20404
NvU32 version
Version of this structure.
Definition nvapi.h:7673
_NVVIOCAPTURESTATUS
Video Capture Status.
Definition nvapi.h:19847
NvU16 desired_content_max_frame_average_luminance
Desired maximum Frame-Average Light Level (MaxFALL) of HDR content ([0x0000-0xFFFF] = [0....
Definition nvapi.h:7548
NVVIOSIGNALFORMAT syncFormat
Sync format.
Definition nvapi.h:20056
NvU8 colorFormat
One of NV_COLOR_FORMAT enum values.
Definition nvapi.h:7376
NV_LICENSE_FEATURE_TYPE featureCode
Feature code that corresponds to the licensable feature.
Definition nvapi.h:4127
NvAPI_UnicodeString fileInFolder
Definition nvapi.h:21960
NV_DP_COLOR_FORMAT colorFormat
One of the supported color formats.
Definition nvapi.h:8144
NvU32 version
Version of this structure.
Definition nvapi.h:7357
NvU32 frameLockEnable
Flag indicating whether framelock was on/off.
Definition nvapi.h:20426
NvU32 isColorCtrlSupported
If the color format change is supported.
Definition nvapi.h:6541
NvU32 verticalLines
Vertical resolution for frame (in lines)
Definition nvapi.h:20123
NvU32 reserved
(OUT) reserved
Definition nvapi.h:9769
NvU32 applyWithBezelCorrect
When enabling and doing the modeset, do we switch to the bezel-corrected resolution.
Definition nvapi.h:9635
NvU32 VSVDB_version
Version of Vendor Data block,Version 0: 25 bytes Version 1: 14 bytes.
Definition nvapi.h:7553
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB_PARAMS rgbParams[NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS]
Definition nvapi.h:5850
NvU32 bitsPerComponent
Bits per component.
Definition nvapi.h:20447
NvU8 name[40]
Timing name.
Definition nvapi.h:612
NvU32 pciBus
specifies the PCI bus number of the GVI device.
Definition nvapi.h:20852
float fGammaValueR
Red Gamma value within gamma ranges. 0.5 - 6.0.
Definition nvapi.h:20200
NvU32 isDitherOff
Force to turn off dither.
Definition nvapi.h:6641
NvU32 isCommandLine
Command line parsing for the application name.
Definition nvapi.h:21949
NVVIOOUTPUTCONFIG_V1 outConfig
Output device configuration.
Definition nvapi.h:20480
NvU32 flags
Chipset info flags - obsolete.
Definition nvapi.h:22692
_NVVIOCOMPONENTSAMPLING
Component sampling.
Definition nvapi.h:19919
NvU32 deviceId
device ID
Definition nvapi.h:22725
NV_COLOR_SELECTION_POLICY colorSelectionPolicy
One of the color selection policy.
Definition nvapi.h:7380
NvU32 version
IN - Structure version.
Definition nvapi.h:4185
NvU32 validityMask
Definition nvapi.h:9090
NV_GPU_PSTATE20_CLOCK_ENTRY_V1 clocks[NVAPI_MAX_GPU_PSTATE20_CLOCKS]
Definition nvapi.h:1293
NvU32 is10BPCSupported
If 10 bpc is supported.
Definition nvapi.h:6544
NvU32 version
Structure version.
Definition nvapi.h:20846
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7534
NvU32 isMonAdobeRGBCapable
if AdobeRGB extended colorimetry is supported
Definition nvapi.h:6697
NV_D3D12_WORKSTATION_FEATURE_RDMA_PROPERTIES rdmaInfo
Definition nvapi.h:19454
NvU32 isCommandLine
Command line parsing for the application name.
Definition nvapi.h:21963
NvU16 desired_content_max_luminance
Maximum display luminance = desired max luminance of HDR content ([0x0000-0xFFFF] = [0....
Definition nvapi.h:7546
NvU32 count
(IN) target count
Definition nvapi.h:721
NVVIOSIGNALFORMAT signalFormat
Definition nvapi.h:20463
NVVIOSTREAM streams[NVAPI_MAX_VIO_STREAMS]
Stream configurations.
Definition nvapi.h:20466
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7655
NvU32 version
[in] structure version
Definition nvapi.h:8704
union _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGBW::@34 data
NvU32 isEdrSupported
Extended Dynamic Range on SDR displays. Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7459
NVVIOCAPTURESTATUS captureStatus
status of video capture
Definition nvapi.h:20044
NvU32 freq_kHz
Clock frequency within given pstate in (kHz)
Definition nvapi.h:1180
NvU32 refreshRate1K
Definition nvapi.h:911
float h
Height of the viewport.
Definition nvapi.h:563
NvU32 HBvendorId
Host bridge vendor identification.
Definition nvapi.h:22696
NvAPI_ShortString szChipsetName
device Name
Definition nvapi.h:22727
NvU32 baseMosaic
Enable as Base Mosaic (Panoramic) instead of Mosaic SLI (for NVS and Quadro-boards only)
Definition nvapi.h:9637
NvU8 portId
Definition nvapi.h:2978
NvU16 cc_blue_x
Blue primary chromaticity coordinate x.
Definition nvapi.h:7507
NvU32 offset
Definition nvapi.h:324
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED_PARAMS colorFixedParams
Definition nvapi.h:5911
NvU32 is6BPCSupported
If 6 bpc is supported.
Definition nvapi.h:6542
NvU32 version
Version info of the structure (NV_GPU_PERF_PSTATES20_INFO_VER<n>)
Definition nvapi.h:1220
NvU32 isMonYCbCr444Capable
If YCbCr 4:4:4 is supported.
Definition nvapi.h:6690
NvU32 bEnabled
intensity is enabled or not
Definition nvapi.h:3695
NvU8 colorimetry
One of NV_COLOR_COLORIMETRY enum values.
Definition nvapi.h:7338
NvU32 colCount
Number of displays in a column.
Definition nvapi.h:9093
NvU16 interlaced
1-interlaced, 0-progressive
Definition nvapi.h:661
NvU32 displayMask
The Display Mask of the concerned display.
Definition nvapi.h:2963
NvU8 dynamicRange
One of NV_DYNAMIC_RANGE enum values.
Definition nvapi.h:7378
NvU8 maxTmdsClock
Bye 4.
Definition nvapi.h:8072
NvU64 singleBitErrors
Number of single-bit ECC errors detected since last counter reset.
Definition nvapi.h:3396
NVAPI_GSYNC_RJ45_IO RJ45_IO[NVAPI_MAX_RJ45_PER_GSYNC]
Configured as input / output.
Definition nvapi.h:10535
NvU32 enable422Filter
Enables/Disables 4:2:2 filter.
Definition nvapi.h:20428
NvU32 minPixels
minimum number of pixels required at current display mode to induce delay. Updated by NvAPI_GSync_Get...
Definition nvapi.h:10328
NvU32 flags
Reserved for future use. Must be set to 0.
Definition nvapi.h:4687
NvU32 freq
Display frequency.
Definition nvapi.h:9230
NvU32 version
(IN) Structure version
Definition nvapi.h:17742
NvU8 cnc0SupportGraphicsTextContent
Byte 5.
Definition nvapi.h:8074
NvU64 doubleBitErrors
Number of double-bit ECC errors detected since last boot.
Definition nvapi.h:3392
NvU32 outputId
outputId will be 0 for GVI device.
Definition nvapi.h:20522
NV_DP_DYNAMIC_RANGE dynamicRange
Dynamic range.
Definition nvapi.h:6635
NV_DP_LANE_COUNT curLaneCount
Current lane count.
Definition nvapi.h:6534
NvU8 dynamicRange
One of NV_DYNAMIC_RANGE enum values.
Definition nvapi.h:7351
NvU32 EDID861ExtRev
Revision number of the EDID 861 extension.
Definition nvapi.h:6700
NvU32 version
Unused.
Definition nvapi.h:4134
NvU32 nvlinkCommonClockSpeedMhz
This field gives the value of nvlink common clock in MHz.
Definition nvapi.h:4451
NVVIOSIGNALFORMAT signalFormat
Signal format for video output.
Definition nvapi.h:20416
NvU8 cnc2SupportCinemaContent
Byte 5.
Definition nvapi.h:8076
NvU8 isTrueGsync
whether the monitor is actually GSYNC or adaptive sync monitor : 0 for adaptive sync.
Definition nvapi.h:8105
NvPhysicalGpuHandle hPhysicalGpu
Handle to Physical GPU (This could be NULL for GVI device if its not binded)
Definition nvapi.h:20519
NvU32 supports_YUV422_12bit
If set, sink is capable of YUV422-12 bit.
Definition nvapi.h:7492
NV_I2C_SPEED i2cSpeedKhz
The target speed of the transaction in (kHz) (Chosen from the enum NV_I2C_SPEED).
Definition nvapi.h:2977
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1169
NvU8 lowestNvlinkVersion
This field specifies the lowest supported NVLink version for this GPU.
Definition nvapi.h:4273
NvU32 bInterlaced
(IN/OUT) Indicates if the timing being used on this monitor is interlaced.
Definition nvapi.h:728
NvU32 isST2084EotfSupported
HDMI2.0a UHDA HDR with ST2084 EOTF (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7519
NvU16 VVisible
vertical visible
Definition nvapi.h:654
NvU16 min
Minutes value of license expiry.
Definition nvapi.h:4106
NvU16 HBorder
horizontal border
Definition nvapi.h:648
NvU32 version
Version of this structure.
Definition nvapi.h:9647
NvU32 EDID861ExtRev
Revision number of the EDID 861 extension.
Definition nvapi.h:6680
NvU32 u32PredefinedValue
Accessing default DWORD value of this setting.
Definition nvapi.h:21897
NvU32 numClocks
The number of clock domains supported by each P-State.
Definition nvapi.h:4638
NvU32 bForceModeSet
(IN) Used only on Win7 and higher during a call to NvAPI_SetViewEx(). Turns off optimization & forces...
Definition nvapi.h:813
NvAPI_LicenseString productName
Nvidia Grid licensable product name.
Definition nvapi.h:4151
NvU32 enableAlphaKeyComposite
Enable Alpha key composite.
Definition nvapi.h:20406
NvU32 timeInQueueUsTarget
(IN) Target amount of time in the completed frame queue. (0 means N/A)
Definition nvapi.h:17624
NVVIOOUTPUTAREA outputArea
Usable resolution for video output (safe area)
Definition nvapi.h:20419
NV_TIMING_OVERRIDE type
Timing type(formula) to use for calculating the timing.
Definition nvapi.h:7981
NvU32 physicalGpuCount
[out] Number of physical GPU handles associated with the specified logical GPU handle.
Definition nvapi.h:4028
NvU32 isLicenseSupported
True if Software Licensing is supported.
Definition nvapi.h:4197
NvU32 horizontalDelay
Horizontal delay in pixels.
Definition nvapi.h:20111
NV_TIMING_FLAG flag
Flag containing additional info for timing calculation.
Definition nvapi.h:7979
NvU32 boardId
Board ID.
Definition nvapi.h:10124
NV_DISPLAY_TV_FORMAT tvFormat
Definition nvapi.h:929
NvU8 rsvd[126]
(IN) Reserved. Must be set to 0s.
Definition nvapi.h:17489
enum _NVVIOCOMPONENTSAMPLING NVVIOCOMPONENTSAMPLING
Component sampling.
NvU32 isMonHDMI
If the monitor is HDMI (with IEEE's HDMI registry ID)
Definition nvapi.h:6677
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7657
NvU16 uRed[1024]
Red channel gamma ramp (10-bit index, 16-bit values)
Definition nvapi.h:20101
NvU32 isInterlaced
To retrieve interlaced/progressive timing.
Definition nvapi.h:7954
NVVIODATAFORMAT dataFormat
Data format for video output.
Definition nvapi.h:20388
NvU32 subSysDeviceId
subsystem device ID
Definition nvapi.h:22712
NvU16 desired_content_min_luminance
Minimum display luminance = desired min luminance of HDR content ([0x0000-0xFFFF] = [0....
Definition nvapi.h:7547
NvU32 reserved
Reserved. Should be 0.
Definition nvapi.h:21964
NvU32 reserved
reserved for future use. Should be set to ZERO.
Definition nvapi.h:3987
NVVIOSIGNALFORMAT signalFormat
Signal format enumerated value.
Definition nvapi.h:20133
NvAPI_UnicodeString wszCurrentValue
Accessing current unicode string value of this setting.
Definition nvapi.h:21909
NvU32 regAddrSize
Definition nvapi.h:2972
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1225
NV_DP_LANE_COUNT laneCount
Lane count.
Definition nvapi.h:6633
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7686
NvU32 interface_supported_by_sink
Indicates the interface (standard or low latency) supported by the sink.
Definition nvapi.h:7497
NvU8 i2cDevAddress
Definition nvapi.h:2966
NvU32 version
Version of the structure.
Definition nvapi.h:10115
NvU32 RJ45_Ethernet[NVAPI_MAX_RJ45_PER_GSYNC]
Connected to ethernet hub? [ERRONEOUSLY CONNECTED!].
Definition nvapi.h:10536
NvU8 illumDeviceIdx
Definition nvapi.h:5672
NvU32 version
structure version
Definition nvapi.h:22687
NvU32 isSupported
ECC memory feature support.
Definition nvapi.h:3371
NV_DP_COLOR_FORMAT colorFormat
Color format to set.
Definition nvapi.h:6634
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7793
NvU32 version
(IN) Structure version
Definition nvapi.h:17485
NV_GSYNC_DELAY syncSkew
The time delay between the frame sync signal and the GPUs signal.
Definition nvapi.h:10368
NvU32 numBaseVoltages
Number of populated base voltages (per pstate)
Definition nvapi.h:1277
NvU32 depth
Source surface color depth."0" means all 8/16/32bpp.
Definition nvapi.h:8204
NvU32 nvlinkRefClkSpeedMhz
This field gives the value of nvlink refclk clock in MHz.
Definition nvapi.h:4452
NvU32 sizeOfEDID
Size of EDID data.
Definition nvapi.h:8536
NvU8 audioLatency
Byte 7.
Definition nvapi.h:8085
NvU32 boardId
Board ID.
Definition nvapi.h:10133
NvU32 numIllumZones
Definition nvapi.h:5713
struct _NV_GPU_CLIENT_PERIODIC_CALLBACK_SETTINGS_SUPER_V1 NV_GPU_CLIENT_PERIODIC_CALLBACK_SETTINGS_SUPER_V1
NvU32 reserved
reserved for future use.
Definition nvapi.h:8636
NV_GPU_CONNECTOR_TYPE connector
Specify connector type. For TV only, ignored if tvFormat == NV_DISPLAY_TV_FORMAT_NONE.
Definition nvapi.h:928
NvU8 * pbI2cRegAddress
Definition nvapi.h:2949
NvU32 cscOverride
Use provided CSC color matrix to overwrite.
Definition nvapi.h:20402
NvU32 isPredefined
Is the application userdefined/predefined.
Definition nvapi.h:21922
float fGammaValueB
Blue Gamma value within gamma ranges. 0.5 - 6.0.
Definition nvapi.h:20202
NvU32 reserved
Reserved.
Definition nvapi.h:4126
NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId
ID of the voltage domain, containing flags and mvolt info.
Definition nvapi.h:4686
NvU32 i2cSpeed
The target speed of the transaction (between 28Kbps to 40Kbps; not guaranteed).
Definition nvapi.h:2935
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7683
NvU8 i2cDevIdx
Definition nvapi.h:5390
NvU32 bDisableAdaptiveSync
[in] Indicates if adaptive sync is disabled on the display.
Definition nvapi.h:8634
NvU32 topoBriefsCount
Number of topologies in below array.
Definition nvapi.h:9266
NvU16 peak_luminance_index
Peak luminance index.
Definition nvapi.h:7583
NvU32 numSettingValues
Total number of values available in a setting.
Definition nvapi.h:21865
@ NVAPI_VSYNC_OFF
Force vertical sync off when performance is more important than image quality and for benchmarking".
Definition nvapi.h:11416
@ NVAPI_VSYNC_ADAPTIVE
Definition nvapi.h:11418
@ NVAPI_VSYNC_DEFAULT
Fall back to the default settings.
Definition nvapi.h:11415
@ NVAPI_VSYNC_ON
Force vertical sync on when image quality is more important than performance.
Definition nvapi.h:11417
NvU32 nvlinkCommonClockSpeedMhz
This field gives the value of nvlink common clock in MHz.
Definition nvapi.h:4429
NVVIODATAFORMAT dataFormat
Data format for video output.
Definition nvapi.h:20360
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7442
NvU32 bIsExternalGpu
This flag is set for external GPU.
Definition nvapi.h:4524
struct _NVVIOINPUTSTATUS NVVIOINPUTSTATUS
Input device status.
NvU32 isMonHDMI
If the monitor is HDMI (with IEEE's HDMI registry ID)
Definition nvapi.h:6694
NvU32 regAddrSize
Definition nvapi.h:2951
NvU32 version
[in] Structure version.
Definition nvapi.h:4026
NvPhysicalGpuHandle hPhysicalGpu
Definition nvapi.h:5146
NvU8 reserved8
Byte 5.
Definition nvapi.h:8078
NvU16 target_min_luminance
Represents min luminance level of Sink.
Definition nvapi.h:7501
NvU32 minorVersion
Minor version. For GVI, minorVersion contains Revison(HIWORD) And Build(LOWORD)
Definition nvapi.h:20012
NvU32 revision
FPGA major revision.
Definition nvapi.h:10134
NV_DP_BPC bpc
Bit-per-component.
Definition nvapi.h:6637
NvU32 displayId
(OUT) The DisplayID of this display.
Definition nvapi.h:9764
NV_DISPLAY_TV_FORMAT tvFormat
(IN) To choose the last TV format set this value to NV_DISPLAY_TV_FORMAT_NONE
Definition nvapi.h:806
NVDRS_BINARY_SETTING binaryDefaultValue
Definition nvapi.h:21870
NvAPI_ShortString szSubSysVendorName
subsystem vendor Name
Definition nvapi.h:22695
NVVIOSYNCSOURCE syncSource
Sync source.
Definition nvapi.h:20055
NvU32 vioCaps
Data format capabilities (NVVIOCAPS_* mask)
Definition nvapi.h:20168
NvU32 enableRGBData
Indicates data is in RGB format.
Definition nvapi.h:20439
NvU8 rsvd[61]
Definition nvapi.h:23052
NvU8 hdmi_vic[7]
Keeping maximum length for 3 bits.
Definition nvapi.h:8097
NvU32 width
width of the input texture
Definition nvapi.h:3643
NvU32 version
Version of this structure.
Definition nvapi.h:9217
NvU32 version
Structure Version.
Definition nvapi.h:4523
NvU8 rsvd[64]
Definition nvapi.h:5878
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7654
NvU32 isEnabled
Structure version.
Definition nvapi.h:3506
NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId
ID of the voltage domain.
Definition nvapi.h:1203
NvU32 interval
Number of pulses to wait between framelock signal generation.
Definition nvapi.h:10362
NvU32 isHPD
If the control panel is making this call due to HPD.
Definition nvapi.h:6638
NvU32 nvlinkLinkClockMhz
This field gives the actual clock/speed at which links is running in MHz.
Definition nvapi.h:4432
NvU32 u32Value
< NOT mixed types.
Definition nvapi.h:21876
NV_MONITOR_CONN_TYPE connectorType
Definition nvapi.h:1925
NvU32 u32CurrentValue
Accessing current DWORD value of this setting.
Definition nvapi.h:21905
NvU32 version
Version of this structure.
Definition nvapi.h:7421
NvU32 isMonsYCC601Capable
if sYCC601 extended colorimetry is supported
Definition nvapi.h:6695
NvU32 supports_global_dimming
Indicates if sink supports global dimming.
Definition nvapi.h:7557
NvU32 errorFlags
(OUT) Any of the NV_MOSAIC_DISPLAYTOPO_ERROR_* flags.
Definition nvapi.h:9758
NV_HDR_MODE hdrMode
HDR mode.
Definition nvapi.h:7646
NvU32 targetDisplayHeight
Vertical size of the active resolution scanned out to the display.
Definition nvapi.h:3918
NvU16 displayWhitePoint_x
x coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7444
NvU32 version
IN - Structure version.
Definition nvapi.h:4115
NvU32 enable422Filter
Enables/Disables 4:2:2 filter.
Definition nvapi.h:20371
NvU32 height
Per-display height.
Definition nvapi.h:9219
NvU32 syncEnable
Sync enable (TRUE to use syncSource)
Definition nvapi.h:20393
NV_HDR_CMD cmd
Command get/set.
Definition nvapi.h:7645
NvU32 boardId
Board ID.
Definition nvapi.h:10116
NvU16 displayWhitePoint_y
y coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7445
NVAPI_GSYNC_DISPLAY_SYNC_STATE syncState
Definition nvapi.h:10217
NvU32 version
Version of this structure.
Definition nvapi.h:9631
NV_STATIC_METADATA_DESCRIPTOR_ID static_metadata_descriptor_id
Static Metadata Descriptor Id (0 for static metadata type 1)
Definition nvapi.h:7530
NvU32 fields
Caller sets to NVVIOCONFIG_* mask for fields to use.
Definition nvapi.h:20488
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW_PARAMS rgbwParams
Definition nvapi.h:6005
NvU32 reservedEx[7]
reserved for future use.
Definition nvapi.h:8637
NvU32 isST2084EotfSupported
HDMI2.0a UHDA HDR with ST2084 EOTF (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7457
NvU32 version
Definition nvapi.h:5708
NvU8 rxSublinkStatus
This field specifies the current state of RX sublink.See NVAPI_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_ST...
Definition nvapi.h:4424
NvSBox sourceDesktopRect
Operating system display device rect in desktop coordinates displayId is scanning out from.
Definition nvapi.h:3914
NvU32 isPredefined
Is the application userdefined/predefined.
Definition nvapi.h:21931
NvU32 isMonUnderscanCapable
If the monitor supports underscan.
Definition nvapi.h:6688
NV_GPU_PUBLIC_CLOCK_ID domainId
ID of the clock domain.
Definition nvapi.h:1162
NV_MOSAIC_TOPO_BRIEF topoBriefs[NV_MOSAIC_TOPO_MAX]
List of supported topologies with only brief details.
Definition nvapi.h:9257
NvAPI_UnicodeString wszValue
Accessing current unicode string value of this setting.
Definition nvapi.h:21878
NvU32 enableComposite
Enable composite.
Definition nvapi.h:20377
NVVIOANCPARITYCOMPUTATION ancParityComputation
Enable HW ANC parity bit computation (auto/on/off)
Definition nvapi.h:20440
float * blendingTexture
array of floating values building an intensity RGB texture
Definition nvapi.h:3654
NvU8 sourcePhysicalAddressC
Byte 2.
Definition nvapi.h:8062
_NVVIOCONFIGTYPE
Device configuration.
Definition nvapi.h:19901
NvU32 psfSignalFormat
Indicates whether contained format is PSF Signal format.
Definition nvapi.h:20398
NvU32 targetInfoCount
Number of elements in targetInfo array.
Definition nvapi.h:1021
NvU16 displayWhitePoint_y
y coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7799
NvU32 flags
One or more flags from nvcomp_gpu_top.
Definition nvapi.h:3239
NvAPI_LicenseString productName
Nvidia Grid licensable product name.
Definition nvapi.h:4129
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGB_PARAMS rgbParams
Definition nvapi.h:5788
NvU32 height
Per-display height.
Definition nvapi.h:9228
NvU32 rows
Number of rows.
Definition nvapi.h:9632
NvU32 version
Structure Version.
Definition nvapi.h:21955
NvU32 bIsNVIDIARTXProductionBranchPackage
Definition nvapi.h:22918
NvU64 reserved1
Reserved for future use.
Definition nvapi.h:4526
NvU32 numClocks
Number of populated clocks (per pstate)
Definition nvapi.h:1231
NvU64 singleBitErrors
Number of single-bit ECC errors detected since last boot.
Definition nvapi.h:3391
NvAPI_UnicodeString launcher
Indicates the name (if any) of the launcher that starts the application
Definition nvapi.h:21925
NV_DP_COLOR_FORMAT colorFormat
Current color format.
Definition nvapi.h:6535
NvU32 version
[in] Structure version
Definition nvapi.h:8779
NvU32 supportsRotation
(OUT) This display can be rotated
Definition nvapi.h:9768
enum _NVVIOINPUTOUTPUTSTATUS NVVIOINPUTOUTPUTSTATUS
Video input output status.
NvU32 version
Structure version.
Definition nvapi.h:20174
NvU32 reserved
Reserved for future use.
Definition nvapi.h:22903
NvU16 displayPrimary_x1
x coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7792
NvU32 isDynamic
if bit is set then this display is part of MST topology and it's a dynamic
Definition nvapi.h:1929
NVVIOCOMPONENTSAMPLING samplingFormat
Sampling format.
Definition nvapi.h:20035
NvU8 rsvd[28]
(IN) Reserved. Must be set to 0s.
Definition nvapi.h:17625
NvU8 phyType
This field specifies the type of PHY (NVHS or GRS) being used for this link.
Definition nvapi.h:4443
NvU32 frameLockEnable
Flag indicating whether framelock was on/off.
Definition nvapi.h:20397
NvU32 pclk
pixel clock in 10 kHz
Definition nvapi.h:662
NvU32 version
Version of the structure.
Definition nvapi.h:10359
NvU32 channel
specified (0-based) jack
Definition nvapi.h:20454
NvU8 rsvd[64]
Definition nvapi.h:22970
NvAPI_UnicodeString launcher
Indicates the name (if any) of the launcher that starts the Application.
Definition nvapi.h:21945
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7535
NvU32 licensableFeatureCount
The number of licensable features.
Definition nvapi.h:4199
NvU32 deviceMask
(IN/OUT) Device mask
Definition nvapi.h:724
NV_LICENSE_EXPIRY_DETAILS licenseExpiry
License expiry information.
Definition nvapi.h:4152
NvU32 bIsNVIDIAStudioPackage
Definition nvapi.h:22914
NvU32 psfSignalFormat
Indicates whether contained format is PSF Signal format.
Definition nvapi.h:20427
struct _NVVIOGAMMARAMP8 NVVIOGAMMARAMP8
Gamma ramp (8-bit index)
NV_DP_COLORIMETRY colorimetry
Ignored in RGB space.
Definition nvapi.h:6537
NVVIOINPUTOUTPUTSTATUS vid2Out
Video 2 output status.
Definition nvapi.h:20051
NvU32 boardID
Definition nvapi.h:20007
NV_LICENSE_FEATURE_DETAILS_V4 licenseDetails[NV_LICENSE_MAX_COUNT]
Array of licensable features.
Definition nvapi.h:4202
NvAPI_ShortString szVendorName
Chipset vendor Name.
Definition nvapi.h:22690
NvU32 immersiveGaming
Enable as immersive gaming instead of Mosaic SLI (for Quadro-boards only)
Definition nvapi.h:9636
NvU32 Value
Definition nvapi.h:5288
NvS32 defaultMinTemp
Minimum default temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4964
NvU16 hour
Hour value of license expiry.
Definition nvapi.h:4105
NvU8 colorimetry
One of NV_COLOR_COLORIMETRY enum values.
Definition nvapi.h:7392
NvU32 numRawCaptureImages
Definition nvapi.h:20461
NvU32 flags
bit 0 indicates if the dynamic Pstate is enabled or not
Definition nvapi.h:4857
NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_V1 callback
Definition nvapi.h:23112
NvU8 sourcePhysicalAddressB
Byte 1.
Definition nvapi.h:8058
float w
Width of the viewport.
Definition nvapi.h:562
NvU32 bIsNVIDIARTXNewFeatureBranchPackage
Definition nvapi.h:22920
NvU32 isEnabledByDefault
Current ECC configuration stored in non-volatile memory.
Definition nvapi.h:3507
NvU16 size
Size of this structure.
Definition nvapi.h:7345
NVVIOINPUTCONFIG inConfig
Input device configuration.
Definition nvapi.h:20504
NvU32 supports_2160p60hz
If set sink is capable of 4kx2k @ 60hz.
Definition nvapi.h:7555
struct _NV_GPU_CLIENT_UTILIZATION_DATA_V1 NV_GPU_CLIENT_UTILIZATION_DATA_V1
NvU8 hdmiVicLength
Byte 11.
Definition nvapi.h:8095
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7435
NvU32 smpte352
4-byte SMPTE 352 video payload identifier
Definition nvapi.h:20032
NvU32 targetInfoCount
Number of elements in targetInfo array.
Definition nvapi.h:1003
NvU32 version
Structure version.
Definition nvapi.h:20069
enum _NVVIOOWNERTYPE NVVIOOWNERTYPE
Owner type for device.
struct _NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_V1 NV_GPU_CLIENT_UTILIZATION_PERIODIC_CALLBACK_SETTINGS_V1
NvAPI_UnicodeString userFriendlyName
UserFriendly name of the Application.
Definition nvapi.h:21944
NvU32 flags
Definition nvapi.h:4679
NvU32 displayMask
The Display Mask of the concerned display.
Definition nvapi.h:2922
NvU16 full_frame_peak_luminance_index
Full frame peak luminance index.
Definition nvapi.h:7582
NvU8 supportVRR
monitor supports variable refresh rate. Valid for NV_MONITOR_CAPS_TYPE_GENERIC only.
Definition nvapi.h:8103
NV_DISPLAYCONFIG_SPANNING_ORIENTATION spanningOrientation
Spanning is only supported on XP.
Definition nvapi.h:988
NvU32 interval
Number of pulses to wait between framelock signal generation.
Definition nvapi.h:10339
NvU32 settingId
32 bit setting Id
Definition nvapi.h:21889
void * pOSAdapterId
[out] Returns OS-AdapterId. User must send memory buffer of size atleast equal to the size of LUID st...
Definition nvapi.h:4027
NvU32 defaultMinTemp
The min default temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4948
NvU32 currentTemp
The current temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4950
NvS32 min
Min value allowed for parameter delta (in respective units [kHz, uV])
Definition nvapi.h:1151
NV_GPU_PERF_PSTATE_ID pstateId
ID of the P-State.
Definition nvapi.h:1284
NV_MOSAIC_GRID_TOPO_DISPLAY_V2 displays[NV_MOSAIC_MAX_DISPLAYS]
Displays are done as [(row * columns) + column].
Definition nvapi.h:9658
NvS32 overlapX
(+overlap, -gap)
Definition nvapi.h:9596
NvU32 isLicenseSupported
True if Software Licensing is supported.
Definition nvapi.h:4164
NvU32 refreshRate
The refresh rate.
Definition nvapi.h:10524
_NVVIOINPUTOUTPUTSTATUS
Video input output status.
Definition nvapi.h:19827
NvU32 houseSyncIncoming
Incoming house sync frequency in Hz.
Definition nvapi.h:10527
NvAPI_ShortString szSubSysVendorName
subsystem vendor Name
Definition nvapi.h:22713
NvU8 remoteDeviceLinkNumber
This field specifies the link number on the remote end of the link.
Definition nvapi.h:4436
NvU32 bDisableFrameSplitting
[out] Indicates if frame splitting is disabled on the display.
Definition nvapi.h:8595
NvU32 nvPsfId
Definition nvapi.h:7963
struct _NVVIODATAFORMATDETAIL NVVIODATAFORMATDETAIL
Data format details.
NvU32 fields
Caller sets to NVVIOCONFIG_* mask for fields to use.
Definition nvapi.h:20500
NvU32 reserved
Reserved.
Definition nvapi.h:6678
NvU32 displayCount
(OUT) The number of valid entries in the displays array.
Definition nvapi.h:9761
NvU32 isST2084EotfSupported
HDMI2.0a UHDA HDR with ST2084 EOTF (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7423
NvPhysicalGpuHandle hPhysicalGPU
Physical GPU to be used in the topology (0 if GPU missing)
Definition nvapi.h:9097
#define NVAPI_MAX_VIO_DEVICES
Assumption, maximum 4 SDI input and 4 SDI output cards supported on a system.
Definition nvapi.h:19862
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7652
NvU32 flipQueueLength
Number of buffers used for the internal flip queue.
Definition nvapi.h:20432
NvU32 flags
Chipset info flags - obsolete.
Definition nvapi.h:22710
NvU32 version
Version of the structure.
Definition nvapi.h:10471
NvU32 numPstates
The number of available p-states.
Definition nvapi.h:4666
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7789
NVVIODATAFORMAT dataFormat
Data format enumerated value.
Definition nvapi.h:20167
enum _NVVIOVIDEOSTANDARD NVVIOVIDEOSTANDARD
SMPTE standards format.
NvU16 size
Size of this structure.
Definition nvapi.h:7333
NVVIOCHANNELSTATUS vidIn[NVAPI_MAX_VIO_JACKS][NVAPI_MAX_VIO_CHANNELS_PER_JACK]
Video input status per channel within a jack.
Definition nvapi.h:20043
NvU16 month
Month value of license expiry.
Definition nvapi.h:4103
NvU16 size
Size of this structure.
Definition nvapi.h:7358
NvU32 RJ45_Ethernet[NVAPI_MAX_RJ45_PER_GSYNC]
Connected to ethernet hub? [ERRONEOUSLY CONNECTED!].
Definition nvapi.h:10526
NvU16 cc_blue_y
Blue primary chromaticity coordinate y.
Definition nvapi.h:7574
NVAPI_GSYNC_VIDEO_MODE vmode
None, TTL, NTSCPALSECAM, HDTV.
Definition nvapi.h:10338
NvU16 desired_content_min_luminance
Minimum display luminance = desired min luminance of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7483
NvU32 bIsPresent
Set if this utilization domain is present on this GPU.
Definition nvapi.h:4860
NvU8 highestNciVersion
This field specifies the highest supported NCI version for this GPU.
Definition nvapi.h:4276
NvU32 backlt_min_luma
It is the level for Backlt min luminance value (reserved = 0x3 in latest DV spec).
Definition nvapi.h:7560
enum _NVVIOSYNCSTATUS NVVIOSYNCSTATUS
Synchronization input status.
NvU32 isCluster
if bit is set then this display is the representative display
Definition nvapi.h:1934
NvU32 interlaceMode
interlace mode for a Sync device
Definition nvapi.h:10364
NvU32 reserved
Reserved for future use without adding versioning.
Definition nvapi.h:8781
NV_MOSAIC_DISPLAY_SETTING_V1 displaySettings[NV_MOSAIC_DISPLAY_SETTINGS_MAX]
List of per display settings possible.
Definition nvapi.h:9259
NvU32 isMonAdobeYCC601Capable
if AdobeYCC601 extended colorimetry is supported
Definition nvapi.h:6696
NvU32 reserved
Should be set to ZERO.
Definition nvapi.h:10208
NvU32 reserved
Reserved.
Definition nvapi.h:4198
NvU16 VSyncWidth
vertical sync width
Definition nvapi.h:657
NvU32 isGpuHDMICapable
If the GPU can handle HDMI.
Definition nvapi.h:6670
NvU32 isFeatureEnabled
The current state of feature, true=enabled, false=disabled.
Definition nvapi.h:4147
NvU32 numLines
delay to be induced in number of horizontal lines.
Definition nvapi.h:10325
struct _NVVIOCAPS NVVIOCAPS
Device capabilities.
NvU8 localDeviceLinkNumber
This field specifies the link number on the local end of the link.
Definition nvapi.h:4460
NvU32 colCount
Vertical display count.
Definition nvapi.h:9938
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7684
NvU32 isInternalDp
If the monitor is driven by an NV Dp transmitter.
Definition nvapi.h:6540
NvU32 reserved
Reserved for future use.
Definition nvapi.h:10138
NV_POSITION position
Definition nvapi.h:985
NvU32 isEdrSupported
Extended Dynamic Range on SDR displays. Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7521
NvU32 version
Structure Version.
Definition nvapi.h:21864
NvU32 minFreq_kHz
Min clock frequency within given pstate in (kHz)
Definition nvapi.h:1186
NvU32 x
Horizontal origin in pixels.
Definition nvapi.h:20084
NvU32 connected
This field specifies if any device is connected on the other end of the link.
Definition nvapi.h:4455
enum _NVVIOCOMPSYNCTYPE NVVIOCOMPSYNCTYPE
Composite synchronization type.
NVVIOCONFIGTYPE nvvioConfigType
Input or Output configuration.
Definition nvapi.h:20489
_NVVIOVIDEOTYPE
HD or SD video type.
Definition nvapi.h:19758
NvU32 version
Structure version.
Definition nvapi.h:8534
NV_GPU_PERF_PSTATE_ID pstateId
ID of the p-state.
Definition nvapi.h:4671
#define NVAPI_MAX_VIO_STREAMS
4 Streams, 1 per physical jack
Definition nvapi.h:19875
NvU32 compositeTerminate
Composite termination.
Definition nvapi.h:20372
NvU32 warningFlags
(OUT) Any of the NV_MOSAIC_DISPLAYTOPO_WARNING_* flags.
Definition nvapi.h:9759
NVDRS_BINARY_SETTING binaryValue
All possible Binary values for a setting.
Definition nvapi.h:21877
NvU16 desired_content_max_luminance
Maximum display luminance = desired max luminance of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7482
NvU32 reserved
must be zero
Definition nvapi.h:1941
NvU32 vblankIntervalUs
(IN) Interval between VBLANKs in microseconds. (0 means N/A)
Definition nvapi.h:17622
NvU32 pciDomain
specifies the PCI domain of the GVI device.
Definition nvapi.h:20851
NV_GPU_CLIENT_CALLBACK_DATA_SUPER_V1 super
Definition nvapi.h:23064
NvU32 version
Version of this structure.
Definition nvapi.h:7517
NvU32 isTraditionalSdrGammaSupported
HDMI2.0a traditional SDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7428
NvU8 nvlinkVersion
This field specifies the NVLink version supported by the link.
Definition nvapi.h:4426
struct _NVVIOSIGNALFORMATDETAIL NVVIOSIGNALFORMATDETAIL
Signal format details.
NvU32 version
Version of this structure.
Definition nvapi.h:9226
NV_GPU_HDCP_KEY_SOURCE_STATE hdcpKeySourceState
GPU's HDCP key source.
Definition nvapi.h:3196
NvU32 bIsDCHDriver
Definition nvapi.h:22891
NvU32 reserved
Reserved, must be 0.
Definition nvapi.h:9657
NvAPI_UnicodeString commandLine
Definition nvapi.h:21965
NvU32 reserved
Reserved.
Definition nvapi.h:4148
NvU32 vioId
device Id of SDI Input/Output device
Definition nvapi.h:20521
NvU32 reserved1
These bits are reserved.
Definition nvapi.h:5057
NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO * details
May be NULL if no advanced settings are required. NULL for Non-NVIDIA Display.
Definition nvapi.h:955
NvU16 uBlue[256]
Blue channel gamma ramp (8-bit index, 16-bit values)
Definition nvapi.h:20095
NvU32 subSysVendorId
Chipset subsystem vendor identification.
Definition nvapi.h:22693
NvU32 isWFD
Deprecated. Will always return 0.
Definition nvapi.h:1936
NvU8 nciVersion
This field specifies the NCI version supported by the link.
Definition nvapi.h:4449
NvU32 isMonxvYCC601Capable
If xvYCC extended colorimetry 601 is supported.
Definition nvapi.h:6692
NvU32 driverVersion
Contains the driver version after successful return.
Definition nvapi.h:22909
NvS32 overlapX
Pixels of overlap on left of target: (+overlap, -gap)
Definition nvapi.h:9099
NvU32 callbackPeriodms
Definition nvapi.h:22992
NvU32 reserved
Reserved.
Definition nvapi.h:4117
NVVIOSYNCDELAY syncDelay
Sync delay.
Definition nvapi.h:20424
NvU16 displayWhitePoint_y
y coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7480
NvU32 reserved[8]
Reserved for future use. Should be set to ZERO.
Definition nvapi.h:4036
NvU32 immersiveGaming
Enable as immersive gaming instead of Mosaic SLI (for Quadro-boards only)
Definition nvapi.h:9652
NvU16 desired_content_min_luminance
Minimum display luminance = desired min luminance of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7448
NvU32 version
structure version
Definition nvapi.h:4943
union _NVVIOGAMMACORRECTION::@62 gammaRamp
Gamma correction:
NvU32 bGDIPrimary
(IN/OUT) Indicates if this is the desktop GDI primary.
Definition nvapi.h:729
NvU16 VBorder
vertical border
Definition nvapi.h:655
NvU8 subLinkWidth
This field specifies the no. of lanes per sublink.
Definition nvapi.h:4422
NVVIOCOLORCONVERSION colorConversion
Color conversion.
Definition nvapi.h:20363
float colorMatrix[3][3]
Output[n] =.
Definition nvapi.h:20175
NV_STATIC_METADATA_DESCRIPTOR_ID static_metadata_descriptor_id
Static Metadata Descriptor Id (0 for static metadata type 1)
Definition nvapi.h:7466
NvU32 enableFullColorRange
Flag indicating Full Color Range.
Definition nvapi.h:20438
NvU32 version
(IN) Structure version
Definition nvapi.h:17531
NvU32 reserved
Definition nvapi.h:7464
NvU32 version
version of this structure
Definition nvapi.h:3651
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7436
NvU16 uGreen[1024]
Green channel gamma ramp (10-bit index, 16-bit values)
Definition nvapi.h:20102
NV_HDR_MODE hdrMode
HDR mode.
Definition nvapi.h:7675
NvU16 sec
Seconds value of license expiry.
Definition nvapi.h:4107
NvU32 frameIntervalUs
[out] frame interval in micro seconds if Virtual RR is currently applied
Definition nvapi.h:8671
enum _NVVIOSYNCSOURCE NVVIOSYNCSOURCE
Synchronization source.
NvU16 cc_red_x
Red primary chromaticity coordinate x.
Definition nvapi.h:7569
NvU16 cc_green_x
Green primary chromaticity coordinate x.
Definition nvapi.h:7571
NvU32 frequency
Clock frequency (kHz)
Definition nvapi.h:5062
NV_DYNAMIC_RANGE hdrDynamicRange
Optional, One of NV_DYNAMIC_RANGE enum values, if set it will apply requested dynamic range for HDR s...
Definition nvapi.h:7700
NVVIOCONFIGTYPE nvvioConfigType
Input or Output configuration.
Definition nvapi.h:20501
NvU8 colorimetry
One of NV_COLOR_COLORIMETRY enum values.
Definition nvapi.h:7350
NvU32 u32DefaultValue
Accessing default DWORD value of this setting.
Definition nvapi.h:21869
NvU16 day
Day value of license expiry.
Definition nvapi.h:4104
NvU8 cmd
The actions to perform from NV_INFOFRAME_CMD.
Definition nvapi.h:7195
NvU32 isSetDeferred
Requires an OS modeset to finalize the setup if set.
Definition nvapi.h:6639
NvU32 flagsRsvd
(IN) Reserved flag bits. Must be set to 0s.
Definition nvapi.h:17621
float * blendingTexture
array of floating values building an intensity RGB texture
Definition nvapi.h:3645
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_RGBW_PARAMS rgbwParams[NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS]
Definition nvapi.h:6019
NvU32 numStreams
Number of active streams.
Definition nvapi.h:20465
NvU32 colorimetry
If set indicates sink supports DCI P3 colorimetry, REc709 otherwise.
Definition nvapi.h:7558
NvU32 version
Unused.
Definition nvapi.h:4145
NV_GPU_ILLUMINATION_ATTRIB Attribute
Definition nvapi.h:5218
NvU32 cscOverride
Use provided CSC color matrix to overwrite.
Definition nvapi.h:20431
NvU32 edidId
Definition nvapi.h:321
NvU32 reserved
reserved for future use.
Definition nvapi.h:8596
NvU32 version
Definition nvapi.h:5478
NvAPI_ShortString szVendorName
vendor Name
Definition nvapi.h:22708
NvU32 version
Structure version.
Definition nvapi.h:6529
NvU8 hasVicEntries
Byte 5.
Definition nvapi.h:8079
NvU32 driverExpandDefaultHdrParameters
Definition nvapi.h:7522
struct _NVVIOSTATUS NVVIOSTATUS
Video device status.
NvU32 numIllumDevices
Definition nvapi.h:5483
NvU32 version
Version of the structure.
Definition nvapi.h:10336
NvU32 dm_version
Upper Nibble represents major version of Display Management(DM) while lower represents minor version ...
Definition nvapi.h:7490
NV_DP_LINK_RATE linkRate
Link rate.
Definition nvapi.h:6632
NvAPI_LicenseString productName
Nvidia Grid licensable product name.
Definition nvapi.h:4140
NvU8 supportDeepColor48bits
Byte 3.
Definition nvapi.h:8069
NvU32 driverReloadAllowed
If necessary, reloading the driver is permitted (for Vista and above only). Will not be persisted....
Definition nvapi.h:9638
NvU32 version
Structure Version.
Definition nvapi.h:21930
NvU8 sourcePhysicalAddressA
Byte 1.
Definition nvapi.h:8059
NvU32 vioTotalDeviceCount
How many video I/O targets are valid.
Definition nvapi.h:20529
NvU32 version
structure version
Definition nvapi.h:22723
NV_GPU_CLIENT_PERIODIC_CALLBACK_SETTINGS_SUPER_V1 super
Definition nvapi.h:23107
NvU8 sourcePhysicalAddressD
Byte 2.
Definition nvapi.h:8061
NvU16 HVisible
horizontal visible
Definition nvapi.h:647
NvU16 displayWhitePoint_y
y coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7661
NvU16 cc_green_y
Green primary chromaticity coordinate Y.
Definition nvapi.h:7572
NvU32 reserved
Reserved.
Definition nvapi.h:4176
NvU32 isYCrCb422Supported
If YCrCb422 is supported.
Definition nvapi.h:6548
NvU8 colorFormat
One of NV_COLOR_FORMAT enum values.
Definition nvapi.h:7362
NVAPI_GSYNC_MULTIPLY_DIVIDE_MODE multiplyDivideMode
Definition nvapi.h:10370
NV_GPU_WARPING_VERTICE_FORMAT vertexFormat
format of the input vertices
Definition nvapi.h:3738
NvU32 syncEnable
Sync enable (TRUE to use syncSource)
Definition nvapi.h:20365
NvU32 status
Timing standard.
Definition nvapi.h:611
NvU32 freq
Display frequency.
Definition nvapi.h:9221
NvU32 isMonYCbCr422Capable
If YCbCr 4:2:2 is supported.
Definition nvapi.h:6674
NvAPI_ShortString szBuildBranch
Contains the driver-branch string after successful return.
Definition nvapi.h:22910
NvU8 * pbI2cRegAddress
Definition nvapi.h:2970
NvU32 reserved
Must be 0.
Definition nvapi.h:1025
NvU32 version
(IN) structure version
Definition nvapi.h:720
NvU32 syncEnable
Sync enable (TRUE to use syncSource)
Definition nvapi.h:20422
NvU32 dataIntegrityCheckEnabled
Data integrity check status enabled.
Definition nvapi.h:20060
NvU8 i2cDevAddress
Definition nvapi.h:2925
NvU32 refreshRate
The refresh rate.
Definition nvapi.h:10534
NvU8 signature[NV_LICENSE_SIGNATURE_SIZE]
Definition nvapi.h:4178
float x
x-coordinate of the viewport top-left point
Definition nvapi.h:560
NvU32 minorVersion
Minor version. In version 2, for both GVI and GVO, minorVersion contains Revison(HIWORD) And Build(LO...
Definition nvapi.h:20018
NvU32 displayId
this is a unique identifier for each device
Definition nvapi.h:1927
NvU8 txSublinkStatus
This field specifies the current state of TX sublink.See NVAPI_NVLINK_GET_NVLINK_STATUS_SUBLINK_TX_ST...
Definition nvapi.h:4447
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7540
NvU8 * pbData
The buffer of data which is to be read or written (depending on the command).
Definition nvapi.h:2974
NvU32 rows
Number of rows.
Definition nvapi.h:9648
NvU32 bIsNVIDIAGameReadyPackage
Definition nvapi.h:22896
NvU8 signature[NV_LICENSE_SIGNATURE_SIZE]
Definition nvapi.h:4167
NvAPI_UnicodeString appName
String name of the Application.
Definition nvapi.h:21932
NvU32 isYCrCb420Supported
If YCrCb420 is supported.
Definition nvapi.h:6547
NVVIOCOMPOSITERANGE compRange
Composite ranges.
Definition nvapi.h:20379
NvU32 ceaId
Definition nvapi.h:7960
NvU32 maxFrameInterval
Definition nvapi.h:8592
NvU32 syncSourceIsOutput
Definition nvapi.h:10342
NV_GSYNC_DELAY startupDelay
Sync start delay for master.
Definition nvapi.h:10346
NVVIOSYNCSTATUS compSyncIn
Composite sync input status.
Definition nvapi.h:20053
NvAPI_ShortString szChipsetName
Chipset device Name.
Definition nvapi.h:22691
NvU32 isChromaLpfOff
Force the chroma low_pass_filter to be off.
Definition nvapi.h:6640
NvU32 bDisableFrameSplitting
[in] Indicates if Frame Splitting should be disabled.
Definition nvapi.h:8635
float colorOffset[3]
Input[0] * colorMatrix[n][0] +.
Definition nvapi.h:20176
NvU32 reserved
Reserved.
Definition nvapi.h:6698
NV_PIXEL_SHIFT_TYPE pixelShiftType
Type of the pixel shift enabled display.
Definition nvapi.h:9620
NvBool bSync
Definition nvapi.h:5530
NvU8 interlacedVideoLatency
Byte 8.
Definition nvapi.h:8087
NvU8 multiplyDivideValue
Definition nvapi.h:10372
NvU16 displayWhitePoint_x
x coordinate of white point of the display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7479
NvU32 bIsSyncSignalAvailable
Is the sync signal available?
Definition nvapi.h:10474
NvU32 version
Structure Version.
Definition nvapi.h:22908
NvU32 enableANCTimeCodeGeneration
Enable SDI ANC time code generation.
Definition nvapi.h:20433
NVVIOCOMPOSITERANGE compRange
Composite ranges.
Definition nvapi.h:20407
NvU32 count
number of associated thermal sensors
Definition nvapi.h:4960
NvU32 isActive
if bit is set then this display is being actively driven
Definition nvapi.h:1933
NvU32 numLinks
Number of active links.
Definition nvapi.h:20450
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7474
float * offsetTexture
array of floating values building an offset texture
Definition nvapi.h:3655
NVVIODATAFORMAT dataFormat
Data format for video output.
Definition nvapi.h:20417
NvU32 reserved
Reserved for future use.
Definition nvapi.h:10541
NvU32 bEnabled
warping is enabled or not
Definition nvapi.h:3777
NVVIOGAMMARAMP8 gammaRamp8
Gamma ramp (8-bit index, 16-bit values)
Definition nvapi.h:20197
NvU32 bIsPresent
Set if this domain is present on this GPU.
Definition nvapi.h:5060
void * callbackParam
This value will be passed back to the callback function when an event occurs.
Definition nvapi.h:3587
NvU32 maxFrameInterval
Definition nvapi.h:8632
NvU32 supports_backlight_control
This is set when sink is using lowlatency interface and can control its backlight.
Definition nvapi.h:7559
NV_LICENSE_FEATURE_TYPE featureCode
Feature code that corresponds to the licensable feature.
Definition nvapi.h:4149
NvPhysicalGpuHandle hPhysicalGPU
Physical GPU to be used in the topology.
Definition nvapi.h:9942
union _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_SINGLE_COLOR::@35 data
NvU32 version
Version of this structure.
Definition nvapi.h:9613
NV_VIRTUALIZATION_MODE virtualizationMode
one of NV_VIRTUALIZATION_MODE.
Definition nvapi.h:3986
NvU32 driverReloadAllowed
If necessary, reloading the driver is permitted (for Vista and above only). Will not be persisted....
Definition nvapi.h:9654
NVVIOVIDEOMODE videoMode
Video mode for signal format.
Definition nvapi.h:20134
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7441
NvU8 provIdx
Definition nvapi.h:5677
NV_MOSAIC_TOPO topo
The topology.
Definition nvapi.h:9203
NVVIOOUTPUTCONFIG_V2 outConfig
Output device configuration.
Definition nvapi.h:20493
NvU32 flags
Reserved. Must be set to 0.
Definition nvapi.h:4633
NvU32 isMonxvYCC601Capable
If xvYCC 601 is supported.
Definition nvapi.h:6675
NvU8 rsvd[64]
Definition nvapi.h:5718
NvU16 cc_green_y
Green primary chromaticity coordinate Y.
Definition nvapi.h:7506
_NVVIOSYNCSTATUS
Synchronization input status.
Definition nvapi.h:19836
NvAPI_UnicodeString wszDefaultValue
Accessing default unicode string value of this setting.
Definition nvapi.h:21872
NvU32 reserved
Reserved.
Definition nvapi.h:4137
NvU32 lastFlipRefreshCount
[out] Number of times the last flip was shown on the screen
Definition nvapi.h:8597
NV_GPU_CLIENT_ILLUM_DEVICE_TYPE type
Definition nvapi.h:5438
NvU32 majorVersion
Major version. In version 2, for both GVI and GVO, majorVersion contains MajorVersion(HIWORD) And Min...
Definition nvapi.h:20017
NvU32 uPowerOn
TRUE: indicates there is sufficient power.
Definition nvapi.h:20063
NvU8 supportULMB
monitor supports ULMB with variable refresh rate. Valid for NV_MONITOR_CAPS_TYPE_GENERIC only.
Definition nvapi.h:8104
NvU32 isEnabled
Active ECC memory setting.
Definition nvapi.h:3373
NvU32 frequency
Clock frequency (kHz)
Definition nvapi.h:5032
NvU32 gpuCount
Total number of compute-capable GPUs.
Definition nvapi.h:3234
NvU32 displayId
display identifier for displays.The GPU to which it is connected, can be retireved from NvAPI_SYS_Get...
Definition nvapi.h:10214
NvU32 targetId
Windows CCD target ID. Must be present only for non-NVIDIA adapter, for NVIDIA adapter this parameter...
Definition nvapi.h:963
NvU32 regAddrSize
Definition nvapi.h:2931
enum _NVVIOINTERLACEMODE NVVIOINTERLACEMODE
Interlace mode.
NvS32 timeInQueueUs
(IN) Amount of time in the completed frame queue. Can be negative. (0 means N/A)
Definition nvapi.h:17623
NvU32 is16BPCSupported
If 16 bpc is supported.
Definition nvapi.h:6546
NvU32 displaySettingsCount
Number of display settings in below array.
Definition nvapi.h:9268
NvU32 y
Vertical origin in pixels.
Definition nvapi.h:20085
NvU32 nvlinkLineRateMbps
Bit rate at which bits toggle on wires in megabits per second.
Definition nvapi.h:4462
NV_BPC bpc
One of NV_BPC enum values.
Definition nvapi.h:7394
NvU32 compositeSafe
compositeSafe constrains luminance range when using composite output
Definition nvapi.h:20183
NVAPI_GSYNC_VIDEO_MODE vmode
None, TTL, NTSCPALSECAM, HDTV.
Definition nvapi.h:10361
enum _NVVIOCAPTURESTATUS NVVIOCAPTURESTATUS
Video Capture Status.
NvU8 nvlinkVersion
This field specifies the NVLink version supported by the link.
Definition nvapi.h:4448
NvU32 bIsPortIdSet
set this flag on if and only if portid value is set
Definition nvapi.h:2980
NVVIOPCILINKWIDTH pciLinkWidth
specifies the the negotiated PCIE link width.
Definition nvapi.h:20854
NvU8 phyVersion
This field specifies the version of PHY being used by the link.
Definition nvapi.h:4428
NvU32 subSysVendorId
subsystem vendor ID
Definition nvapi.h:22711
NvU32 version
Structure Version.
Definition nvapi.h:21921
NvU32 offsetTexChannels
number of channels per pixel in the offset texture
Definition nvapi.h:3656
NV_COMPUTE_GPU * computeGpus
Array of compute-capable physical GPUs (allocate memory of size of Physical gpuCount of system).
Definition nvapi.h:3257
NvU32 numIllumDevices
Definition nvapi.h:5579
NVDRS_SETTING_TYPE settingType
Type of setting value.
Definition nvapi.h:21890
NvVioHandle hVioHandle
handle to SDI Input/Output device
Definition nvapi.h:20520
NvU32 horizontalPixels
Horizontal resolution (in pixels)
Definition nvapi.h:20122
NvU8 * pbI2cRegAddress
Definition nvapi.h:2929
NvU32 isPredefinedValid
It is different than 0 if the PredefinedValue union contains a valid value.
Definition nvapi.h:21894
NVVIOSTATUSTYPE nvvioStatusType
Input or Output status.
Definition nvapi.h:20070
NvU32 version
Structure version.
Definition nvapi.h:6685
NvU32 gpuActiveRenderTimeUs
(OUT) Difference between gpuRenderStartTime and gpuRenderEndTime, excluding the idles in between,...
Definition nvapi.h:17676
NvU32 displayOutputId
Connected display target.
Definition nvapi.h:9943
NvU32 reservedEx[4]
Reserved for future use.
Definition nvapi.h:9019
NvS32 max
Max value allowed for parameter delta (in respective units [kHz, uV])
Definition nvapi.h:1154
NVVIOINPUTSTATUS inStatus
Input device status.
Definition nvapi.h:20073
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1246
NvU32 version
Unused.
Definition nvapi.h:4124
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7796
NvU32 version
The structure version.
Definition nvapi.h:2941
NVVIOSYNCSOURCE syncSource
Sync source.
Definition nvapi.h:20423
NvU8 colorimetry
One of NV_COLOR_COLORIMETRY enum values.
Definition nvapi.h:7377
NvU32 version
structure version
Definition nvapi.h:22705
NvU64 timeStampms
Definition nvapi.h:5535
NvU32 version
Structure Version.
Definition nvapi.h:21941
NvU8 hasLatencyField
Byte 5.
Definition nvapi.h:8081
NvU32 isFeatureEnabled
The current state of feature, true=enabled, false=disabled.
Definition nvapi.h:4136
NvU32 displayId
Display ID.
Definition nvapi.h:961
NV_ROTATE rotation
(IN) rotation setting.
Definition nvapi.h:907
NvU8 hdmi_3d[31]
Keeping maximum length for 5 bits.
Definition nvapi.h:8098
NvU32 height
height of the input texture
Definition nvapi.h:3644
NV_ECC_CONFIGURATION configurationOptions
Supported ECC memory feature configuration options.
Definition nvapi.h:3372
NV_SCALING scaling
(IN) Scaling setting
Definition nvapi.h:800
NvU32 flag
Reserved for NVIDIA hardware-based enhancement, such as double-scan.
Definition nvapi.h:606
NvS32 overlapX
Pixels of overlap on the left of target: (+overlap, -gap)
Definition nvapi.h:9944
NvU32 bpp
Bits per pixel.
Definition nvapi.h:9220
NVVIOVIDEOSTANDARD videoStandard
SMPTE standards format.
Definition nvapi.h:20126
NvU16 cc_red_y
Red primary chromaticity coordinate y.
Definition nvapi.h:7570
NvAPI_UnicodeString appName
String name of the Application.
Definition nvapi.h:21957
NV_GPU_CLIENT_ILLUM_PIECEWISE_LINEAR_CYCLE_TYPE cycleType
Definition nvapi.h:5801
NvU32 refreshRate
(IN) Refresh rate of the mode
Definition nvapi.h:803
NvU8 cnc3SupportGameContent
Byte 5.
Definition nvapi.h:8077
NvU32 bIsNVIDIARTXNewFeatureBranchPackage
Definition nvapi.h:22900
NvU32 bSupported
A boolean indicating if the attribute is supported.
Definition nvapi.h:5157
NvU32 enableRGBData
Indicates data is in RGB format.
Definition nvapi.h:20382
NVVIOOUTPUTAREA outputArea
Usable resolution for video output (safe area)
Definition nvapi.h:20362
NvU32 count
number of associated thermal sensors
Definition nvapi.h:4944
NvU32 version
Structure version.
Definition nvapi.h:20499
NVVIOCOMPSYNCTYPE compositeSyncType
Composite sync type.
Definition nvapi.h:20425
NvU32 version
IN - Structure version.
Definition nvapi.h:4163
NvU32 version
Structure version.
Definition nvapi.h:3388
NV_GPU_PERF_PSTATE20_CLOCK_TYPE_ID typeId
Clock type ID.
Definition nvapi.h:1165
enum _NVVIOSIGNALFORMAT NVVIOSIGNALFORMAT
Video signal format and resolution.
NvU32 reserved
Reserved for future use without adding versioning.
Definition nvapi.h:8741
NvU32 capsTbl
This is bit field for getting different global caps.The individual bitfields are specified by NVAPI_N...
Definition nvapi.h:4442
NvBool bCplVsyncOn
(OUT) Is Control Panel overriding VSYNC ON?
Definition nvapi.h:17488
NvU32 displayId
[out] The queried stereo display
Definition nvapi.h:8780
NvAPI_LicenseString licenseInfo
Deprecated.
Definition nvapi.h:4139
NV_GPU_CLIENT_UTIL_DOMAIN_ID utilId
Definition nvapi.h:23041
NvU16 cc_white_x
White primary chromaticity coordinate x.
Definition nvapi.h:7575
NvU32 isHdr10PlusSupported
HDR10+ (Sink Side Tonemapping) is supported.
Definition nvapi.h:7526
NvU32 revision
FPGA Revision.
Definition nvapi.h:10117
NvU32 bIsDCHDriver
Definition nvapi.h:22911
NvU32 version
(IN) structure version
Definition nvapi.h:7973
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7651
NvU32 revision
revision and revision_id are the same. The former is NvU32 while the latter is an enum made for reada...
Definition nvapi.h:2855
NvU32 baseMosaic
Enable as Base Mosaic (Panoramic) instead of Mosaic SLI (for NVS and Quadro-boards only)
Definition nvapi.h:9653
NvU32 isCurrentPredefined
Definition nvapi.h:21892
NvU16 uRed[256]
Red channel gamma ramp (8-bit index, 16-bit values)
Definition nvapi.h:20093
struct _NVVIOCOLORCONVERSION NVVIOCOLORCONVERSION
Colorspace conversion.
NvU32 rrx1k
Physical vertical refresh rate in 0.001Hz.
Definition nvapi.h:608
NvU32 numPstates
Number of populated pstates.
Definition nvapi.h:1228
NvAPI_UnicodeString launcher
Indicates the name (if any) of the launcher that starts the Application.
Definition nvapi.h:21934
NvU32 flipQueueLength
Number of buffers used for the internal flipqueue.
Definition nvapi.h:20375
NvU32 flags
Definition nvapi.h:4642
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_COLOR_FIXED_PARAMS colorFixedParams[NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS]
Definition nvapi.h:5925
NvU8 interlacedAudioLatency
Byte 9.
Definition nvapi.h:8089
NV_GPU_CLIENT_ILLUM_ZONE_LOCATION zoneLocation
Definition nvapi.h:5682
NvU32 version
The structure version.
Definition nvapi.h:2921
NvU32 interlaced
(IN) Interlaced mode flag
Definition nvapi.h:804
enum _NVVIOSTATUSTYPE NVVIOSTATUSTYPE
Video Capture Status.
NvU32 licensableFeatureCount
The number of licensable features.
Definition nvapi.h:4177
NvU32 cloneGroup
Reserved, must be 0.
Definition nvapi.h:9619
NvU32 reserved
should be set zero
Definition nvapi.h:10344
NvU32 version
Version of this structure.
Definition nvapi.h:9255
NvU32 reservedEx[8]
reserved for future use.
Definition nvapi.h:8672
NVVIOCOMPSYNCTYPE compositeSyncType
Composite sync type.
Definition nvapi.h:20368
NvU32 displayId
DisplayID of the display.
Definition nvapi.h:9595
NvU32 isDolbyVisionSupported
Dolby Vision Support. Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7463
NvU32 version
[in] structure version
Definition nvapi.h:8670
NvU8 rsvd[64]
Definition nvapi.h:5488
NvU32 pciDeviceId
specifies the internal PCI device identifier for the GVI.
Definition nvapi.h:20848
NvU32 capFlags
Capabilities of the Sync board. Reserved for future use.
Definition nvapi.h:10135
NvU32 linkMask
This field provides a bitfield mask of NVLink links enabled on this GPU.
Definition nvapi.h:4277
NvU32 version
The structure version.
Definition nvapi.h:2962
NVVIOOUTPUTSTATUS outStatus
Output device status.
Definition nvapi.h:20074
NvU8 dynamicRange
One of NV_DYNAMIC_RANGE enum values.
Definition nvapi.h:7364
NvU32 isPredefined
Is the application userdefined/predefined.
Definition nvapi.h:21956
NvU32 reserved0
Reserved for future use.
Definition nvapi.h:4525
NvU8 rsvd[64]
Definition nvapi.h:23080
NvU8 status
License expiry status.
Definition nvapi.h:4109
NvU16 target_min_luminance
Represents min luminance level of Sink.
Definition nvapi.h:7567
NvU32 isMonUnderscanCapable
If the monitor supports underscan.
Definition nvapi.h:6671
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7538
NV_BPC bpc
One of NV_BPC enum values.
Definition nvapi.h:7365
NvU32 compositeTerminate
Composite termination.
Definition nvapi.h:20400
enum _NVVIOOUTPUTAREA NVVIOOUTPUTAREA
Video output area.
NvPhysicalGpuHandle physicalGpuHandles[NVAPI_MAX_PHYSICAL_GPUS]
Definition nvapi.h:4030
NvU32 NVVIOOWNERID
Definition nvapi.h:19616
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7477
NVVIOCOMPSYNCTYPE compositeSyncType
Composite sync type.
Definition nvapi.h:20396
NvU32 version
Version of this structure. Must always be first element in this structure.
Definition nvapi.h:4468
NVDRS_SETTING_TYPE settingType
Type of setting value.
Definition nvapi.h:21866
NV_GPU_CLIENT_UTILIZATION_DATA_V1 utils[NV_GPU_CLIENT_UTIL_DOMAINS_MAX_V1]
Definition nvapi.h:23085
NvU32 rowCount
Horizontal display count.
Definition nvapi.h:9937
NvU32 reserved
Reserved.
Definition nvapi.h:4165
NvS32 currentTemp
Current temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4966
NvU32 reserved
Reserved.
Definition nvapi.h:4187
NvU32 version
Structure version.
Definition nvapi.h:3255
NvU32 isHdr10PlusGamingSupported
HDR10+ Gaming, a.k.a HDR10+ Source Side Tonemapping (SSTM), is supported.
Definition nvapi.h:7527
NV_GPU_HDCP_FUSE_STATE hdcpFuseState
Structure version constucted by macro NV_GPU_GET_HDCP_SUPPORT_STATUS.
Definition nvapi.h:3194
NvU32 isMonYCbCr422Capable
If YCbCr 4:2:2 is supported.
Definition nvapi.h:6691
NvU32 HBsubSysDeviceId
Host bridge subsystem device identification.
Definition nvapi.h:22699
NvU32 dm_version
Upper Nibble represents major version of Display Management(DM) while lower represents minor version ...
Definition nvapi.h:7554
NvAPI_String adapterName
Graphics adapter name.
Definition nvapi.h:20002
NvSBox * textureRect
rectangle in desktop coordinates describing the source area for the warping
Definition nvapi.h:3740
NvU32 version
Structure version.
Definition nvapi.h:5054
NvU32 pixelShift
Enable Pixel shift.
Definition nvapi.h:9656
NvU8 supportDualDviOperation
Byte 3.
Definition nvapi.h:8064
int numVertices
number of the input vertices
Definition nvapi.h:3739
NVVIOSIGNALFORMAT signalFormat
Signal format for video output.
Definition nvapi.h:20359
NvU32 version
Structure Version.
Definition nvapi.h:22888
NvU32 bIsNVIDIARTXProductionBranchPackage
Definition nvapi.h:22898
NvPhysicalGpuHandle hPhysicalGpu
Compute-capable physical GPU handle.
Definition nvapi.h:3248
NvU32 driverExpandDefaultHdrParameters
Definition nvapi.h:7426
NV_GPU_CLIENT_ILLUM_DEVICE_SYNC_V1 syncData
Definition nvapi.h:5556
struct _NVVIOOUTPUTCONFIG_V1 NVVIOOUTPUTCONFIG_V1
Output device configuration.
NvU32 reserved
Should be set to zero.
Definition nvapi.h:7564
NvU16 max_frame_average_light_level
Maximum Frame-Average Light Level (MaxFALL) ([0x0000-0xFFFF] = [0.0 - 65535.0] cd/m^2,...
Definition nvapi.h:7805
NvU32 version
Version of this structure.
Definition nvapi.h:5145
NvU16 displayWhitePoint_x
x coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7689
NvU8 VSyncPol
vertical sync polarity: 1-negative, 0-positive
Definition nvapi.h:659
NvU32 flags
Reserved. Must be set to 0.
Definition nvapi.h:4649
NvU32 bFocusDisplay
(IN) If set, this display path should have the focus after the GPU topology change
Definition nvapi.h:814
NvU32 reserved_sourceId
Definition nvapi.h:1000
NvU32 acceleratePrimaryDisplay
Enable SLI acceleration on the primary display while in single-wide mode (For Immersive Gaming only)....
Definition nvapi.h:9639
NVVIOVIDEOTYPE videoType
HD or SD signal classification.
Definition nvapi.h:20127
NvU32 bDisable
(IN) Disable Reflex Sync
Definition nvapi.h:17620
NvU32 version
Structure version.
Definition nvapi.h:310
NvU32 supports_global_dimming
Indicates if sink supports global dimming.
Definition nvapi.h:7493
NvU32 cbSize
The size of the data buffer, pbData, to be read or written.
Definition nvapi.h:2954
NvU16 VTotal
vertical total
Definition nvapi.h:658
NvU32 colorimetry
If set indicates sink supports DCI P3 colorimetry, REc709 otherwise.
Definition nvapi.h:7494
NvU16 min_display_mastering_luminance
Minimum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 6.55350] cd/m^2)
Definition nvapi.h:7693
NvU32 sourceId
(IN/OUT) Source ID - values will be based on the number of heads exposed per GPU.
Definition nvapi.h:725
NvAPI_LicenseString licenseInfo
Deprecated.
Definition nvapi.h:4128
NvU32 vendorId
Chipset vendor identification.
Definition nvapi.h:22688
NV_TIMING timing
Timing used to program TMDS/DAC/LVDS/HDMI/TVEncoder, etc.
Definition nvapi.h:8212
NvU32 scaling
Define preferred scaling.
Definition nvapi.h:7966
NvU8 bIsDDCPort
Definition nvapi.h:2964
NvU32 licensableFeatureCount
The number of licensable features.
Definition nvapi.h:4188
NvU16 application_version
Application version of HDR10+ Vendor Specific Video Data Block.
Definition nvapi.h:7581
NvU32 count
(IN) Path count
Definition nvapi.h:824
NvU32 interlaceMode
interlace mode for a Sync device
Definition nvapi.h:10341
NvAPI_UnicodeString settingName
String name of setting.
Definition nvapi.h:21888
void * pCallbackParam
Definition nvapi.h:23008
NvU32 displayMask
The Display Mask of the concerned display.
Definition nvapi.h:2942
NvU32 version
Version of the structure.
Definition nvapi.h:10324
NvU32 isTraditionalHdrGammaSupported
HDMI2.0a traditional HDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7458
float fFrameRate
Frame rate.
Definition nvapi.h:20124
NvU32 isRgb444SupportedOnCurrentMode
If Rgb444 is supported on the current mode.
Definition nvapi.h:6550
NV_GPU_PUBLIC_CLOCK_ID domainId
ID of the clock domain.
Definition nvapi.h:4648
NvU32 percentage
Percentage of time where the domain is considered busy in the last 1 second interval.
Definition nvapi.h:4861
NvU32 height
Height of region in pixels.
Definition nvapi.h:20087
NvU8 colorFormat
One of NV_COLOR_FORMAT enum values.
Definition nvapi.h:7391
NV_DP_DYNAMIC_RANGE dynamicRange
Dynamic range.
Definition nvapi.h:6536
struct _NV_GPU_CLIENT_CALLBACK_UTILIZATION_DATA_V1 NV_GPU_CLIENT_CALLBACK_UTILIZATION_DATA_V1
NvU32 deviceId
Chipset device identification.
Definition nvapi.h:22689
NvU32 targetDisplayWidth
Horizontal size of the active resolution scanned out to the display.
Definition nvapi.h:3917
struct _NV_GPU_PERF_PSTATES20_INFO_V2::@9 ov
NvU32 isTraditionalSdrGammaSupported
HDMI2.0a traditional SDR gamma (CEA861.3). Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7462
NV_GPU_PSTATE20_BASE_VOLTAGE_ENTRY_V1 voltages[NVAPI_MAX_GPU_PSTATE20_BASE_VOLTAGES]
Definition nvapi.h:1309
NvU16 size
Size of this structure.
Definition nvapi.h:7372
struct _NVVIOOUTPUTREGION NVVIOOUTPUTREGION
Output region.
NvU32 linkState
This field specifies the current state of the link.See NVAPI_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* fo...
Definition nvapi.h:4423
NvU16 cc_blue_x
Blue primary chromaticity coordinate x.
Definition nvapi.h:7573
NvU16 max_display_mastering_luminance
Maximum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
Definition nvapi.h:7692
NvU32 dpcd_ver
DPCD version of the monitor.
Definition nvapi.h:6530
NvU32 valueLength
valueLength should always be in number of bytes.
Definition nvapi.h:21858
NvU32 testLinkTrain
If testing mode, skip validation.
Definition nvapi.h:6642
NvU32 version
[in] structure version
Definition nvapi.h:8631
NVAPI_CALLBACK_QSYNCEVENT nvQSYNCEventCallback
Callback function pointer for QSYNC events.
Definition nvapi.h:3590
NVDRS_SETTING_LOCATION settingLocation
Describes where the value in CurrentValue comes from.
Definition nvapi.h:21891
NvU32 gpuId
(IN) the physical display/target Gpu id which is the owner of the scan out (for SLI multimon,...
Definition nvapi.h:815
NvU32 isLicenseSupported
True if Software Licensing is supported.
Definition nvapi.h:4186
#define NVAPI_MAX_VIO_CHANNELS_PER_JACK
Definition nvapi.h:19872
NvU32 supports_YUV422_12bit
If set, sink is capable of YUV422-12 bit.
Definition nvapi.h:7556
NvU32 warningFlags
(OUT) Any of the NV_MOSAIC_DISPLAYTOPO_WARNING_* flags.
Definition nvapi.h:9766
NvAPI_UnicodeString fileInFolder
Definition nvapi.h:21946
NvU32 flags
One or more flags from nvcomp_gpu_top.
Definition nvapi.h:3249
NV_LICENSE_FEATURE_DETAILS_V2 licenseDetails[NV_LICENSE_MAX_COUNT]
Array of licensable features.
Definition nvapi.h:4180
NvU8 * pbData
The buffer of data which is to be read or written (depending on the command).
Definition nvapi.h:2953
NV_MOSAIC_DISPLAY_SETTING_V1 displaySettings
Display settings.
Definition nvapi.h:9659
NvU32 version
Version of the structure.
Definition nvapi.h:10132
NvU32 isLicenseSupported
True if Software Licensing is supported.
Definition nvapi.h:4175
NvU8 rsvd[64]
Definition nvapi.h:23013
NvU8 phyType
This field specifies the type of PHY (NVHS or GRS) being used for this link.
Definition nvapi.h:4421
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7687
NvU32 isEnabled
The current state of license, true=licensed, false=unlicensed.
Definition nvapi.h:4146
NvU32 rowCount
Number of displays in a row.
Definition nvapi.h:9092
NvU8 loopProperty
This field specifies if the link is a loopback/loopout link. See NVAPI_NVLINK_STATUS_LOOP_PROPERTY_* ...
Definition nvapi.h:4457
NvU32 version
Structure version.
Definition nvapi.h:20192
NvU8 remoteDeviceLinkNumber
This field specifies the link number on the remote end of the link.
Definition nvapi.h:4458
NvU32 bDisableAdaptiveSync
[out] Indicates if adaptive sync is disabled on the display.
Definition nvapi.h:8594
NvU16 HTotal
horizontal total
Definition nvapi.h:651
NvPhysicalGpuHandle hPhysicalGpu
Definition nvapi.h:5279
NvU16 displayWhitePoint_y
y coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7690
NvU32 version
Structure version.
Definition nvapi.h:318
NvU32 isPossible
1 if topo can be enabled, else 0
Definition nvapi.h:9205
NvU64 deviceType
GPU Type. See NVAPI_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values.
Definition nvapi.h:4340
NvU32 isEnabled
The current state of the licensed feature, true=enabled, false=disabled.
Definition nvapi.h:4125
NvU32 isYCbCr420SupportedOnCurrentMode
If YCbCr420 is supported on the current mode.
Definition nvapi.h:6553
NvU32 version
(IN) Structure version
Definition nvapi.h:17618
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR_PARAMS singleColorParams[NV_GPU_CLIENT_ILLUM_CTRL_MODE_PIECEWISE_LINEAR_COLOR_ENDPOINTS]
Definition nvapi.h:6093
NvU16 desired_content_max_frame_average_luminance
Desired maximum Frame-Average Light Level (MaxFALL) of HDR content ([0x0001-0xFFFF] = [1....
Definition nvapi.h:7484
NvPhysicalGpuHandle hPhysicalGpu
GPU handle.
Definition nvapi.h:10203
NvU32 ctrlModeMask
Definition nvapi.h:5443
NvBool supported
(OUT) boolean returning if feature is supported
Definition nvapi.h:19451
NvU16 cc_green_x
Green primary chromaticity coordinate x.
Definition nvapi.h:7505
NvU32 totalCount
Count of valid topologies.
Definition nvapi.h:9958
NV_DISPLAYCONFIG_PATH_ADVANCED_TARGET_INFO * details
May be NULL if no advanced settings are required.
Definition nvapi.h:962
NvU32 version
Version of this structure.
Definition nvapi.h:7455
NvU32 frameLockEnable
Framelock enable flag.
Definition nvapi.h:20057
NvU8 reservedData[256]
Indicates last stored SDI output state TRUE-ON / FALSE-OFF.
Definition nvapi.h:20437
NvU32 version
Version of this structure.
Definition nvapi.h:9265
NvU32 dipSwitch
On-board DIP switch settings bits.
Definition nvapi.h:20005
NvU32 VSVDB_version
Version of Vendor Data block,Version 0: 25 bytes Version 1: 14 bytes.
Definition nvapi.h:7489
union _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_RGB::@32 data
NvU8 colorimetry
One of NV_COLOR_COLORIMETRY enum values.
Definition nvapi.h:7363
NV_THERMAL_TARGET target
Thermal sensor targeted @ GPU, memory, chipset, powersupply, Visual Computing Device,...
Definition nvapi.h:4951
NvU16 cc_white_y
White primary chromaticity coordinate y.
Definition nvapi.h:7510
NvU32 version
Structure version.
Definition nvapi.h:20487
NvU32 version
version of this structure
Definition nvapi.h:3694
NV_MOSAIC_TOPO_BRIEF brief
The brief details of this topo.
Definition nvapi.h:9320
struct _NV_GPU_CLIENT_CALLBACK_DATA_SUPER_V1 NV_GPU_CLIENT_CALLBACK_DATA_SUPER_V1
NvU16 displayPrimary_y2
y coordinate of color primary 2 (e.g. Blue) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7541
NvU8 nvlinkRefClkType
This field specifies whether refclk is taken from NVHS reflck or PEX refclk for the current GPU....
Definition nvapi.h:4431
struct _NVVIOCAPS::@59 driver
Driver version.
struct _NVVIOCAPS::@60 firmWare
Firmware version.
NvU32 reserved
These bits are reserved for future use.
Definition nvapi.h:5061
NvPhysicalGpuHandle hProxyPhysicalGpu
Definition nvapi.h:10205
NvU32 subSysDeviceId
Chipset subsystem device identification.
Definition nvapi.h:22694
NvS32 overlapX
(+overlap, -gap)
Definition nvapi.h:9616
NVLINK_DEVICE_INFO_V1 remoteDeviceInfo
This field stores the device information for the remote end of the link.
Definition nvapi.h:4459
NvU32 isMetro
Windows 8 style app.
Definition nvapi.h:21962
NVVIOCOMPONENTSAMPLING sampling
Sampling
Definition nvapi.h:20448
NvU32 i2cSpeed
Deprecated, Must be set to NVAPI_I2C_SPEED_DEPRECATED.
Definition nvapi.h:2976
NV_GPU_PERF_VOLTAGE_INFO_DOMAIN_ID domainId
Voltage domain ID and value range in (uV) required for this clock.
Definition nvapi.h:1192
NvU8 has3dEntries
Byte 10.
Definition nvapi.h:8092
NvU32 deviceIdFlags
Definition nvapi.h:4332
NV_FORMAT colorFormat
Color format if it needs to be specified. Not used now.
Definition nvapi.h:794
NVVIOCOLORCONVERSION colorConversion
Color conversion.
Definition nvapi.h:20391
NVLINK_DEVICE_INFO_V1 remoteDeviceInfo
This field stores the GPU information for the remote end of the link.
Definition nvapi.h:4437
NvU32 flags
Chipset info flags.
Definition nvapi.h:22728
NvU32 enableComposite
Enable composite.
Definition nvapi.h:20405
NvU32 currentLidState
Structure version, constructed from the macro NV_LID_DOCK_PARAMS_VER.
Definition nvapi.h:22774
NV_GPU_ARCH_IMPLEMENTATION_ID implementation_id
specifies the implementation of the architecture for the GPU.
Definition nvapi.h:2851
NvU32 enableANCTimeCodeGeneration
Enable SDI ANC time code generation.
Definition nvapi.h:20376
NvU32 displayId
DisplayID of the display.
Definition nvapi.h:9615
NvU16 displayWhitePoint_x
x coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
Definition nvapi.h:7660
NvU32 backlt_min_luma
It is the level for Backlt min luminance value.
Definition nvapi.h:7496
NV_GSYNC_DELAY startupDelay
Sync start delay for master.
Definition nvapi.h:10369
NvU8 videoLatency
Byte 6.
Definition nvapi.h:8083
NvU32 dataIntegrityCheckErrorCount
Data integrity check error count.
Definition nvapi.h:20059
_NVVIOSIGNALFORMAT
Video signal format and resolution.
Definition nvapi.h:19671
NV_D3D12_WORKSTATION_FEATURE_TYPE workstationFeatureType
(IN) the type of workstation feature to be queried
Definition nvapi.h:19450
NV_STATIC_METADATA_DESCRIPTOR_ID static_metadata_descriptor_id
Static Metadata Descriptor Id (0 for static metadata type 1)
Definition nvapi.h:7431
NvU32 version
Structure version.
Definition nvapi.h:5026
NvU32 outputVideoLocked
Output locked status.
Definition nvapi.h:20058
NvU8 * pEDID
Pointer to EDID data.
Definition nvapi.h:8542
NvU32 height
Visible vertical size.
Definition nvapi.h:7976
NvU32 applyWithBezelCorrect
When enabling and doing the modeset, do we switch to the bezel-corrected resolution.
Definition nvapi.h:9651
NVVIOOUTPUTCONFIG_V3 outConfig
Output device configuration.
Definition nvapi.h:20505
NV_VIEWPORTF srcPartition
For multimon support, should be set to (0,0,1.0,1.0) for now.
Definition nvapi.h:8207
NvBool bLowLatencyMode
(IN) Low latency mode enable/disable.
Definition nvapi.h:17532
NvU8 loopProperty
This field specifies if the link is a loopback/loopout link. See NVAPI_NVLINK_STATUS_LOOP_PROPERTY_* ...
Definition nvapi.h:4435
NvU8 hasInterlacedLatencyField
Byte 5.
Definition nvapi.h:8080
struct _NVVIOVIDEOMODE NVVIOVIDEOMODE
Video mode information.
NvU32 interface_supported_by_sink
Indicates the interface (standard or low latency) supported by the sink.
Definition nvapi.h:7561
NV_INFOFRAME_PROPERTY property
This is NVIDIA-specific and corresponds to the property cmds and associated infoframe.
Definition nvapi.h:7200
NvU32 compositeTerminate
Composite termination.
Definition nvapi.h:20429
NvU32 reserved
Should be set to ZERO.
Definition nvapi.h:10216
void * pCallbackParam
Definition nvapi.h:22965
NvU16 uGreen[256]
Green channel gamma ramp (8-bit index, 16-bit values)
Definition nvapi.h:20094
NvU16 displayPrimary_y0
y coordinate of color primary 0 (e.g. Red) of the display ([0x0000-0xC350] = [0.0 - 1....
Definition nvapi.h:7471
NvU32 version
version of this structure
Definition nvapi.h:3736
NvU32 version
IN - Structure version.
Definition nvapi.h:4196
NV_COLOR_SELECTION_POLICY colorSelectionPolicy
One of the color selection policy.
Definition nvapi.h:7395
NvLogicalGpuHandle hLogicalGPU
Logical GPU for this topology.
Definition nvapi.h:9089
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1268
NvU32 version
Definition nvapi.h:5574
NvU32 enable422Filter
Enables/Disables 4:2:2 filter.
Definition nvapi.h:20399
NvU32 vendorId
vendor ID
Definition nvapi.h:22724
NvU32 is12BPCSupported
If 12 bpc is supported.
Definition nvapi.h:6545
NvU16 cc_white_x
White primary chromaticity coordinate x.
Definition nvapi.h:7509
NvU32 numPstates
The number of available p-states.
Definition nvapi.h:4637
NvU32 enableRGBData
Indicates data is in RGB format.
Definition nvapi.h:20410
NvU8 HSyncPol
horizontal sync polarity: 1-negative, 0-positive
Definition nvapi.h:652
NvU32 aspect
Display aspect ratio Hi(aspect):horizontal-aspect, Low(aspect):vertical-aspect.
Definition nvapi.h:609
NvU16 rr
Logical refresh rate to present.
Definition nvapi.h:607
NvU32 bHouseSync
Is house sync connected?
Definition nvapi.h:10538
NvU32 version
Structure version.
Definition nvapi.h:20001
NV_GPU_ILLUMINATION_ATTRIB Attribute
Definition nvapi.h:5153
NVVIOBITSPERCOMPONENT bitsPerComponent
Bits per component.
Definition nvapi.h:20034
NV_MOSAIC_DISPLAY_SETTING_V1 displaySettings
Display settings.
Definition nvapi.h:9642
NvU32 licensableFeatureCount
The number of licensable features.
Definition nvapi.h:4166
NvU32 bDefault
Definition nvapi.h:6153
NvU8 i2cDevAddress
Definition nvapi.h:2945
NvU8 rxSublinkStatus
This field specifies the current state of RX sublink.See NVAPI_NVLINK_GET_NVLINK_STATUS_SUBLINK_RX_ST...
Definition nvapi.h:4446
NvU8 lowestNciVersion
This field specifies the lowest supported NCI version for this GPU.
Definition nvapi.h:4275
_NVVIOVIDEOSTANDARD
SMPTE standards format.
Definition nvapi.h:19747
NvU8 supportDeepColorYCbCr444
Byte 3.
Definition nvapi.h:8066
NvU16 size
size of this structure
Definition nvapi.h:7194
NvU32 pciSlot
specifies the PCI slot number of the GVI device.
Definition nvapi.h:20853
float rr
Timing refresh rate.
Definition nvapi.h:7977
NvU32 reserved
Reserved, must be 0.
Definition nvapi.h:9640
NvU32 isEdrSupported
Extended Dynamic Range on SDR displays. Boolean: 0 = not supported, 1 = supported;.
Definition nvapi.h:7425
NV_SCALING scaling
(IN) scaling setting.
Definition nvapi.h:908
NvU32 extendedRevision
FPGA minor revision.
Definition nvapi.h:10136
NvU32 flipQueueLength
Number of buffers used for the internal flip queue.
Definition nvapi.h:20403
NvU32 enableComposite
Enable composite.
Definition nvapi.h:20434
float colorScale[3]
Definition nvapi.h:20177
NvU32 bIsNVIDIAGameReadyPackage
Definition nvapi.h:22916
NvU32 numUtils
Definition nvapi.h:23069
NvU32 isMonBasicAudioCapable
If the monitor supports basic audio.
Definition nvapi.h:6689
_NVVIOINTERLACEMODE
Interlace mode.
Definition nvapi.h:19765
NV_THERMAL_CONTROLLER controller
internal, ADM1032, MAX6649...
Definition nvapi.h:4963
NvU32 reserved
These bits are reserved for future use (must be always 0)
Definition nvapi.h:1207
NV_GPU_CHIP_REVISION revision_id
specifies the architecture revision of the GPU.
Definition nvapi.h:2856
NVVIOSYNCSTATUS sdiSyncIn
SDI sync input status.
Definition nvapi.h:20052
NvU32 revision
FPGA major revision.
Definition nvapi.h:10125
NvU32 version
Structure Version.
Definition nvapi.h:21887
NvU32 version
Structure version.
Definition nvapi.h:20110
_NVVIOSYNCSOURCE
Synchronization source.
Definition nvapi.h:19812
NvU32 cscOverride
Use provided CSC color matrix to overwrite.
Definition nvapi.h:20374
NvU32 version
Version of the structure.
Definition nvapi.h:10213
float fGammaValueG
Green Gamma value within gamma ranges. 0.5 - 6.0.
Definition nvapi.h:20201
NvU32 version
Structure version.
Definition nvapi.h:3233
NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_MANUAL_SINGLE_COLOR_PARAMS singleColorParams
Definition nvapi.h:6079
NvU32 bIsNVIDIAStudioPackage
Definition nvapi.h:22894
NVVIOSYNCSOURCE syncSource
Sync source.
Definition nvapi.h:20366
NvU32 height
(IN) Height of the mode
Definition nvapi.h:792
NvU32 height
height of the input texture
Definition nvapi.h:3653
NVAPI_GSYNC_GPU_TOPOLOGY_CONNECTOR connector
Indicates which connector on the device the GPU is connected to.
Definition nvapi.h:10204
NvAPI_ShortString szChipsetName
device Name
Definition nvapi.h:22709
NvU32 version
Structure version.
Definition nvapi.h:3370
NvU8 nciVersion
This field specifies the NCI version supported by the link.
Definition nvapi.h:4427
NvAPI_UnicodeString profileName
String name of the Profile.
Definition nvapi.h:21980
NvU32 displayCount
Number of display details.
Definition nvapi.h:9634
NvU32 isEnabled
The current state of the licensed feature, true=enabled, false=disabled.
Definition nvapi.h:4116
NvSBox sourceViewportRect
Area inside the sourceDesktopRect which is scanned out to the display.
Definition nvapi.h:3915
NvU32 width
Source surface(source mode) width.
Definition nvapi.h:8202
union _NV_GPU_CLIENT_ILLUM_DEVICE_INFO_V1::@30 data
NvU32 bHouseSync
Is house sync connected?
Definition nvapi.h:10528
NvU32 isPredefined
Is the application userdefined/predefined.
Definition nvapi.h:21942
NvU32 version
Version of the structure.
Definition nvapi.h:10202
struct _NV_GPU_PERF_PSTATES20_INFO_V2::@8 pstates[NVAPI_MAX_GPU_PSTATE20_PSTATES]
NvS32 overlapY
Pixels of overlap on top of target: (+overlap, -gap)
Definition nvapi.h:9100
NvU32 utilizationPercent
Definition nvapi.h:23047
NVVIOSYNCDELAY syncDelay
Sync delay.
Definition nvapi.h:20395
NVVIOPCILINKRATE pciLinkRate
specifies the the negotiated PCIE link rate.
Definition nvapi.h:20855
NVVIOCOMPOSITERANGE compRange
Composite ranges.
Definition nvapi.h:20436
NvU16 size
Size of this structure.
Definition nvapi.h:7387
NvU32 gpuCount
Size of array.
Definition nvapi.h:3256
NV_DP_LANE_COUNT maxLaneCount
Maximum supported lane count.
Definition nvapi.h:6532
struct _NV_CLIENT_CALLBACK_SETTINGS_SUPER_V1 NV_CLIENT_CALLBACK_SETTINGS_SUPER_V1
NV_THERMAL_CONTROLLER controller
internal, ADM1032, MAX6649...
Definition nvapi.h:4947
NvU32 version
Structure Version.
Definition nvapi.h:4564
NV_MOSAIC_TOPO_BRIEF topoBriefs[NV_MOSAIC_TOPO_MAX]
List of supported topologies with only brief details.
Definition nvapi.h:9267
NvU32 isMasterable
Can this display be the master? (Read only)
Definition nvapi.h:10215
NvU32 reserved
Reserved for future use.
Definition nvapi.h:4518
NvU32 tensorCores
Number of "Tensor Cores" supported by the GPU.
Definition nvapi.h:4528
NvU32 columns
Number of columns.
Definition nvapi.h:9633
NvU8 rsvd[64]
Definition nvapi.h:6164
NvU32 isYCbCr422SupportedOnCurrentMode
If YCbCr422 is supported on the current mode.
Definition nvapi.h:6552
NvU32 version
Version of this structure.
Definition nvapi.h:7332
NvU32 flags
Definition nvapi.h:4672
NvU32 reserved
Should be set to zero.
Definition nvapi.h:7528
NvU32 version
Version of the structure.
Definition nvapi.h:10123
float xRatio
Horizontal scaling ratio.
Definition nvapi.h:8209
struct _NVVIOINPUTCONFIG NVVIOINPUTCONFIG
Input device configuration.
NvU32 linkState
This field specifies the current state of the link.See NVAPI_NVLINK_GET_NVLINK_STATUS_LINK_STATE_* fo...
Definition nvapi.h:4445
NV_GPU_HDCP_KEY_SOURCE hdcpKeySource
GPU's HDCP fuse state.
Definition nvapi.h:3195
NvU32 defaultMaxTemp
The max default temperature value of the thermal sensor in degree Celsius.
Definition nvapi.h:4949
NvU32 reserved
These bits are reserved for future use. Must be set to 0.
Definition nvapi.h:5056
NvU32 displayId
[in] Monitor Identifier to be set
Definition nvapi.h:8740
NV_COLOR_FORMAT hdrColorFormat
Optional, One of NV_COLOR_FORMAT enum values, if set it will apply requested color format for HDR ses...
Definition nvapi.h:7699
NvU32 version
Version of this structure.
Definition nvapi.h:7371
NV_GPU_PERF_PSTATES20_PARAM_DELTA freqDelta_kHz
Current frequency delta from nominal settings in (kHz)
Definition nvapi.h:1172
NvU16 min_display_mastering_luminance
Minimum display mastering luminance ([0x0000-0xFFFF] = [0.0 - 6.55350] cd/m^2, in units of 0....
Definition nvapi.h:7802
NvU32 syncEnable
Sync enable (TRUE if using syncSource)
Definition nvapi.h:20054
union _NV_GPU_CLIENT_ILLUM_ZONE_CONTROL_DATA_COLOR_FIXED::@33 data
NvU8 signature[NV_LICENSE_SIGNATURE_SIZE]
Definition nvapi.h:4189
NvU32 HBsubSysVendorId
Host bridge subsystem vendor identification.
Definition nvapi.h:22698
NvU16 displayPrimary_x2
x coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7795
NV_BPC bpc
One of NV_BPC enum values.
Definition nvapi.h:7379
NvU32 version
structure version
Definition nvapi.h:2624
NvU32 numIllumZonesControl
Definition nvapi.h:6159
NVAPI_GSYNC_SYNC_SOURCE source
VSync/House sync.
Definition nvapi.h:10363
NvU32 sourceId
Identifies sourceId used by Windows CCD. This can be optionally set.
Definition nvapi.h:1017
NvU32 connected
This field specifies if any device is connected on the other end of the link.
Definition nvapi.h:4433
NvU8 isRLACapable
whether monitor supports RLA
Definition nvapi.h:8106
NvU64 timestamp
Definition nvapi.h:23075
NvU32 isMonxvYCC709Capable
If xvYCC extended colorimetry 709 is supported.
Definition nvapi.h:6693
NvU8 bIsDDCPort
Definition nvapi.h:2923
NV_GPU_CLIENT_CALLBACK_SETTINGS_SUPER_V1 super
Definition nvapi.h:22984
NvU8 supportDeepColor36bits
Byte 3.
Definition nvapi.h:8068
NvU16 displayPrimary_y1
y coordinate of color primary 1 (e.g. Green) of the display ([0x0000-0xC350] = [0....
Definition nvapi.h:7439
NVVIOTOPOLOGYTARGET vioTarget[NVAPI_MAX_VIO_DEVICES]
Array of video I/O targets.
Definition nvapi.h:20530
NvU32 reserved
These bits are reserved for future use.
Definition nvapi.h:5027
NvU16 displayPrimary_x0
x coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0....
Definition nvapi.h:7680
NvSBox targetViewportRect
Area inside the rect described by targetDisplayWidth/Height sourceViewportRect is scanned out to.
Definition nvapi.h:3916
NvU32 bIsStereoSynced
Does the phase of the timing signal from the GPU = the phase of the master sync signal?
Definition nvapi.h:10473
NvU32 dipSwitchReserved
On-board DIP switch settings reserved bits.
Definition nvapi.h:20006
NvU16 domain
domain, bus, device, function, pciDeviceId : PCI information for the GPU.
Definition nvapi.h:4335
NvBool bLowLatencyMode
(OUT) Is low latency mode enabled?
Definition nvapi.h:17486
@ NVVIOCOMPSYNCTYPE_BILEVEL
Bi-level signal.
Definition nvapi.h:19821
@ NVVIOCOMPSYNCTYPE_AUTO
Auto-detect.
Definition nvapi.h:19820
@ NVVIOCOMPSYNCTYPE_TRILEVEL
Tri-level signal.
Definition nvapi.h:19822
@ NVVIOOUTPUTAREA_FULLSIZE
Output to entire video resolution (full size)
Definition nvapi.h:19805
@ NVVIOOUTPUTAREA_SAFEACTION
Output to centered 90% of video resolution (safe action)
Definition nvapi.h:19806
@ NVVIOOUTPUTAREA_SAFETITLE
Output to centered 80% of video resolution (safe title)
Definition nvapi.h:19807
@ NVVIODATAFORMAT_X10X8X8Z10_4444_PASSTHRU
Y10:CR8:CB8:Z10 => YCrCbZ (4:4:4:4)
Definition nvapi.h:19787
@ NVVIODATAFORMAT_X10X8X8A10_4444_PASSTHRU
Y10:CR8:CB8:A10 => YCrCbA (4:4:4:4)
Definition nvapi.h:19786
@ NVVIODATAFORMAT_Y10CR10CB10_TO_YCRCB422
Y10:CR10:CB10 => YCrCb (4:2:2)
Definition nvapi.h:19794
@ NVVIODATAFORMAT_UNKNOWN
Invalid DataFormat.
Definition nvapi.h:19774
@ NVVIODATAFORMAT_X10X8X8_444_PASSTHRU
Y10:CR8:CB8 => YCrCb (4:4:4)
Definition nvapi.h:19785
@ NVVIODATAFORMAT_X12X12X12_422_PASSTHRU
X12:X12:X12 => XXX (4:2:2)
Definition nvapi.h:19793
@ NVVIODATAFORMAT_DUAL_X8X8X8_TO_DUAL_422_PASSTHRU
Y8:CR8:CB8 + Y8:CR8:CB8 => YCrCb (4:2:2 + 4:2:2)
Definition nvapi.h:19789
@ NVVIODATAFORMAT_Y10CR8CB8A10_TO_YCRCBA4224
Y10:CR8:CB8:A10 => YCrCbA (4:2:2:4)
Definition nvapi.h:19796
@ NVVIODATAFORMAT_R8G8B8_TO_YCRCB422
R8:G8:B8 => YCrCb (4:2:2)
Definition nvapi.h:19778
@ NVVIODATAFORMAT_R8G8B8A8_TO_YCRCBA4224
R8:G8:B8:A8 => YCrCbA (4:2:2:4)
Definition nvapi.h:19779
@ NVVIODATAFORMAT_Y8CR8CB8_TO_YCRCB422
Y8:CR8:CB8 => YCrCb (4:2:2)
Definition nvapi.h:19795
@ NVVIODATAFORMAT_R8G8B8Z10_TO_YCRCBZ4444
R8:G8:B8:Z10 => YCrCbZ (4:4:4:4)
Definition nvapi.h:19777
@ NVVIODATAFORMAT_X12X12X12_444_PASSTHRU
X12:X12:X12 => XXX (4:4:4)
Definition nvapi.h:19792
@ NVVIODATAFORMAT_R8G8B8A8_TO_YCRCBA4444
R8:G8:B8:A8 => YCrCbA (4:4:4:4)
Definition nvapi.h:19776
@ NVVIODATAFORMAT_X8X8X8A8_4444_PASSTHRU
R8:G8:B8:A8 => RGBA (4:4:4:4)
Definition nvapi.h:19782
@ NVVIODATAFORMAT_R8G8B8_TO_YCRCB444
R8:G8:B8 => YCrCb (4:4:4)
Definition nvapi.h:19775
@ NVVIODATAFORMAT_R10G10B10_TO_YCRCB444
R10:G10:B10 => YCrCb (4:4:4)
Definition nvapi.h:19791
@ NVVIODATAFORMAT_R10G10B10_TO_YCRCB422
R10:G10:B10 => YCrCb (4:2:2)
Definition nvapi.h:19790
@ NVVIODATAFORMAT_X10X10X10_444_PASSTHRU
Y10:CR10:CB10 => YCrCb (4:4:4)
Definition nvapi.h:19784
@ NVVIODATAFORMAT_R10G10B10_TO_RGB444
R10:G10:B10 => RGB (4:4:4)
Definition nvapi.h:19797
@ NVVIODATAFORMAT_X8X8X8_444_PASSTHRU
R8:G8:B8 => RGB (4:4:4)
Definition nvapi.h:19781
@ NVVIODATAFORMAT_R8G8B8Z10_TO_YCRCBZ4224
R8:G8:B8:Z10 => YCrCbZ (4:2:2:4)
Definition nvapi.h:19780
@ NVVIODATAFORMAT_R12G12B12_TO_YCRCB422
R12:G12:B12 => YCrCb (4:2:2)
Definition nvapi.h:19799
@ NVVIODATAFORMAT_DUAL_R8G8B8_TO_DUAL_YCRCB422
R8:G8:B8 + R8:G8:B8 => YCrCb (4:2:2 + 4:2:2)
Definition nvapi.h:19788
@ NVVIODATAFORMAT_X8X8X8Z10_4444_PASSTHRU
R8:G8:B8:Z10 => RGBZ (4:4:4:4)
Definition nvapi.h:19783
@ NVVIODATAFORMAT_R12G12B12_TO_YCRCB444
R12:G12:B12 => YCrCb (4:4:4)
Definition nvapi.h:19798
@ NVVIOOWNERTYPE_NONE
No owner for the device.
Definition nvapi.h:19629
@ NVVIOOWNERTYPE_DESKTOP
Desktop transparent mode owns the device (not applicable for video input)
Definition nvapi.h:19631
@ NVVIOOWNERTYPE_APPLICATION
Application owns the device.
Definition nvapi.h:19630
@ NV_GPU_CLIENT_UTIL_DOMAIN_RSVD
Definition nvapi.h:23028
@ NVVIOSTATUSTYPE_OUT
Output Status.
Definition nvapi.h:19857
@ NVVIOSTATUSTYPE_IN
Input Status.
Definition nvapi.h:19856
@ NVVIOSTATUS_ERROR
Genlock in use, format mismatch with output.
Definition nvapi.h:19850
@ NVVIOSTATUS_RUNNING
Error detected.
Definition nvapi.h:19849
@ NVVIOSTATUS_STOPPED
Sync not detected.
Definition nvapi.h:19848
@ NVVIOCONFIGTYPE_OUT
Output Status.
Definition nvapi.h:19903
@ NVVIOCONFIGTYPE_IN
Input Status.
Definition nvapi.h:19902
@ NVINPUTOUTPUTSTATUS_SDI_SD
SDI (standard-definition)
Definition nvapi.h:19830
@ NVINPUTOUTPUTSTATUS_OFF
Not in use.
Definition nvapi.h:19828
@ NVINPUTOUTPUTSTATUS_ERROR
Error detected.
Definition nvapi.h:19829
@ NVINPUTOUTPUTSTATUS_SDI_HD
SDI (high-definition)
Definition nvapi.h:19831
@ NVVIOVIDEOTYPE_SD
Standard-definition (SD)
Definition nvapi.h:19759
@ NVVIOVIDEOTYPE_HD
High-definition (HD)
Definition nvapi.h:19760
@ NVVIOSYNCSTATUS_ERROR
Error detected.
Definition nvapi.h:19838
@ NVVIOSYNCSTATUS_OFF
Sync not detected.
Definition nvapi.h:19837
@ NVVIOSYNCSTATUS_SDI_SD
SDI sync (standard-definition)
Definition nvapi.h:19841
@ NVVIOSYNCSTATUS_SDI_HD
SDI sync (high-definition)
Definition nvapi.h:19842
@ NVVIOSYNCSTATUS_COMPOSITE
Composite sync.
Definition nvapi.h:19840
@ NVVIOSYNCSTATUS_SYNCLOSS
Genlock in use, format mismatch with output.
Definition nvapi.h:19839
@ NVVIOSIGNALFORMAT_2048I_48_00_SMPTE372_3G_LEVEL_B
55 2048i 48.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19730
@ NVVIOSIGNALFORMAT_1080I_59_94_SMPTE274_3G_LEVEL_B
57 1080i 59.94Hz (SMPTE274) 3G Level B
Definition nvapi.h:19732
@ NVVIOSIGNALFORMAT_1080I_50_00_SMPTE274_3G_LEVEL_B
46 1080i 50.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19721
@ NVVIOSIGNALFORMAT_1080I_60_00_SMPTE274
06 1080i 60.00Hz (SMPTE274)
Definition nvapi.h:19678
@ NVVIOSIGNALFORMAT_720P_60_00_SMPTE296
14 720p 60.00Hz (SMPTE296)
Definition nvapi.h:19686
@ NVVIOSIGNALFORMAT_1080P_50_00_SMPTE274_3G_LEVEL_A
39 1080P 50.00Hz (SMPTE274) 3G Level A
Definition nvapi.h:19713
@ NVVIOSIGNALFORMAT_1080P_24_00_SMPTE274
12 1080p 24.00Hz (SMPTE274)
Definition nvapi.h:19684
@ NVVIOSIGNALFORMAT_2048P_25_00_SMPTE372_3G_LEVEL_B
51 2048p 25.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19726
@ NVVIOSIGNALFORMAT_720P_59_94_SMPTE296
15 720p 59.94Hz (SMPTE296)
Definition nvapi.h:19687
@ NVVIOSIGNALFORMAT_1080I_59_94_SMPTE274
07 1080i 59.94Hz (SMPTE274)
Definition nvapi.h:19679
@ NVVIOSIGNALFORMAT_1080P_59_94_SMPTE274_3G_LEVEL_A
40 1080P 59.94Hz (SMPTE274) 3G Level A
Definition nvapi.h:19714
@ NVVIOSIGNALFORMAT_576I_50_00_SMPTE259_PAL
02 576i 50.00Hz (SMPTE259) PAL
Definition nvapi.h:19674
@ NVVIOSIGNALFORMAT_1080P_59_94_SMPTE274_3G_LEVEL_B
56 1080p 59.94Hz (SMPTE274) 3G Level B
Definition nvapi.h:19731
@ NVVIOSIGNALFORMAT_2048P_23_98_SMPTE372
31 2048p 23.98Hz (SMPTE372)
Definition nvapi.h:19703
@ NVVIOSIGNALFORMAT_2048I_47_96_SMPTE372_3G_LEVEL_B
64 2048i 47.96Hz (SMPTE372) 3G Level B
Definition nvapi.h:19739
@ NVVIOSIGNALFORMAT_1080I_50_00_SMPTE274
08 1080i 50.00Hz (SMPTE274)
Definition nvapi.h:19680
@ NVVIOSIGNALFORMAT_1080P_25_00_SMPTE274_3G_LEVEL_B
50 1080p 25.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19725
@ NVVIOSIGNALFORMAT_1080P_60_00_SMPTE274_3G_LEVEL_A
41 1080P 60.00Hz (SMPTE274) 3G Level A
Definition nvapi.h:19715
@ NVVIOSIGNALFORMAT_720P_23_98_SMPTE296
23 720p 23.98Hz (SMPTE296)
Definition nvapi.h:19695
@ NVVIOSIGNALFORMAT_1080PSF_23_98_SMPTE274
38 1080PsF 23.98Hz (SMPTE274)
Definition nvapi.h:19711
@ NVVIOSIGNALFORMAT_1080I_50_00_SMPTE295
05 1080i 50.00Hz (SMPTE295)
Definition nvapi.h:19677
@ NVVIOSIGNALFORMAT_1080P_30_00_SMPTE274
09 1080p 30.00Hz (SMPTE274)
Definition nvapi.h:19681
@ NVVIOSIGNALFORMAT_487I_59_94_SMPTE259_NTSC
01 487i 59.94Hz (SMPTE259) NTSC
Definition nvapi.h:19673
@ NVVIOSIGNALFORMAT_2048P_24_00_SMPTE372_3G_LEVEL_B
53 2048p 24.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19728
@ NVVIOSIGNALFORMAT_2048P_29_97_SMPTE372_3G_LEVEL_B
60 2048p 29.97Hz (SMPTE372) 3G Level B
Definition nvapi.h:19735
@ NVVIOSIGNALFORMAT_2048I_48_00_SMPTE372
32 2048i 48.00Hz (SMPTE372)
Definition nvapi.h:19704
@ NVVIOSIGNALFORMAT_2048P_24_00_SMPTE372
30 2048p 24.00Hz (SMPTE372)
Definition nvapi.h:19702
@ NVVIOSIGNALFORMAT_2048I_59_94_SMPTE372_3G_LEVEL_B
58 2048i 59.94Hz (SMPTE372) 3G Level B
Definition nvapi.h:19733
@ NVVIOSIGNALFORMAT_2048I_50_00_SMPTE372
29 2048i 50.00Hz (SMPTE372)
Definition nvapi.h:19701
@ NVVIOSIGNALFORMAT_1080P_29_97_SMPTE274
10 1080p 29.97Hz (SMPTE274)
Definition nvapi.h:19682
@ NVVIOSIGNALFORMAT_1035I_59_94_SMPTE260
04 1035i 59.94Hz (SMPTE260)
Definition nvapi.h:19676
@ NVVIOSIGNALFORMAT_2048I_50_00_SMPTE372_3G_LEVEL_B
47 2048i 50.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19722
@ NVVIOSIGNALFORMAT_2048P_23_98_SMPTE372_3G_LEVEL_B
62 2048p 29.98Hz (SMPTE372) 3G Level B
Definition nvapi.h:19737
@ NVVIOSIGNALFORMAT_2048I_60_00_SMPTE372_3G_LEVEL_B
44 2048i 60.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19719
@ NVVIOSIGNALFORMAT_1080P_60_00_SMPTE274_3G_LEVEL_B
42 1080p 60.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19717
@ NVVIOSIGNALFORMAT_END
65 To indicate end of signal format list
Definition nvapi.h:19741
@ NVVIOSIGNALFORMAT_1080I_60_00_SMPTE274_3G_LEVEL_B
43 1080i 60.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19718
@ NVVIOSIGNALFORMAT_1080P_29_97_SMPTE274_3G_LEVEL_B
59 1080p 29.97Hz (SMPTE274) 3G Level B
Definition nvapi.h:19734
@ NVVIOSIGNALFORMAT_1080P_23_98_SMPTE274_3G_LEVEL_B
61 1080p 29.98Hz (SMPTE274) 3G Level B
Definition nvapi.h:19736
@ NVVIOSIGNALFORMAT_1080PSF_30_00_SMPTE274
36 1080PsF 30.00Hz (SMPTE274)
Definition nvapi.h:19709
@ NVVIOSIGNALFORMAT_1080P_24_00_SMPTE274_3G_LEVEL_B
52 1080p 24.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19727
@ NVVIOSIGNALFORMAT_1080PSF_25_00_SMPTE274
34 1080PsF 25.00Hz (SMPTE274)
Definition nvapi.h:19707
@ NVVIOSIGNALFORMAT_1080P_50_00_SMPTE274_3G_LEVEL_B
45 1080p 50.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19720
@ NVVIOSIGNALFORMAT_1080PSF_29_97_SMPTE274
35 1080PsF 29.97Hz (SMPTE274)
Definition nvapi.h:19708
@ NVVIOSIGNALFORMAT_1080I_47_96_SMPTE274_3G_LEVEL_B
63 1080i 47.96Hz (SMPTE274) 3G Level B
Definition nvapi.h:19738
@ NVVIOSIGNALFORMAT_1080I_48_00_SMPTE274_3G_LEVEL_B
54 1080i 48.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19729
@ NVVIOSIGNALFORMAT_720P_24_00_SMPTE296
22 720p 24.00Hz (SMPTE296)
Definition nvapi.h:19694
@ NVVIOSIGNALFORMAT_720P_29_97_SMPTE296
20 720p 29.97Hz (SMPTE296)
Definition nvapi.h:19692
@ NVVIOSIGNALFORMAT_1035I_60_00_SMPTE260
03 1035i 60.00Hz (SMPTE260)
Definition nvapi.h:19675
@ NVVIOSIGNALFORMAT_2048P_30_00_SMPTE372
24 2048p 30.00Hz (SMPTE372)
Definition nvapi.h:19696
@ NVVIOSIGNALFORMAT_2048P_25_00_SMPTE372
28 2048p 25.00Hz (SMPTE372)
Definition nvapi.h:19700
@ NVVIOSIGNALFORMAT_2048I_60_00_SMPTE372
26 2048i 60.00Hz (SMPTE372)
Definition nvapi.h:19698
@ NVVIOSIGNALFORMAT_1080PSF_24_00_SMPTE274
37 1080PsF 24.00Hz (SMPTE274)
Definition nvapi.h:19710
@ NVVIOSIGNALFORMAT_2048P_30_00_SMPTE372_3G_LEVEL_B
49 2048p 30.00Hz (SMPTE372) 3G Level B
Definition nvapi.h:19724
@ NVVIOSIGNALFORMAT_1080I_47_96_SMPTE274
18 1080I 47.96Hz (SMPTE274)
Definition nvapi.h:19690
@ NVVIOSIGNALFORMAT_2048I_59_94_SMPTE372
27 2048i 59.94Hz (SMPTE372)
Definition nvapi.h:19699
@ NVVIOSIGNALFORMAT_1080P_30_00_SMPTE274_3G_LEVEL_B
48 1080p 30.00Hz (SMPTE274) 3G Level B
Definition nvapi.h:19723
@ NVVIOSIGNALFORMAT_1080I_48_00_SMPTE274
17 1080I 48.00Hz (SMPTE274)
Definition nvapi.h:19689
@ NVVIOSIGNALFORMAT_720P_30_00_SMPTE296
19 720p 30.00Hz (SMPTE296)
Definition nvapi.h:19691
@ NVVIOSIGNALFORMAT_1080P_23_976_SMPTE274
13 1080p 23.976Hz (SMPTE274)
Definition nvapi.h:19685
@ NVVIOSIGNALFORMAT_1080P_25_00_SMPTE274
11 1080p 25.00Hz (SMPTE274)
Definition nvapi.h:19683
@ NVVIOSIGNALFORMAT_2048P_29_97_SMPTE372
25 2048p 29.97Hz (SMPTE372)
Definition nvapi.h:19697
@ NVVIOSIGNALFORMAT_720P_25_00_SMPTE296
21 720p 25.00Hz (SMPTE296)
Definition nvapi.h:19693
@ NVVIOSIGNALFORMAT_2048I_47_96_SMPTE372
33 2048i 47.96Hz (SMPTE372)
Definition nvapi.h:19705
@ NVVIOSIGNALFORMAT_NONE
Invalid signal format.
Definition nvapi.h:19672
@ NVVIOSIGNALFORMAT_720P_50_00_SMPTE296
16 720p 50.00Hz (SMPTE296)
Definition nvapi.h:19688
@ NVVIOVIDEOSTANDARD_SMPTE259
SMPTE259.
Definition nvapi.h:19748
@ NVVIOVIDEOSTANDARD_SMPTE372
SMPTE372.
Definition nvapi.h:19753
@ NVVIOVIDEOSTANDARD_SMPTE295
SMPTE295.
Definition nvapi.h:19751
@ NVVIOVIDEOSTANDARD_SMPTE260
SMPTE260.
Definition nvapi.h:19749
@ NVVIOVIDEOSTANDARD_SMPTE274
SMPTE274.
Definition nvapi.h:19750
@ NVVIOVIDEOSTANDARD_SMPTE296
SMPTE296.
Definition nvapi.h:19752
@ NVVIOINTERLACEMODE_PSF
Progressive Segment Frame (psf)
Definition nvapi.h:19768
@ NVVIOINTERLACEMODE_PROGRESSIVE
Progressive (p)
Definition nvapi.h:19766
@ NVVIOINTERLACEMODE_INTERLACE
Interlace (i)
Definition nvapi.h:19767
@ NVVIOSYNCSOURCE_COMPSYNC
COMP Sync (Composite input)
Definition nvapi.h:19814
@ NVVIOSYNCSOURCE_SDISYNC
SDI Sync (Digital input)
Definition nvapi.h:19813
Definition nvapi.h:2623
Definition nvapi.h:7331
Definition nvapi.h:7343
Definition nvapi.h:7356
Definition nvapi.h:7370
Definition nvapi.h:7385
Definition nvapi.h:3254
Definition nvapi.h:3247
Definition nvapi.h:22907
Definition nvapi.h:22887
Definition nvapi.h:6528
Definition nvapi.h:998
Definition nvapi.h:1014
Definition nvapi.h:8533
Definition nvapi.h:8540
Definition nvapi.h:8590
Definition nvapi.h:17484
Definition nvapi.h:9015
Definition nvapi.h:5666
Definition nvapi.h:23037
Definition nvapi.h:1923
Definition nvapi.h:5207
Definition nvapi.h:4515
Definition nvapi.h:4522
Used in NvAPI_GPU_GetPstates20() interface call.
Definition nvapi.h:1261
Definition nvapi.h:5275
Definition nvapi.h:3983
Definition nvapi.h:4563
Used in NvAPI_GSync_QueryCapabilities().
Definition nvapi.h:10114
Definition nvapi.h:10122
Definition nvapi.h:10131
Used in NvAPI_GSync_GetControlParameters() and NvAPI_GSync_SetControlParameters().
Definition nvapi.h:10335
Definition nvapi.h:10358
Used in NV_GSYNC_CONTROL_PARAMS.
Definition nvapi.h:10323
Definition nvapi.h:10212
Definition nvapi.h:10201
Definition nvapi.h:10522
Definition nvapi.h:10532
Used in NvAPI_GSync_GetSyncStatus().
Definition nvapi.h:10470
Definition nvapi.h:6667
Definition nvapi.h:6684
Definition nvapi.h:7420
Definition nvapi.h:7454
Definition nvapi.h:7516
Definition nvapi.h:7643
Definition nvapi.h:7672
Definition nvapi.h:7786
Definition nvapi.h:17741
Definition nvapi.h:17659
Licensable features.
Definition nvapi.h:4162
Definition nvapi.h:4173
Definition nvapi.h:4184
Definition nvapi.h:4195
Definition nvapi.h:4101
Used in NV_LICENSABLE_FEATURES.
Definition nvapi.h:4114
Definition nvapi.h:4123
Definition nvapi.h:4133
Definition nvapi.h:4144
Definition nvapi.h:4025
Definition nvapi.h:15756
Definition nvapi.h:15766
See NvAPI_DISP_GetMonitorCapabilities().
Definition nvapi.h:8113
Definition nvapi.h:8102
Definition nvapi.h:8045
See NvAPI_DISP_GetMonitorCapabilities().
Definition nvapi.h:8056
Definition nvapi.h:8141
Basic per-display settings that are used in setting/getting the Mosaic mode.
Definition nvapi.h:9216
Definition nvapi.h:9594
Definition nvapi.h:9612
Definition nvapi.h:9630
Definition nvapi.h:9646
Definition nvapi.h:9254
Definition nvapi.h:9264
Definition nvapi.h:15673
Definition nvapi.h:888
Definition nvapi.h:15719
Definition nvapi.h:895
Definition nvapi.h:3911
Definition nvapi.h:3693
Definition nvapi.h:3775
Definition nvapi.h:8630
Definition nvapi.h:17617
Definition nvapi.h:17530
Definition nvapi.h:7972
Definition nvapi.h:645
Definition nvapi.h:20527
Definition nvapi.h:21246
Definition nvapi.h:21920
Definition nvapi.h:21929
Definition nvapi.h:21940
Definition nvapi.h:21954
Enum to decide on the datatype of setting value.
Definition nvapi.h:21857
Definition nvapi.h:21820
Definition nvapi.h:21978
Definition nvapi.h:21886
Definition nvapi.h:21863
Device capabilities.
Definition nvapi.h:20000
Input channel status.
Definition nvapi.h:20031
Colorspace conversion.
Definition nvapi.h:20173
Definition nvapi.h:20213
Definition nvapi.h:20473
Definition nvapi.h:20486
Definition nvapi.h:20498
Data format details.
Definition nvapi.h:20166
Gamma correction.
Definition nvapi.h:20191
Gamma ramp (10-bit index)
Definition nvapi.h:20100
Gamma ramp (8-bit index)
Definition nvapi.h:20092
Input device configuration.
Definition nvapi.h:20460
Input device status.
Definition nvapi.h:20042
Output device configuration.
Definition nvapi.h:20358
Definition nvapi.h:20386
Definition nvapi.h:20415
Output region.
Definition nvapi.h:20083
Output device status.
Definition nvapi.h:20049
Definition nvapi.h:20845
Signal format details.
Definition nvapi.h:20132
Video device status.
Definition nvapi.h:20068
Stream configuration.
Definition nvapi.h:20446
Sync delay.
Definition nvapi.h:20109
Video mode information.
Definition nvapi.h:20121
Definition nvapi.h:22732
Definition nvapi.h:22722
Definition nvapi.h:22704
Definition nvapi.h:22686
Definition nvapi.h:3232
Definition nvapi.h:8198
Definition nvapi.h:1352
Definition nvapi.h:822
Definition nvapi.h:831
Definition nvapi.h:783
Definition nvapi.h:6630
Definition nvapi.h:302
Used in NvAPI_GPU_GetEDID()
Definition nvapi.h:309
Used in NvAPI_GPU_GetEDID()
Definition nvapi.h:317
Core NV_EVENT_REGISTER_CALLBACK structure declaration.
Definition nvapi.h:3584
Definition nvapi.h:8778
Used in NvAPI_GPU_GetArchInfo()
Definition nvapi.h:2687
Definition nvapi.h:2840
Definition nvapi.h:5526
Definition nvapi.h:5025
Definition nvapi.h:5053
Definition nvapi.h:4855
Definition nvapi.h:3504
Definition nvapi.h:3387
Definition nvapi.h:3369
HDPC support status - used in NvAPI_GPU_GetHDCPSupportStatus()
Definition nvapi.h:3192
Used in NvAPI_GPU_GetPstates20() interface call.
Definition nvapi.h:1218
Used to describe both voltage and frequency deltas.
Definition nvapi.h:1144
Definition nvapi.h:4631
Definition nvapi.h:4660
Used to describe single base voltage entry.
Definition nvapi.h:1201
Used to describe single clock entry.
Definition nvapi.h:1160
Definition nvapi.h:4942
Definition nvapi.h:4958
Used in NvAPI_I2CRead() and NvAPI_I2CWrite()
Definition nvapi.h:2920
Used in NvAPI_I2CRead() and NvAPI_I2CWrite()
Definition nvapi.h:2940
Used in NvAPI_I2CRead() and NvAPI_I2CWrite()
Definition nvapi.h:2961
Definition nvapi.h:7170
Definition nvapi.h:7192
Definition nvapi.h:6775
Adding an Auto bit to each field.
Definition nvapi.h:6950
Definition nvapi.h:22772
Definition nvapi.h:9225
Definition nvapi.h:9756
Used in NvAPI_GetSupportedMosaicTopologies().
Definition nvapi.h:9956
Definition nvapi.h:9201
This structure defines the topology details.
Definition nvapi.h:9087
Definition nvapi.h:9318
Used in NvAPI_GetCurrentMosaicTopology() and NvAPI_SetCurrentMosaicTopology().
Definition nvapi.h:9935
Definition nvapi.h:3566
Definition nvapi.h:3641
Definition nvapi.h:3650
Definition nvapi.h:3735
Definition nvapi.h:8738
Definition nvapi.h:7953
Definition nvapi.h:719
Definition nvapi.h:559
Definition nvapi.h:4331
Definition nvapi.h:4270
Definition nvapi.h:4467
Definition nvapi.h:4474
Definition nvapi.h:4419
Definition nvapi.h:4441
Definition nvapi.h:20518
Definition nvapi_lite_common.h:170
Definition nvapi.h:605