Power Management for Jetson TX2 Series Devices
NVIDIA® Jetson™ TX2 series devices and NVIDIA® Jetson Board Support Package (BSP) provide many features related to power management, thermal management, and electrical management. These features deliver the best user experience possible given the constraints of a particular platform. The target user experience ensures the perception that the device provides:
• Uniformly high performance
• Excellent battery life
• Perfect stability
• Comfortable and cool to the touch
This topic describes the power, thermal, and electrical management features visible to software, as well as some tools and related techniques.
Interacting Features
Power, thermal, and electrical management features place dynamic constraints on many operational settings (“knobs”), such as:
• Clock gate settings
• Clock frequencies
• Power gate (or regulator enable) settings
• Voltages
• Processor power state (i.e., which idle state is selected for the CPU)
• Peripheral power state (i.e., which idle state is selected for an I/O controller)
• Chipset power state
• Availability of CPU cores to the OS
Some of these knobs are constrained by more than one feature. For example, cpufreq implements load based scaling based on how busy the CPU is, and adjusts the CPU frequency accordingly. CPU thermal management, however, can override the target frequency of cpufreq. Therefore, before you attempt to debug power, performance, thermal, or electrical problems, familiarize yourself with all of the power, thermal, and electrical management features in BSP.
Kernel Space Power Saving Features
This section describes BSP features that save power and extend battery life. Many of these features are implemented by the Linux kernel, with support from firmware and hardware, and without significant involvement from the user space.
Chipset Power States
The supported power states are listed in order of increasing flexibility or configurability:
• Off: There is only one way for a system to be off.
• Deep Sleep (SC7) offers a small amount of configurability. For example, prior to entering Deep Sleep, software can select which of the many hardware wake events can wake the chip from Deep Sleep.
• Active state is extraordinarily flexible in terms of power and performance. It encompasses activity levels from low power audio playback through peak performance. Power consumption in the active state can range from tens of milliwatts up to several watts.
Supported Power States
The supported power states are.
Power State | Functionality | Characteristics |
Off | Power rails | None of the power rails supplying the SoC and DRAM are powered. |
State | No state is maintained in the SoC or DRAM. | |
Exiting | Into Active state via cold boot. | |
Deep Sleep (SC7) | Power rails | VDD_RTC, VDDIO_DDR, VDDIO_SYS, and DRAM power rails are powered on. VDD_CORE and VDD_CPU are powered off. |
State | The SoC maintains a small amount of state information in the PMC block. DRAM maintains state. | |
Exiting | Into Active state via a pre-defined set of wake events. | |
Active | Power rails | VDD_RTC, VDDIO_DDR, VDDIO_SYS, VDD_CORE, and DRAM rails are powered on. Other power rails, including VDD_CPU, may be powered on. |
State | Software actively manages the power states of the devices that make up the SoC. | |
Exiting | Software can initiate a transition from Active to any other power state. |
Power State Mapping to Linux
BSP maps hardware power states onto Linux power states as follows.
Chipset Power State | Linux Power State | Comments |
Off | Off | — |
Deep Sleep (SC7) | Suspend to RAM | Software can choose whether to enter Deep Sleep before the OS enters suspend. |
Active | Running/Idle (display on or off) | Many SoC devices may be idle or disabled under driver control. For example, VDD_GPU may be powered off and the companion GPU may be power-gated. |
Note: | For Jetson TX2 the name of the chipset power state is SCy instead of LPx. |
Deep Sleep (SC7)
You can initiate deep sleep from the user space with this command if the systemd init system is in use:
$ sudo systemctl suspend
Alternatively, you can use this:
$ sudo bash -c “echo mem > /sys/power/state”
The first method of entering deep sleep is preferred because it cooperates better with systemd, which maintains the Linux runlevel. Use the second method if your system is not running systemd.
The system can be awakened from deep sleep by common wake sources available on Jetson platforms:
Wake Source | Usage |
Power button | Press and release the power button on the Jetson device. If the power button is not available, connect then disconnect the power button pin and ground. |
RTC alarm | Before entering low power state, program the RTC alarm with the command: $ sudo bash -c "echo `date '+%s' -d '+ 10 seconds'` > /sys/class/rtc/rtc0/wakealarm" |
Micro USB cable hotplug | Connect or disconnect a micro-USB cable to the USB micro-B port for flashing the device. |
USB remote wakeup | Press any key on a USB keyboard connected to the device. |
Wake on LAN | On another machine on the same LAN, enter: $ sudo etherwake -i <interface> <MAC_address_of_target> |
SD card detection | Insert or remove SD card. |
Clock and Voltage Management
Because frequency is proportional to voltage, dynamic voltage scaling is closely related to frequency scaling. For example, higher frequencies require higher voltages and vice versa.
Most clock register manipulation on Jetson TX2 is handled by the Boot and Power Management (BPMP) firmware – power management firmware running on the BPMP. A Linux kernel driver on the CPU exposes a somewhat simplified view of the physical clock tree to software on the main CPU via the Linux Common Clock Framework.
Each of the significant clock domains on the chip has its own dedicated clock source known as a Noise Aware Frequency Lock Loop (NAFLL).
Regulator Framework
The Linux regulator framework provides an abstraction that allows regulator consumer drivers to dynamically adjust voltage or current regulators at runtime, without knowledge of the underlying hardware power tree.
The framework provides a mechanism that platform initialization code can use to declare a power tree topology and assign a driver that provides regulators for each node in the hardware power tree. Such a driver is called a regulator provider driver.
BSP configures the platform power tree appropriately for SoC devices. Additionally, drivers within BSP act as regulator consumers, where appropriate.
When porting BSP to a new platform, ensure that:
• The platform power tree is configured to match the underlying hardware.
• All drivers for peripheral devices use the regulator consumer APIs correctly.
• The Device Tree and board configuration file information for your new platform avoids conflicts between functions using the same I/O pads. BSP drivers registering as regulator consumers can cause I/O pads on the chip to be unavailable for other functions.
The SoC core power rails (VDD_CORE, VDD_CPU, VDD_SRAM, VDD_GPU) are under the direct control of the BPMP firmware. They are configured via the BPMP device tree blob (which is distinct from the Linux device tree blob).
CPU Power Management
The CPU power management strategy includes dynamic frequency scaling with dynamic voltage scaling, idle power states, and core management tuned for the Jetson TX2 architecture.
Frequency Management with cpufreq
BSP implements CPU Dynamic Frequency Scaling (DFS) with the Linux cpufreq subsystem. The cpufreq subsystem comprises:
• Platform drivers to implement the clock adjustment mechanism.
• Governors to implement frequency scaling policies.
• Core framework to connect governors to platform drivers
The policy for frequency scaling depends on which cpufreq governor is selected at runtime.
For details, see the information at:
<top>/kernel/kernel-4.9/Documentation/cpu-freq/
For each Jetson hardware reference design, NVIDIA selects a cpufreq governor and tunes it to achieve a balance between power and performance.
When a governor requests a CPU frequency change, the SoC-specific cpufreq platform driver reconciles that request with constraints imposed by thermal and electrical limits, and updates the CPU clock speed.
Jetson TX2 uses an NAFLL to clock each CPU. The NAFLLs are configured for AVFS. Hardware, with the assistance of the BPMP, ensures that the CPU voltage is appropriate for the NAFLL to deliver requested CPU frequencies.
Idle Management with cpuidle
The Linux cpuidle infrastructure supports the implementation of SoC-specific idle states for each CPU core. cpuidle lacks direct support for idle states applicable to an entire CPU cluster and for idle states extending beyond a CPU cluster.
For more information on the Linux cpuidle infrastructure, see:
<top>/kernel/kernel-4.9/Documentation/cpuidle/
NVIDIA provides an SoC-specific cpuidle driver that plugs into the cpuidle framework to enable CPU idle power management.
CPU Idle
For each core there is an idle task which is scheduled when no other runnable tasks are left in the run queue for that core. This task places the core in a low-power state selected by the cpuidle governor. The core stays in that state until an interrupt wakes it up to process more work.
When the last active core in a CPU cluster goes into an idle or offline state, the idle task puts the entire CPU cluster in a low-power state.
Idle States
The table below summarizes the different CPU core, cluster, and CCplex (CPU Complex) idle states available on Jetson TX2, and the BSP software support for them.
Type of State | State | Meaning | Software Support |
Core state | C1 | Clock gating | Supported |
C6 | Virtual retention (power gating and architecture state restored by MTS) | Supported (Denver cores only) | |
C7 | Power gating | Supported | |
Cluster state | CC1 | Auto clock gating | Supported |
CC3 | fmax@Vmin | Supported | |
CC6 | Cluster power gating (includes non-CPU logic) | Supported | |
CC7 | Cluster rail gating | Not supported | |
CCplex state | CCP3 | EMC reduction state during CC3 | Not supported |
Core states are denoted as Cx states, cluster states are denoted as CCx states, and CCplex states are denoted as CCPx states.
To enable CPU idle
To enable CPU idle you must enable the appropriate kernel configuration option and the appropriate device tree node. (Enabling either one alone is not effective.)
• To enable CPU idle in the configuration file, set this option:
CONFIG_CPU_IDLE=y
• To enable CPU idle in the device tree, enable the device tree node cpuidle:
cpuidle {
compatible = "nvidia,tegra18x-cpuidle";
status = "okay";
};
To disable cpuidle at boot time
• Disable the device tree node cpuidle.
To display CPU idle status
• To determine whether CPU idle is enabled, enter these commands:
$ cat /sys/devices/system/cpu/cpuidle/current_driver
If CPU idle is enabled, the command displays:
tegra18x_idle_a57
To disable a core/cluster power state at boot time
Use either of the following procedures. Both procedures apply to the device trees:
tegra186-a57-cpuidle.dtsi
tegra186-denver-cpuidle.dtsi
• Remove or disable the appropriate core/cluster state nodes.
or
• Modify the appropriate core/cluster state nodes by setting the property min-residency-us to a high value, e.g. 0xffffffff.
For example, to disable the C6 power state node in the device tree tegra186-denver-cpuidle.dtsi:
DENVER_C6: c6 {
compatible = "nvidia,tegra186-cpuidle-denver";
state-name = "Virtual core powergate";
wakeup-latency-us = <190>;
min-residency-us = <0xffffffff>;
power = <60>;
pmstate = <0x6>;
arm,psci-suspend-param= <0x6>;
status = "okay";
};
To get and set a CPU core’s power state
The pathnames of the nodes that represent core power states are:
/sys/devices/system/cpu/cpu<x>/cpuidle/state<y>
Where:
• <x> is a core ID.
• Core IDs 1 and 2 represent Denver cores.
• Core IDs 0, 3, 4, and 5 represent A57 cores.
• Core IDs 6 and 7 are not valid.
• <y> is the index of core power state:
• On a Denver core, 0 for C1, 1 for C6, or 2 for C7.
• On an A57 core, 0 for C1 or 1 for C7.
Note: | A core power state’s status is 1 if the state is disabled, and 0 if it is enabled. This is the reverse of the usual Boolean sense of 0 and 1. |
To get the status of core power state <y> on core <x>, read the appropriate node. To set the status, write an ASCII 0 to 1 to the node.
Following are several useful commands for getting and setting the core power state.
• To display the name of the core power state with index <y>, enter the command:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/name
For example:
• On a Denver core this command displays C1:
$ cat /sys/devices/system/cpu<x>/cpuidle/state0/name
This command displays C6:
$ cat /sys/devices/system/cpu<x>/cpuidle/state1/name
(Here <x> must be 1 or 2, the CPU IDs of the Denver cores.)
• On an A57 core, this command displays C1:
$ cat /sys/devices/system/cpu<x>/cpuidle/state0/name
This command displays C7:
$ cat /sys/devices/system/cpu<x>/cpuidle/state1/name
(Here <x> must be 0, 3, 4, or 5, the CPU IDs of the A57 cores.)
• To get the status of core power state <y> on core <x>:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/disable
• To change the status of core power state <y> on CPU core <x>:
echo <b> > /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/disable
Note: | Remember that a status of 1 disables the core power state is disabled, and 0 enables it. |
To get cluster states
• To get the status of the cluster states enabled for each cluster, read the appropriate node for the type of cores in the cluster:
For A57 cores, read:
/sys/kernel/debug/cpuidle_a57/deepest_cc_state
For Denver cores, read:
/sys/kernel/debug/cpuidle_denver/deepest_cc_state
The value returned is:
• 1: Only CC1 is enabled
• 6: CC1 and CC6 are enabled
• 7: CC1, CC6 and CC7 are enabled
For example, to get the status of the cluster states on a Denver cluster, enter this command:
$ cat /sys/kernel/debug/cpuidle_denver/deepest_cc_state
To get the per-core state statistics
• To get the number of times the kernel requested a specified core to enter a specified state, read this node:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/usage
• To get the number of times a specified core actually entered a specified state, enter this command:
$ cat /sys/kernel/debug/tegra_mce/cstats
• To get the total time in microseconds that a specified core has spent in a specified state since boot, read the following device:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/time
For example, to get the number of times that Denver core 2 has entered state C6, enter this command:
$ cat /sys/devices/system/cpu/cpu2/cpuidle/state1/usage
To get the total time in microseconds that Denver core 2 has spent in state C6, enter this command:
$ cat /sys/devices/system/cpu/cpu2/cpuidle/state1/time
Memory Power Management
NVIDIA SoC chipsets include power saving features whose operation is largely invisible to software at runtime. Most of those features are statically enabled at boot, according to settings in the boot configuration table (BCT).
Additionally, BSP implements EMC frequency scaling, which is dynamic frequency scaling for the memory controller (EMC/MC) and DRAM. This is a critical power saving feature that requires tuning and characterization for each new printed circuit board design.
The calibration results include a BCT and an EMC DVFS table specific to the board design. The EMC DVFS table must be included in the platform BPMP device tree file.
EMC Frequency Scaling Policy
The following factors affect EMC frequency scaling policy at runtime:
• The entries in the EMC DVFS table
• The average memory bandwidth used (as measured by hardware)
• Requests made by various device drivers (cpufreq, graphics drivers, USB, HDMI™, and display)
• Any limits dynamically imposed by thermal throttling
Supported Modes and Power Efficiency
Jetson TX2 is designed with a high efficiency Power Management Integrated Circuit (PMIC), voltage regulators, and power trees to optimize power efficiency. It supports two optimized power budgets:
• Max‑Q, maximizing power efficiency: 7.5 watts for Jetson TX2/TX2 4GB, and 10 watts for Jetson TX2i
• Max-P, balancing power efficiency and speed: 15 watts for Jetson TX2/TX2 4GB, and 20 watts for Jetson TX2i
Each power budget allows several configurations with different CPU frequencies and numbers of cores online.
Capping the memory, CPU, and GPU frequencies at pre-qualified level confines the module to the target mode. The configurations pre-defined by NVIDIA are as follows.
NVPModel Clock Configuration for Jetson TX2 and TX2 4GB
Property | Mode | |||||
MAXN | MAX-Q | MAX-P | MAX-P* | |||
Power budget | n/a | 7.5W | 15W | 15W | ||
Mode ID | 0 | 1 | 2 | 3 | ||
Online A57 CPU | 4 | 4 | 4 | 4 | ||
Online D15 CPU | 2 | 0 | 2 | 0 | ||
A57 CPU max frequency (MHz) | 2000 | 1200 | 1400 | 2000 | ||
D15 CPU max frequency (MHz) | 2000 | n/a | 1400 | N/A | ||
GPU max frequency (MHz) | 1300 | 850 | 1122 | 1122 | ||
Memory max frequency (MHz) | 1866 | 1331 | 1600 | 1600 | ||
SOC clocks max frequency (MHz) All modes | adsp 300 ape 150 axi_cbb 409.6 bpmp 1088 bpmp_apb 408 host1x 408 | isp 1126.4 display 810 display_hub 652.8 nvcsi 225 nvdec 1203.2 nvenc 1164.8 | nvjpg 857.6 sce 960 se 985.6 tsec 716.8 vi 1036.8 vic 1024 | |||
* The default mode is MAX-P (mode ID 3). | ||||||
For Jetson TX2i, power budgets for Max-Q and Max-P are 10 watts and 20 watts respectively.
NVPModel Clock Configuration for Jetson TX2i UCM1 Profile
Property | Mode | |||||
MAXN | MAX-Q | MAX-P | MAX-P* | |||
Power budget | n/a | 10W | 20W | 20W | ||
Mode ID | 0 | 1 | 2 | 3 | ||
Online A57 CPU | 4 | 4 | 4 | 4 | ||
Online D15 CPU | 2 | 0 | 2 | 0 | ||
A57 CPU max frequency (MHz) | 1920 | 1200 | 1400 | 1920 | ||
D15 CPU max frequency (MHz) | 1958 | n/a | 1400 | n/a | ||
GPU max frequency (MHz) | 1236 | 850 | 1122 | 1122 | ||
Memory max frequency (MHz) | 1600 | 1600 | 1600 | 1600 | ||
SOC clocks max frequency (MHz) All modes | adsp 951.9 ape 158.6 axi_cbb 499.2 bpmp 819.2 bpmp_apb 408 host1x 496.9 | isp 857.6 display 1620 display_hub 652.8 nvcsi 225 nvdec 908.8 nvenc 883.2 | nvjpg 646.4 sce 729.6 se 729.6 tsec 569.6 vi 780.8 vic 780.8 | |||
* The default mode is MAX-P (mode ID 3). | ||||||
NVPModel Clock Configuration for Jetson TX2i UCM2 Profile
Property | Mode | ||||||
MAXN | MAX-Q | MAX-P | MAX-P* | ||||
Power budget | n/a | 10W | 20W | 20W | |||
Mode ID | 0 | 1 | 2 | 3 | |||
Online A57 CPU | 4 | 4 | 4 | 4 | |||
Online D15 CPU | 2 | 0 | 2 | 0 | |||
A57 CPU max frequency (MHz) | 1420 | 1200 | 1400 | 1420 | |||
D15 CPU max frequency (MHz) | 1497 | n/a | 1400 | n/a | |||
GPU max frequency (MHz) | 918 | 850 | 918 | 918 | |||
Memory max frequency (MHz) | 1600 | 1600 | 1600 | 1600 | |||
SOC clocks max frequency (MHz) All modes | adsp 951.9 ape 158.6 axi_cbb 499.2 bpmp 819.2 bpmp_apb 408 host1x 496.9 | isp 857.6 display 1620 display_hub 652.8 nvcsi 225 nvdec 908.8 nvenc 883.2 | nvjpg 646.4 sce 729.6 se 729.6 tsec 569.6 vi 780.8 vic 780.8 | ||||
* The default mode is MAX-P (mode ID 3). | |||||||
NVPModel Clock Configuration for Jetson TX2 NX
Property | Mode | |||||
MAXN | MAX-Q | MAX-P | MAX-P* | |||
Power budget | n/a | 7.5W | 15W | 15W | ||
Mode ID | 0 | 1 | 2 | 3 | ||
Online A57 CPU | 4 | 4 | 4 | 4 | ||
Online D15 CPU | 2 | 0 | 2 | 0 | ||
A57 CPU max frequency (MHz) | 2000 | 1200 | 1400 | 2000 | ||
D15 CPU max frequency (MHz) | 2000 | n/a | 1400 | N/A | ||
GPU max frequency (MHz) | 1300 | 850 | 1122 | 1122 | ||
Memory max frequency (MHz) | 1600 | 1600 | 1600 | 1600 | ||
SOC clocks max frequency (MHz) All modes | adsp 600 ape 408 axi_cbb 408 bpmp 1088 bpmp_apb 408 host1x 408 | isp 1126.4 display 810 display_hub 508.8 nvcsi 225 nvdec 1203.2 nvenc 1164.8 | nvjpg 857.6 sce 960 se 985.6 tsec 716.8 vi 1036.8 vic 1024 | |||
To change the power mode
• Enter the command:
$ sudo /usr/sbin/nvpmodel -m <x>
Where <x> is the power mode ID (i.e. 0, 1, 2, 3, or 4).
• Alternatively, use the nvpmodel GUI front end. For more information, see To use the nvpmodel GUI, later in this topic.
Once you set a power mode, the module stays in that mode until you change it. The mode persists across power cycles and SC7.
To display the current power mode
• Enter the command:
$ sudo /usr/sbin/nvpmodel -q
• Alternatively, see the mode displayed to the right of the NVIDIA icon in the nvpmodel window’s menu bar. For more information, see To use the nvpmodel GUI, later in this topic.
To learn about other options
• Enter the command:
$ /usr/sbin/nvpmodel -h
To define a custom power mode
• Add a mode definition to the file:
$ /etc/nvpmodel.conf
This is an example entry for mode 2:
< POWER_MODEL ID=2 NAME=MAXP_CORE_ALL >
# cpu core settings
/sys/devices/system/cpu/cpu1/online 1
/sys/devices/system/cpu/cpu2/online 1
/sys/devices/system/cpu/cpu3/online 1
/sys/devices/system/cpu/cpu4/online 1
/sys/devices/system/cpu/cpu5/online 1
# cpu clock settings
# A57 cluster
/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq 0
/sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq 1400000
# Denver cluster
/sys/devices/system/cpu/cpu1/cpufreq/scaling_max_freq 1400000
# gpu clock settings
/sys/devices/17000000.gp10b/devfreq/17000000.gp10b/min_freq 0
/sys/devices/17000000.gp10b/devfreq/17000000.gp10b/max_freq 1120000000
# emc clock settings
/sys/kernel/nvpmodel_emc_cap/emc_iso_cap 1600000000
The unit of measure for the CPU frequency is KHz. The unit for GPU and EMMC frequency is hertz. You must assign each custom mode a unique number in the ID field. Test your use case to determine:
• How many active cores to use
• The frequency for each CPU cluster, and the GPU and EMC frequencies
The frequencies you select are subject to the EDP limit defined in mode 0.
Thermal Management
Thermal management is essential for system stability and quality of user experience. The Jetson TX2 thermal management provides the following capabilities:
• Sensing for on-board and on-die thermal sensor temperature reporting
• Cooldown for removing heat via the fan and for controlling heat via the software clock throttling
• Slowdown for hardware clock throttling
• Shutdown:for orderly software shutdown and hardware thermal shutdown
Previously, Jetson thermal management was performed by the software on the main CPU. Thermal management in Jetson TX2 is performed by:
• The Linux kernel, which monitors on-board thermal sensors, performs cooldown, and supports software and hardware thermal shutdown
• The Board and Power Management Processor (BPMP), which monitors on-die thermal sensors and performs slowdown and hardware thermal shutdown
The following table identifies each thermal management action and the associated module for the SoC.
Thermal Action | Linux Device Driver | Associated Module |
|---|---|---|
Sensing | soctherm.c | BPMP firmware |
aotag.c | BPMP firmware | |
nct1008.c | Kernel software | |
Cooldown for software throttling | tegraXX_throttle.c | Kernel software |
Cooldown for fan | pwm_fan.c | Kernel software |
Slowdown for hardware throttling | soctherm.c | BPMP firmware |
Software shutdown | thermal_core.c | Kernel software |
Hardware shutdown | soctherm.c and aotag.c | BPMP firmware |
nct1008.c | Kernel software |
Linux Thermal Framework
The Linux thermal framework provides generic user space and kernel space interfaces for working with devices that measure temperature and devices that control temperature. The central component of the framework is the thermal zone.
For more information about the Linux thermal framework, see:
<top>/kernel/kernel-4.9/Documentation/thermal/sysfs-api.txt
Thermal Zone
A thermal zone is a virtual object that represents an area on the die whose temperature is monitored and controlled. A thermal zone acts as an object with the following components:
• Temperature sensor
• Cooling device
• Trip points
• Governor
BSP includes drivers that provide interfaces to these components.
This topic introduces these components and demonstrates how they form a thermal zone on an NVIDIA SoC.
Configuring a Thermal Zone Using the Device Tree
A thermal zone provides knobs to tune the thermal response of the zone. BSP provides several thermal zones tuned to provide optimum thermal performance. You can modify the provided thermal zones by editing the entries in the device tree. You can define sensors to monitor temperature limits and perform cooling actions based on those limits. When a device becomes too hot, you can resolve the problem in most cases by tuning the thermal zone.
The following code snippet provides an example of a thermal zone for Jetson TX2 series platforms. This thermal zone monitors the temperature of the THERMAL_ZONE_CPU sensor. Clock throttling is performed using the CPU-balanced cooling device when the passive trip point, trip_bthrot, is crossed at 95.5 °C.
BCPU-therm {
status = “okay”;
polling-delay-passive = <500>;
thermal-zone-params {
governor-name = “step_wise”;
};
trips {
trip_critical {
temperature = <101000>;
type = “critical”;
hysteresis = <0>;
writable;
};
trip_bthrot {
temperature = <95500>;
type = “passive”;
hysteresis = <0>;
writable;
};
};
cooling-maps {
map0 {
trip = <&{/thermal-zones/BCPU-therm/trips/trip_bthrot}>;
cdev-type = “cpu-balanced”;
cooling-device = <&{/bthrot_cdev/cpu_balanced} THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
More information about thermal knobs, see:
<top>/kernel/kernel-4.9/Documentation/devicetree/bindings/thermal.txt
Temperature Sensors
A temperature sensor in a thermal zone is responsible for reporting the temperature in millidegrees Celsius. An NVIDIA SoC has several types of temperature sensors on the die and board.
For more information see Thermal Sensing in Linux.
Trip Points
Thermal management uses trip points to communicate with thermal zones. A trip point identifies the temperature at which to perform a thermal action.
Trip points are classified as active or passive, based on the type of cooling they trigger. A trip point is classified as critical if it triggers a thermal shutdown. A cooling map specifies how a cooling device is associated with certain trip points. BSP supports fan and clock throttling.
Cooling Devices
A cooling device reduces the temperature of a power dissipating device. There are essentially two types of cooling devices:
• An active cooling device, such as a fan, reduces the temperate of a power dissipating device by removing heat.
• A passive cooling device, such as software or hardware clock throttling, reduces temperature by reducing device performance, and so reducing heat dissipation.
For more information, see Thermal Cooling.
For more information, see Fan Management and Clock Throttling.
Governors
Thermal management requires some form of feedback control system that keeps the device within a safe operating temperature. A governor implements this feedback control loop. While the Linux thermal framework provides many different governors, BSP provides a simple Proportional Integral Derivative (PID) controller for all passive throttling needs.
BSP Specific Thermal Zones
BSP defines platform-specific thermal zones. The zones are tuned to provide the best performance within the thermal constraints of the device. Each thermal zone uses a temperature sensor that is controlled by either the Linux kernel or the BPMP firmware as described in the following table.
Thermal Zone | Thermal Sensor | Associated Module |
|---|---|---|
BCPU-therm | THERMAL_ZONE_CPU | BPMP firmware |
MCPU-therm | THERMAL_ZONE_AUX | BPMP firmware |
PLL-therm | THERMAL_ZONE_PLLX | BPMP firmware |
GPU-therm | THERMAL_ZONE_AO | BPMP firmware |
Tboard_tegra | tmp451 local sensor | Linux kernel |
Tdiode_tegra | tmp451 remote sensor | Linux kernel |
thermal-fan-est | Weighted average of CPU, AUX, and GPU | Linux kernel |
• For more information, see Thermal Management in BPMP.
• For information on AOTAG versus GPU-therm for GPU balanced throttles, see AOTAG in Thermal Sensing.
All gains achieved by tuning are limited by the Thermal Design Power (TDP) of the system. Tuning cannot remedy a faulty TDP. Removing all of the thermal zones does not guarantee maximum performance, and it can cause resets and/or irreversible damage to the device.
Thermal Management in Linux
The Linux kernel provided by BSP includes several drivers for on-die and on-board temperature sensing.
Thermal Sensors
Jetson TX2 has several types of sensors to support hardware and software cooling strategies.
NCT Sensors
BSP includes a driver for on-board sensor devices such as:
• NCT1008
• NCT72
• TMP451
These devices can sense their own temperature as well as sensing the temperature of a remote diode. NVIDIA SoC platforms have these sensors set up as follows:
Thermal Zone | Thermal Sensor | Sensed Location |
|---|---|---|
Tdiode_tegra | Remote sensor | Temperature on die near GPU |
Tboard_tegra | Local sensor | Temperature of the board |
BSP configures these sensors to operate in an extended mode to increase the temperature range to −64 °C to 191 °C.
Operation During SC7
On many platforms, the voltage rail that powers the sensor is gated when the SoC enters the SC7 state. Consequently, the sensor is stopped when the SoC enters SC7 and restarted when the SoC exits that state.
Thermal Capabilities
The NCT sensors generate thermal events for:
• Thermal zone trip points
• Hardware thermal shutdown
Correction Offset
The NCT sensors allow software to program a static offset temperature for the remote sensor. This accounts for any inaccuracy that may be present in the sensor hardware. BSP reads the offset from the device tree and programs it into the offset register on boot. The offset is calculated and validated via oil bath experiments.
BPMP Sensors
Jetson TX2 replaces the soctherm and aotag drivers in the Linux kernel with the tegra_bpmp_thermal sensor driver. This module registers itself as the sensor device driver with the Linux thermal framework for all the thermal sensors, except the NCT sensors.
Each BPMP sensor is exposed using the Application Binary Interface (ABI), and has an ABI name as shown in the table in BSP Specific Thermal Zones. BPMP sensors, without the thermal_zone prefix, work as described in the following paragraphs. All BPMP sensors have programmable temperature threshold (one trip), allocated for a thermal zone trip point.
The tegra_bpmp_thermal driver walks through the list of thermal trip points in a thermal zone based on the current temperature. It then comes up with a trip to program the BPMP sensor that is specified in the thermal zone. The driver then uses the following thermal message requests (MRQs) to communicate with the BPMP thermal framework.
• CMD_THERMAL_QUERY_ABI
• CMD_THERMAL_GET_TEMP
• CMD_THERMAL_SET_TRIP
• CMD_THERMAL_GET_NUM_ZONES
The driver receives a CMD_THERMAL_HOST_TRIP_REACHED MRQ message when a particular sensor crosses a trip. The message is then relayed back to the Linux thermal framework.
For more information on these thermal management features provided as part of BSP, see Thermal Management in BPMP.
Thermal Cooling
BSP provides thermal management using fan control and throttling of various clocks in the system.
Fan Management
BSP provides active cooling by fan management through the cooling device pwm-fan, which provides:
• Fan speed control by programming the PWM controller
• Ramp-up and ramp-down control to change the speed of the fan smoothly
• Fan control during various power states
The PWM-RPM mapping, and the various ramp rates, are stored as part of the device tree binary. The pwm-fan cooling device maps these PWM values to a cooling state. The fan cooling device can be attached to monitor the temperature of any of the BSP sensors. As the temperature increases, the governor picks a progressively deeper cooling state for the fan. This results in a higher RPM for the fan, which produces more cooling.
SoC thermal management uses the fan as the first line of defense to delay clock throttling until a much higher temperature is reached.
Software Clock Throttling
BSP provides thermal cooling by throttling various clocks in the system. When a thermal sensor’s temperature crosses a trip point, clock throttling employs the DVFS capabilities of the clocks to reduce their operating frequencies, and thereby the voltages of the rails that power the clocks. This reduction in frequency and voltage reduces power consumption, which helps to control the temperature.
Because cooling is achieved by reducing the clock frequency, there is a direct impact on performance and user experience. If a device feels warm and seems sluggish, it may be due to thermal throttling on the clocks. You can remedy this by tuning thermal zones that are mapped to the following balanced cooling devices:
• gpu_balanced
• cpu_balanced
• emergency_balanced
Each of these balanced cooling devices provides several cooling states that translate to a maximum allowable operating frequency for the CPU, GPU, and EMC clocks. These frequencies are optimized to provide the best possible performance at a given temperature. The frequency tables for these clocks are part of the device tree binary.
The governor uses the current temperature of the sensor as an input to the feedback control loop. Similarly, the governor uses the control loop’s output as the new cooling state for the operation of the cooling device. As the device heats up, the governor progressively picks a higher cooling setting, which then results in a higher frequency cap for all the clocks, and potentially greater cooling. BSP performs this thermal throttling of the clocks to maintain the junction temperature of the die within the recommended safe limits. For software throttling trip temperatures, see the table in Thermal Specifications.
Software Thermal Shutdown
The thermal zones also define a special type of trip point called a critical trip point that triggers a software shutdown. This special trip point allows the operating system to save its state and perform an orderly shutdown before a hardware reset due to high temperature rates. BSP defines one critical trip point per thermal zone. Users can set the lower limit for the orderly shutdown. A thermal shutdown occurs after all the other cooling strategies have failed. It is considered a rare event. For software throttling trip temperatures, see the table in Thermal Specifications
Hardware Thermal Shutdown
The on-board sensor is configured to trigger hardware shutdown when all other cooling strategies have failed, and in particular, after software shutdown has failed to occur when it should. For hardware shutdown limits, see the table in Thermal Specifications.
Thermal Management in BPMP
BSP thermal management features are part of the firmware running on BPMP for Jetson platforms running any host operating system (host OS) on the CPU.
Thermal Sensing
The BPMP firmware hosts the soctherm and aotag drivers for the on-die thermal sensors as follows:
Thermal Sensor | ABI Name | Sensed Location | |
|---|---|---|---|
AOTAG | AOTAG | THERMAL_ZONE_AO | Co-locate with TDIODE in pad-ring |
SOC_THERM | PLLX | THERMAL_ZONE_PLLX | Placed adjacent to PLLX |
AUX (x2) | THERMAL_ZONE_AUX | Centrally located in each Denver CPU | |
CPU (x4) | THERMAL_ZONE_CPU | Centrally located in each A57 CPU | |
GPU (x2) | THERMAL_ZONE_GPU | Within the GPU | |
SOC_THERM
SOC_THERM is the collection of on-chip Ring Oscillators whose frequency changes are based on the temperature. To convert a measured frequency to a temperature, the oscillating frequency of the sensor, at a fixed temperature, must be known in advance and stored in the on-chip fuses.
The soctherm driver uses these fuses during boot and calibrates the sensor. Once the calibration is complete, the temperature sensor reports the temperature, in degrees Celsius, with a 0.5C precision margin.
Sensors and Sensor Groups
The temperature sensors on the chip are logically grouped into sensor groups, based on their proximity to certain hardware blocks. The sensor groups are represented as a single sensor to the host OS and the BPMP firmware.
For example, Jetson TX2 has four temperature sensors in the A57 cluster. These are grouped as CPU sensors that are represented as THERMAL_ZONE_CPU to the operating system running on the CPUs. SOC_THERM reports the temperature of a given group by taking the maximum of all the sensors in the group.
Thermal Event Detection
Thermal sensors can report the temperature when the current temperature crosses a software programmed trip point. The sensors are capable of monitoring several of these software trip points to perform the following thermal actions:
• Report when the thermal trip point has been crossed
• Trigger a hardware thermal shutdown
• Trigger hardware throttling
Voltage Rail Dependencies
To provide accurate temperature sensing, the sensors require a minimum voltage. Additionally, the sensors cannot operate when the rail is power-gated.
When the system is in a low power-state, the firmware provides the following modes of operation:
• No temperature measurements during SC7: Because the rail powering the sensor is power-gated in the SC7 state, the oscillator is not running. Therefore, the frequency-to-temperature conversion may result in inaccurate values. To ensure no spurious temperature reports from the sensors, stop the sensor before entering SC7 state.
The firmware provides the AOTAG sensor for measuring the temperature SC7 state. When the SC7 state is exited, the sensors are restarted.
• Fallback to PLLX sensor on Jetson TX2: To ensure accurate temperature readings during minimum voltage, use the PLLX sensor’s oscillator. On platforms where the minimum voltage is not guaranteed, the firmware falls back on the PLLX sensor’s oscillator with a programmable offset. The result is that all the sensors invalidate their oscillators and use the PLLX sensor’s oscillator with the added offset. This fallback on the PLLX sensor’s oscillator allows for continuous temperature measurement, even at lower voltage levels.
As a side effect of the PLLX fallback, the programmable offset compensates for the fact that the PLLX sensor’s oscillator is farther away from the oscillator that it is replacing. The host OS continues to use all the thermal zones without side effects. The offset ensures that the CPU sensor reports more accurate temperatures than the PLLX sensor. The host OS must therefore continue to use the right sensors for measuring the CPU temperatures.
AOTAG
The Always-On Thermal Alert Generator (AOTAG) is a ring oscillator based temperature sensor. It is in the always-on power domain and can monitor temperatures even when the device is in the SC7 state. Apart from this distinction, the AOTAG sensor operates the same as any of the SOC_THERM sensors.
Thermal Event Detection
Just like the SOC_THERM sensor, the AOTAG sensor can generate interrupts. Additionally, it can monitor two software programmed levels that BSP uses as:
• Thermal zone trip points
• Hardware thermal shutdown
Fallback for the GPU Sensor
AOTAG sensor is ideal for monitoring GPU temperatures instead of the GPU sensor in SOC_THERM because:
• Proximity of AOTAG sensor to the GPU
• AOTAG capability to measure temperatures at all voltage levels into SC7
BPMP Thermal Framework
The BPMP firmware hosts a thermal framework to:
• Register thermal sensors as thermal zones as identified in Thermal Sensing.
• Allow BPMP modules to register trips on the thermal zones.
• Allow the host OS to register trips using thermal MRQ messages.
• Provide trip management and reporting.
The thermal framework maintains a list of trips per sensor that includes the current trip from the host OS, and various BPMP modules. As temperatures change, the framework examines the list of current trips and notifies the owners of the trips of the changes. The notification is sent using a callback for the BPMP owned trips and the thermal MRQ command CMD_THERMAL_HOST_TRIP_REACHED for trips that are owned by the host OS.
The primary thermal MRQ requests handled by the framework are:
• CMD_THERMAL_QUERY_ABI
• CMD_THERMAL_GET_TEMP
• CMD_THERMAL_SET_TRIP
• CMD_THERMAL_GET_NUM_ZONES
Since there can be several trip points on a given sensor, the thermal framework must ensure that a notification is generated whenever a given trip is crossed. For example, if THERMAL_ZONE_CPU has trips at 55°, 60°, 65°, and 70 °C, the thermal framework sends a single notification when the temperature crosses 55°, 60°, 65°, and 70 °C.
Additionally, the framework implements hysteresis to prevent sending too many notifications. So, for the above example, the framework:
• Sends one notification when the temperature reaches 55C
• Waits until the temperature drops below 54C
• Sends another notification when the temperature rises back to 55C
To perform these notifications, the thermal framework sets low trips on the sensors to receive events that the temperature has dropped below the limit.
Hardware Throttling
Each element in a power delivery system includes limitations such as:
• The amount of current a battery can supply without shutting down
• The amount of current a regulator can provide before it fails to maintain its output voltage
• The amount of ripple current that an inductor in a switching regulator can tolerate without overheating
These limitations can result in fast transient electrical and thermal events such as:
• Over-current at the battery
• Voltage drop at the PMIC
• Temperature spikes
The firmware refers to these events as OC alarms and triggers hardware throttling of the clocks to handle them.
Impact
Like software throttling, hardware throttling may reduce performance. Because the triggering events are rare and transient in nature, though, the user experience is minimally impacted.
The host OS is not notified of these events, but can detect the resulting drop in clock rates by using a performance measuring tool that samples the CPU cycle counters. While thermal management in the host OS seeks to control temperature on an ongoing basis, hardware throttling clamps down the clocks to handle events.
Throttle Points and Vector Configuration
The BPMP device tree binary holds the various throttle points and the throttle settings that govern when and how throttling is performed. The soctherm driver in the firmware programs the hardware and handles any interrupts resulting from these events. You can change the throttle points by changing the BPMP device tree.
This table shows the hardware throttling levels.
Hardware Throttling | Clock Throttled Percentage |
|---|---|
Heavy | 87.5 |
Medium | 75 |
Light | 50 |
Throttle vectors are optimized for limiting peak current consumption while maximizing performance. To manage peak current consumption, the firmware supports capping the CPU and GPU clocks at three levels (light, medium, and heavy), as described in the device tree bindings. Clock capping prevents the CPU and GPU from drawing more current than their voltage regulators can supply. For hardware throttling trip temperature, see the table in Thermal Specifications.
Design Considerations
Designing fail safe measures into Power Management Integrated Circuits (PMICs), or using the battery controller to shut down the device when the events described here occur, results in a bad user experience. Similarly, designing power delivery hardware for worst-case loads results in large and costly components.
Consequently, NVIDIA SoCs are designed for use with power delivery systems that are adequate for common loads. Additionally, NVIDIA SoCs actively manage their components to avoid exceeding their design limits. When events are transient, the advantage of this approach to power management becomes more compelling.
Hardware Thermal Shutdown
The final failsafe the firmware thermal management is a hardware thermal reset or thermtrip. If software and hardware throttling are unable to control heat generation in the system, and the software becomes unresponsive, the SoC asserts the reset pin on the PMIC as the hardware shutdown mechanism.
For hardware shutdown limits, see the table in Thermal Specifications.
Thermal Specifications
This table describes the supported power states.
Thermal Zone | Thermal Sensor | Cooling Action | Jetson TX2/TX2 4GB Trip Point | Jetson TX2i Trip Point | Jetson TX2 NX Trip Point |
BCPU-therm | THERMAL_ZONE_CPU | SW throttling | 95.5 °C | 95.5 °C | 95.5 °C |
HW throttling | 99.5 °C | 99.5 °C | 99.5 °C | ||
SW shutdown | 100.5 °C | 100.5 °C | 100.5 °C | ||
MCPU-therm | THERMAL_ZONE_AUX | SW throttling | 95.5 °C | 95.5 °C | 95.5 °C |
HW throttling | 99.5 °C | 99.5 °C | 99.5 °C | ||
SW shutdown | 100.5 °C | 100.5 °C | 100.5 °C | ||
PLL-therm | THERMAL_ZONE_PLLX | HW shutdown | 101.0 °C | 101.0 °C | 101.0 °C |
GPU-therm | THERMAL_ZONE_AO | SW throttling | 95.5 °C | 95.5 °C | 95.5 °C |
SW shutdown | 100.5 °C | 100.5 °C | 100.5 °C | ||
HW shutdown | 101.0 °C | 101.0 °C | 101.0 °C | ||
Tboard_tegra | tmp451 local sensor | SW shutdown | 106.5 °C | 109.5 °C | — |
HW shutdown | 107.0 °C | 110.0 °C | — | ||
Tdiode_tegra | tmp451 remote sensor | SW shutdown | 106.5 °C | 109.5 °C | — |
HW shutdown | 107.0 °C | 110.0 °C | — | ||
thermal-fan-est | Weighted average of CPU, AUX and GPU | Fan ON | 51.0 °C | 51.0 °C | 46.0 °C |
* The tmp451 on-board thermal sensor does not present on Jetson TX2 NX module. | |||||
Software-Based Power Consumption Modeling
Jetson TX2 series modules integrate a three-channel INA3221 power monitor whose information can be read using sysfs nodes. The following table shows the naming convention for sysfs nodes.
Command | Description |
rail_name_<N> | Exports the rail name. |
in_current<N>_input | Exports rail current in milliamperes. |
in_voltage<N>_input | Exports rail voltage in millivolts. |
In_power<N>_input | Exports rail power in milliwatts. |
crit_current_limit_<N> | Exports rail critical current limit in milliamperes. |
Where <N> is a channel number 0-2. | |
Note: | The INA driver may also present other nodes. Do not modify any INA sysfs node value. Modifying these values can result in damage to the device. |
Jetson TX2, TX2i, and TX2 4GB
The Jetson TX2, TX2i, and TX2 4GB modules have three-channel INA3221 power monitors at I2C address 0x40 and 0x421. The sysfs nodes to read for rail names, voltage, current, and power are at:
/sys/bus/i2c/drivers/ina3221x/0-0040/iio:device0
/sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1
The rail names for I2C address 0x40 are:
Rail Name | Description |
Channel 0: VDD_SYS_GPU | GPU power rail. |
Channel 1: VDD_SYS_SOC | SOC power rail. |
Channel 2: VDD_4V0_WIFI | WIFI power rail. |
Note: | On Jetson TX2i, channel 2 is NOT connected to any rail. |
The rail names for I2C address 0x41 are:
Rail Name | Description |
Channel 0: VDD_IN | Main module power input. |
Channel 1: VDD_SYS_CPU | CPU power rail. |
Channel 2: VDD_SYS_DDR | DDR power rail. |
The Jetson TX2 Developer Kit carrier board has 3-channel INA3221 power monitors at I2C addresses 0x42 and 0x43. The sysfs nodes to read rail name, voltage, current, power, and critical current limit are at:
/sys/bus/i2c/drivers/ina3221x/0-0042/iio:device2
/sys/bus/i2c/drivers/ina3221x/0-0043/iio:device3
The rail names for I2C address 0x42 are:
Rail Name | Description |
Channel 0: VDD_MUX | Carrier board power input. |
Channel 1: VDD_5V_IO_SYS | Carrier board 5 V supply. |
Channel 2: VDD_3V3_SYS | Carrier board 3.3 V supply. |
The rail names for I2C address 0x43 are:
Rail Name | Description |
Channel 0: VDD_3V3_IO_SLP | Carrier board 3.3 V sleep supply. |
Channel 1: VDD_1V8_IO (Name on schematic is VDD_1V8) | Carrier board 1.8 V supply. |
Channel 2: VDD_3V3_SYS_M2 | 3.3 V supply for M.2 Key E connector. |
Examples
• To read INA3221 at 0x41, the channel-0 rail name (i.e., VDD_IN), enter the command:
cat /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/rail_name_0
• To read VDD_IN voltage, current, and power, enter the commands:
$ cat /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/in_current0_input
$ cat /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/in_voltage0_input
$ cat /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/in_power0_input
• To read VDD_IN critical current limit, enter the command:
$ cat /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/crit_current_limit_0
• To set VDD_IN critical current limit, enter the command:
$ echo <current_in_ma> > /sys/bus/i2c/drivers/ina3221x/0-0041/iio:device1/crit_current_limit_0
Note: | In terms of accuracy, assume a 5% guard band for INA measurements greater than 200 mW. Below that, accuracy can deviate by as much as 15%. |
Jetson TX2 NX
The Jetson TX2 NX module has a three-channel INA3221 power monitors at I2C address 0x40. The sysfs nodes to read for rail names, voltage, current, and 0x41power are at:
/sys/bus/i2c/drivers/ina3221x/2-0040/iio:device0
The rail names for I2C address 0x40 are:
Rail Name | Description |
Channel 0: VDD_IN | System 5V power rail. |
Channel 1: VDD_CPU_GPU | CPU+GPU power rail. |
Channel 2: VDD_SOC | SOC power rail. |
Note: | The VDD_IN rail overcurrent thresholds for average and instantaneous current are 3 A and 3.6 A, respectively. The INA3221 triggers CPU and GPU hardware clock throttling to prevent shutdown and physical damage when module current consumption exceeds these limits. The overcurrent events are notified to userspace via the nvpmodel GUI applet. For more details, see the section Voltage And Current Monitor in the topic Hardware Setup document. |
Related Tools and Techniques
This section describes the tools and techniques for managing power.
CPU Hot Plug
You may use the following procedures to manage CPU hot plugging.
To turn secondary CPUs on or off manually
• Enter this command to turn the secondary CPU on:
$ echo 1 > /sys/devices/system/cpu/cpuX/online
• Enter this command to turn the secondary CPU off:
$ echo 0 > /sys/devices/system/cpu/cpuX/online
To check a CPU’s state
• Enter the command:
$ cat /sys/devices/system/cpu/cpu<x>/online
Where <x> is the CPU core number.
To check online CPU cores
• Enter the command:
$ cat /sys/devices/system/cpu/online
CPU Frequency Scaling
The default CPU frequency governor is schedutil.
To list available CPU frequency governors
• Enter the command:
$ cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors
To select a CPU frequency governor
• Enter the command:
$ echo <name> > /sys/devices/system/cpu/cpu<x>/cpufreq/scaling_governor
Where:
• <name> is the name of the governor to be selected
• <x> is the CPU core number
GPU 3D Frequency Scaling
GPU 3D frequency scaling is enabled by default.
To disable 3D frequency scaling
• Enter the command:
$ echo 0 > /sys/devices/17000000.gp10b/enable_3d_scaling
To enable 3D frequency scaling
• Enter the command:
$ echo 1 > /sys/devices/17000000.gp10b/enable_3d_scaling
Getting and Setting Frequencies
Use the following procedures to set frequencies and report current frequency settings.
Note: | In all of these procedures, <x> is a CPU core number. For example, to apply a command to CPU core 1, replace cpu<x> with cpu1. |
To get system clock information
• Enter the command:
$ cat /sys/kernel/debug/clk/clk_tree
To print the CPU lower boundary, upper boundary, and current frequency
• Enter the commands:
$ cat /sys/devices/system/cpu/cpu<x>/cpufreq/cpuinfo_min_freq
$ cat /sys/devices/system/cpu/cpu<x>/cpufreq/cpuinfo_max_freq
$ cat /sys/devices/system/cpu/cpu<x>/cpufreq/cpuinfo_cur_freq
To change the CPU upper boundary
• Enter the command:
$ echo <cpu_freq> > /sys/devices/system/cpu/cpu<x>/cpufreq/scaling_max_freq
Where:
• <cpu_freq> is the frequency value available at:
/sys/devices/system/cpu/cpu<x>/cpufreq/scaling_available_frequencies
• <x> is the CPU core number.
To change the CPU lower boundary
• Enter the command:
$ echo <cpu_freq> > /sys/devices/system/cpu/cpu<x>/cpufreq/scaling_min_freq
To set the static CPU frequency
• Enter the commands:
$ echo <cpu_freq> > /sys/devices/system/cpu/cpu<x>/cpufreq/scaling_min_freq
$ echo <cpu_freq> > /sys/devices/system/cpu/cpu<x>/cpufreq/scaling_max_freq
To print the GPU lower boundary, upper boundary, and current frequency
• Enter the commands:
$ cat /sys/devices/gpu.0/devfreq/17000000.gp10b/min_freq
$ cat /sys/devices/gpu.0/devfreq/17000000.gp10b/max_freq
$ cat /sys/devices/gpu.0/devfreq/17000000.gp10b/cur_freq
To change the GPU upper boundary
• Enter the command:
$ echo <gpu_freq> > /sys/devices/17000000.gp10b/devfreq/17000000.gp10b/max_freq
To change the GPU lower boundary
• Enter the command:
$ echo <gpu_freq> > /sys/devices/17000000.gp10b/devfreq/17000000.gp10b/min_freq
To set the static GPU frequency
• Enter the commands:
$ echo <gpu_freq> > /sys/devices/17000000.gp10b/devfreq/17000000.gp10b/min_freq
$ echo <gpu_freq> > /sys/devices/17000000.gp10b/devfreq/17000000.gp10b/max_freq
Where <gpu_freq> is the value available in:
/sys/devices/17000000.gp10b/devfreq/17000000.gp10b/available_frequencies
To print the EMC lower boundary, upper boundary, and current frequency
• Enter the commands:
$ cat /sys/kernel/debug/bpmp/debug/clk/emc/min_rate
$ cat /sys/kernel/debug/bpmp/debug/clk/emc/max_rate
$ cat /sys/kernel/debug/bpmp/debug/clk/emc/rate
To change the EMC upper boundary
• Enter the command:
$ echo <emc_freq> > /sys/kernel/debug/bpmp/debug/clk/emc/max_rate
To change the EMC lower boundary
• Enter the command:
$ echo <emc_freq> > /sys/kernel/debug/bpmp/debug/clk/emc/min_rate
To set static EMC frequency
• Enter the commands:
$ echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
$ echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/state
$ echo <emc_freq> > /sys/kernel/debug/bpmp/debug/clk/emc/rate
Where <emc_freq> is a frequency value between EMC minimum and maximum frequencies.
To set static VIC frequency
• See the section To set the static VIC frequency in the topic Clock Frequency and Power Management.
Maximizing Jetson TX2 Performance
BSP provides the jetson_clocks.sh script to maximize Jetson TX2 performance by setting the static maximum frequencies of the CPU, GPU and EMC clocks. You can also use the script to show current clock settings, store current clock settings into a file, and restore clock settings from a file.
The script is available at:
usr/bin/jetson_clocks
To run the script, enter:
jetson_clocks [options]
Option | Description |
--show | Displays the current settings. |
--store [<file>] | Stores the current settings to a file. The default file is l4t_dfs.conf. |
--restore [<file>] | Restores the saved settings from a file. The default file is l4t_dfs.conf. |
--fan | Sets maximum PWM fan speed. |
To show the current settings
• Execute the command:
$ sudo /usr/bin/jetson_clocks --show
To store the current settings
• Execute the command:
$ sudo /usr/bin/jetson_clocks --store
To maximize platform performance
• Execute the command:
$ sudo /usr/bin/jetson_clocks
To maximize platform performance and fan speed
• Enter the command:
$ sudo /usr/bin/jetson_clocks --fan
Note: | Starting with Release 32.4, jetson_clocks no longer sets maximum fan speed by default. If you prefer the old behavior, use the --fan option. |
To restore the previous settings
• Execute the command:
$ sudo /usr/bin/jetson_clocks --restore
nvpmodel GUI
The nvpmodel GUI is a GUI front end for the nvpmodel command line tool. It is an easy way to access power-related functionality and information.
To use the nvpmodel GUI
The nvpmodel GUI is represented by an NVIDIA icon on the right side the Ubuntu desktop’s top bar:
The current power mode is displayed next to the NVIDIA icon. In the illustration above, the current mode is MODE1SW.
• To switch the current power mode, click the NVIDIA icon to open a dropdown menu from the icon. Click “Power mode” to open a submenu of power modes.
Click the power mode you want to set.
• To run tegrastats, click the NVIDIA icon to open the dropdown menu.
Click “Run tegrastats” to spawn a terminal window and run tegrastats.
The tegrastats display provides power-related information such as CPU, GPU, and EMC frequencies and the temperatures of thermal zones registered to the system.
• If system input voltage drops below a safe level or input current increases beyond the critical limit, the nvpmodel GUI displays a desktop notification to warn you that the system is being throttled back to avoid a shutdown or physical damage. When the system is thermally throttled, the GUI displays a similar notification to show that the device is operating at reduced speed to limit heat generation.
These are examples of notifications:
Fan Speed Control
To set fan speed manually
• Enter the command:
$ echo <PWM_duty_cycle> > /sys/devices/pwm-fan/target_pwm
Where <PWM_duty_cycle> is a value in the range [0,255].
To get the fan speed measured by the tachometer
• Enter the command:
$ cat /sys/devices/generic_pwm_tachometer/hwmon/hwmon1/rpm
Note: | The look and feel of the nvpmodel GUI are different in different desktop environments. A notable example is the LXDE desktop, where “Power mode” menu item is not shown in the NVIDIA icon’s dropdown menu. |