v4l2_nv_extensions.h

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/*
 * Copyright (c) 2016-2023, NVIDIA CORPORATION.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
 *     notice, this list of conditions and the following disclaimer in
 *     the documentation and/or other materials provided with the
 *     distribution.
 *  3. The names of its contributors may not be used to endorse or promote
 *     products derived from this software without specific prior written
 *     permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
 *  TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/* This file contains amendments to the V4L2 headers made after the
 * supported kernel version and NVIDIA extensions.
 */
 
#ifndef __V4L2_NV_EXTENSIONS_H__
#define __V4L2_NV_EXTENSIONS_H__
 
#define V4L2_PIX_FMT_DIVX4     v4l2_fourcc('D', 'V', 'X', '4')
 
#define V4L2_PIX_FMT_DIVX5     v4l2_fourcc('D', 'V', 'X', '5')
 
#define V4L2_PIX_FMT_H265     v4l2_fourcc('H', '2', '6', '5')
 
#define V4L2_PIX_FMT_VP9      v4l2_fourcc('V', 'P', '9', '0')
 
#define V4L2_PIX_FMT_AV1      v4l2_fourcc('A', 'V', '1', '0')
 
#define V4L2_PIX_FMT_P010    v4l2_fourcc('P', '0', '1', '0') /* Y/CbCr 4:2:0, 10 bits per channel */
 
#define V4L2_PIX_FMT_P010M   v4l2_fourcc('P', 'M', '1', '0') /* Y/CbCr 4:2:0, 10 bits per channel */
 
#define V4L2_PIX_FMT_P012    v4l2_fourcc('P', '0', '1', '2') /* Y/CbCr 4:2:0, 12 bits per channel */
 
#define V4L2_PIX_FMT_P012M   v4l2_fourcc('P', 'M', '1', '2') /* Y/CbCr 4:2:0, 12 bits per channel */
 
#define V4L2_PIX_FMT_NV24M   v4l2_fourcc('N', 'M', '2', '4') /* Y/CbCr 4:4:4, 8 bits per channel */
 
#define V4L2_PIX_FMT_NV24_10LE   v4l2_fourcc('N', 'V', '1', '0') /* Y/CbCr 4:4:4, 10 bits per channel */
 
#define V4L2_PIX_FMT_YUV444_10LE   v4l2_fourcc('P', '4', '1', '0') /* Y/Cb/Cr 4:4:4, 10 bits per channel */
 
#define V4L2_PIX_FMT_YUV444_12LE   v4l2_fourcc('P', '4', '1', '2') /* Y/Cb/Cr 4:4:4, 12 bits per channel */
 
/* >> The declarations from here to the next endcond statement are not
 * >> currently implemented. DO NOT USE. */
 
#define V4L2_PIX_FMT_YUV422RM v4l2_fourcc('4', '2', 'R', 'M')
 
 
#define V4L2_PIX_FMT_H264_SLICE v4l2_fourcc('S', '2', '6', '4') 
#define V4L2_PIX_FMT_VP8_FRAME v4l2_fourcc('V', 'P', '8', 'F') 
#define V4L2_CTRL_FLAG_CAN_STORE    0x0200
 
#define V4L2_EVENT_RESOLUTION_CHANGE        5
 
/* >> The declarations from here to the next endcond statement are not
 * >> currently implemented. DO NOT USE. */
 
/*---------------Below are changes from the v4l2-controls.h----------------------*/
 
#define V4L2_CID_MPEG_VIDEO_H264_SPS        (V4L2_CID_MPEG_BASE+383)
#define V4L2_CID_MPEG_VIDEO_H264_PPS        (V4L2_CID_MPEG_BASE+384)
#define V4L2_CID_MPEG_VIDEO_H264_SCALING_MATRIX (V4L2_CID_MPEG_BASE+385)
#define V4L2_CID_MPEG_VIDEO_H264_SLICE_PARAM    (V4L2_CID_MPEG_BASE+386)
#define V4L2_CID_MPEG_VIDEO_H264_DECODE_PARAM   (V4L2_CID_MPEG_BASE+387)
 
#define V4L2_CID_MPEG_VIDEO_VP8_FRAME_HDR       (V4L2_CID_MPEG_BASE+512)
 
#define V4L2_CID_MPEG_VIDEO_H265_PROFILE        (V4L2_CID_MPEG_BASE+513)
 
#define V4L2_CID_MPEG_VIDEO_IDR_INTERVAL        (V4L2_CID_MPEG_BASE+514)
 
/* >> The declarations from here to the next endcond statement are not
 * >> currently implemented. DO NOT USE. */
 
/* Complex controls */
 
#define V4L2_H264_SPS_CONSTRAINT_SET0_FLAG          0x01
#define V4L2_H264_SPS_CONSTRAINT_SET1_FLAG          0x02
#define V4L2_H264_SPS_CONSTRAINT_SET2_FLAG          0x04
#define V4L2_H264_SPS_CONSTRAINT_SET3_FLAG          0x08
#define V4L2_H264_SPS_CONSTRAINT_SET4_FLAG          0x10
#define V4L2_H264_SPS_CONSTRAINT_SET5_FLAG          0x20
 
#define V4L2_H264_SPS_FLAG_SEPARATE_COLOUR_PLANE        0x01
#define V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS  0x02
#define V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO      0x04
#define V4L2_H264_SPS_FLAG_GAPS_IN_FRAME_NUM_VALUE_ALLOWED  0x08
#define V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY           0x10
#define V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD      0x20
#define V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE         0x40
 
#define V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE              0x0001
#define V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT  0x0002
#define V4L2_H264_PPS_FLAG_WEIGHTED_PRED                0x0004
#define V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT        0x0008
#define V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED           0x0010
#define V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT            0x0020
#define V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE               0x0040
#define V4L2_H264_PPS_FLAG_PIC_SCALING_MATRIX_PRESENT           0x0080
 
struct v4l2_h264_pred_weight_table {
    __u8 luma_log2_weight_denom;
    __u8 chroma_log2_weight_denom;
    struct v4l2_h264_weight_factors weight_factors[2];
};
 
#define V4L2_SLICE_FLAG_FIELD_PIC       0x01
#define V4L2_SLICE_FLAG_BOTTOM_FIELD        0x02
#define V4L2_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED  0x04
#define V4L2_SLICE_FLAG_SP_FOR_SWITCH       0x08
struct v4l2_ctrl_h264_slice_param {
    __u32 size;
    __u32 header_bit_size;
 
    __u16 first_mb_in_slice;
    __u8 slice_type;
    __u8 pic_parameter_set_id;
    __u8 colour_plane_id;
    __u16 frame_num;
    __u16 idr_pic_id;
    __u16 pic_order_cnt_lsb;
    __s32 delta_pic_order_cnt_bottom;
    __s32 delta_pic_order_cnt0;
    __s32 delta_pic_order_cnt1;
    __u8 redundant_pic_cnt;
 
    struct v4l2_h264_pred_weight_table pred_weight_table;
    /* Size in bits of dec_ref_pic_marking() syntax element. */
    __u32 dec_ref_pic_marking_bit_size;
    /* Size in bits of pic order count syntax. */
    __u32 pic_order_cnt_bit_size;
 
    __u8 cabac_init_idc;
    __s8 slice_qp_delta;
    __s8 slice_qs_delta;
    __u8 disable_deblocking_filter_idc;
    __s8 slice_alpha_c0_offset_div2;
    __s8 slice_beta_offset_div2;
    __u32 slice_group_change_cycle;
 
    __u8 num_ref_idx_l0_active_minus1;
    __u8 num_ref_idx_l1_active_minus1;
    /*  Entries on each list are indices
     *  into v4l2_ctrl_h264_decode_param.dpb[]. */
    __u8 ref_pic_list0[32];
    __u8 ref_pic_list1[32];
 
    __u8 flags;
};
 
struct v4l2_ctrl_h264_decode_param {
    __u32 num_slices;
    __u8 idr_pic_flag;
    __u8 nal_ref_idc;
    __s32 top_field_order_cnt;
    __s32 bottom_field_order_cnt;
    __u8 ref_pic_list_p0[32];
    __u8 ref_pic_list_b0[32];
    __u8 ref_pic_list_b1[32];
    struct v4l2_h264_dpb_entry dpb[16];
};
 
#define V4L2_VP8_SEGMNT_HDR_FLAG_ENABLED              0x01
#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_MAP           0x02
#define V4L2_VP8_SEGMNT_HDR_FLAG_UPDATE_FEATURE_DATA  0x04
struct v4l2_vp8_sgmnt_hdr {
    __u8 segment_feature_mode;
 
    __s8 quant_update[4];
    __s8 lf_update[4];
    __u8 segment_probs[3];
 
    __u8 flags;
};
 
#define V4L2_VP8_LF_HDR_ADJ_ENABLE  0x01
#define V4L2_VP8_LF_HDR_DELTA_UPDATE    0x02
struct v4l2_vp8_loopfilter_hdr {
    __u8 type;
    __u8 level;
    __u8 sharpness_level;
    __s8 ref_frm_delta_magnitude[4];
    __s8 mb_mode_delta_magnitude[4];
 
    __u8 flags;
};
 
struct v4l2_vp8_quantization_hdr {
    __u8 y_ac_qi;
    __s8 y_dc_delta;
    __s8 y2_dc_delta;
    __s8 y2_ac_delta;
    __s8 uv_dc_delta;
    __s8 uv_ac_delta;
    __u16 dequant_factors[4][3][2];
};
 
struct v4l2_vp8_entropy_hdr {
    __u8 coeff_probs[4][8][3][11];
    __u8 y_mode_probs[4];
    __u8 uv_mode_probs[3];
    __u8 mv_probs[2][19];
};
 
#define V4L2_VP8_FRAME_HDR_FLAG_EXPERIMENTAL        0x01
#define V4L2_VP8_FRAME_HDR_FLAG_SHOW_FRAME      0x02
#define V4L2_VP8_FRAME_HDR_FLAG_MB_NO_SKIP_COEFF    0x04
struct v4l2_ctrl_vp8_frame_hdr {
    __u8 key_frame;
    __u8 version;
 
    __u16 width;
    __u8 horizontal_scale;
    __u16 height;
    __u8 vertical_scale;
 
    struct v4l2_vp8_sgmnt_hdr sgmnt_hdr;
    struct v4l2_vp8_loopfilter_hdr lf_hdr;
    struct v4l2_vp8_quantization_hdr quant_hdr;
    struct v4l2_vp8_entropy_hdr entropy_hdr;
 
    __u8 sign_bias_golden;
    __u8 sign_bias_alternate;
 
    __u8 prob_skip_false;
    __u8 prob_intra;
    __u8 prob_last;
    __u8 prob_gf;
 
    __u32 first_part_size;
    __u32 first_part_offset;
    __u32 macroblock_bit_offset;
 
    __u8 num_dct_parts;
    __u32 dct_part_sizes[8];
 
    __u8 bool_dec_range;
    __u8 bool_dec_value;
    __u8 bool_dec_count;
 
    __u32 last_frame;
   __u32 golden_frame;
    __u32 alt_frame;
 
    __u8 flags;
};
 
/*---------------Add below NVIDIA specific extensions ----------------------*/
 
#define V4L2_CID_MPEG_VIDEO_DISABLE_COMPLETE_FRAME_INPUT (V4L2_CID_MPEG_BASE+515)
 
#define V4L2_CID_MPEG_VIDEO_DISABLE_DPB (V4L2_CID_MPEG_BASE+516)
 
#define V4L2_CID_MPEG_VIDEO_ERROR_REPORTING (V4L2_CID_MPEG_BASE+517)
 
#define V4L2_CID_MPEG_VIDEO_SKIP_FRAMES (V4L2_CID_MPEG_BASE+518)
 
#define V4L2_CID_MPEG_VIDEODEC_METADATA (V4L2_CID_MPEG_BASE+519)
 
#define V4L2_CID_MPEG_VIDEODEC_INPUT_METADATA (V4L2_CID_MPEG_BASE+520)
 
#define V4L2_CID_VIDEODEC_DISPLAYDATA_PRESENT (V4L2_CID_MPEG_BASE+521)
 
#define V4L2_CID_VIDEODEC_HDR_MASTERING_DISPLAY_DATA (V4L2_CID_MPEG_BASE+522)
 
#define V4L2_CID_MPEG_VIDEODEC_SAR_WIDTH (V4L2_CID_MPEG_BASE+580)
 
#define V4L2_CID_MPEG_VIDEODEC_SAR_HEIGHT (V4L2_CID_MPEG_BASE+581)
 
 #define V4L2_CID_MPEG_VIDEOENC_DS_SEI_DATA (V4L2_CID_MPEG_BASE+571)
 
#define V4L2_CID_MPEG_VIDEODEC_GDR_STREAM (V4L2_CID_MPEG_BASE+591)
 
#define V4L2_CID_VIDEO_CONVERT_OUTPUT_PLANE_LAYOUT   (V4L2_CID_MPEG_BASE+523)
 
#define V4L2_CID_VIDEO_CONVERT_CAPTURE_PLANE_LAYOUT  (V4L2_CID_MPEG_BASE+524)
 
#define V4L2_CID_VIDEO_CONVERT_FLIP_METHOD           (V4L2_CID_MPEG_BASE+525)
 
#define V4L2_CID_VIDEO_CONVERT_INTERPOLATION_METHOD  (V4L2_CID_MPEG_BASE+526)
 
#define V4L2_CID_VIDEO_CONVERT_TNR_ALGORITHM         (V4L2_CID_MPEG_BASE+527)
 
#define V4L2_CID_MPEG_VIDEOENC_TEMPORAL_TRADEOFF_LEVEL (V4L2_CID_MPEG_BASE+528)
 
#define V4L2_CID_MPEG_VIDEOENC_SLICE_LENGTH_PARAM (V4L2_CID_MPEG_BASE+529)
 
#define V4L2_CID_MPEG_VIDEOENC_ROI_PARAMS (V4L2_CID_MPEG_BASE+530)
 
#define V4L2_CID_MPEG_VIDEOENC_VIRTUALBUFFER_SIZE (V4L2_CID_MPEG_BASE+531)
 
#define V4L2_CID_MPEG_VIDEOENC_NUM_REFERENCE_FRAMES (V4L2_CID_MPEG_BASE+532)
 
#define V4L2_CID_MPEG_VIDEOENC_SLICE_INTRAREFRESH_PARAM (V4L2_CID_MPEG_BASE+533)
 
#define V4L2_CID_MPEG_VIDEOENC_NUM_BFRAMES (V4L2_CID_MPEG_BASE+534)
 
#define V4L2_CID_MPEG_VIDEOENC_INSERT_SPS_PPS_AT_IDR (V4L2_CID_MPEG_BASE+535)
 
#define V4L2_CID_MPEG_VIDEOENC_METADATA               (V4L2_CID_MPEG_BASE+536)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_METADATA_MV     (V4L2_CID_MPEG_BASE+537)
 
#define V4L2_CID_MPEG_VIDEOENC_METADATA_MV            (V4L2_CID_MPEG_BASE+538)
 
#define V4L2_CID_MPEG_VIDEOENC_QP_RANGE               (V4L2_CID_MPEG_BASE+539)
 
#define V4L2_CID_MPEG_VIDEOENC_HW_PRESET_TYPE_PARAM   (V4L2_CID_MPEG_BASE+540)
 
#define V4L2_CID_MPEG_VIDEOENC_INPUT_METADATA         (V4L2_CID_MPEG_BASE+541)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_EXTERNAL_RPS_CONTROL (V4L2_CID_MPEG_BASE+542)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_EXTERNAL_RATE_CONTROL (V4L2_CID_MPEG_BASE+543)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_ROI_PARAM (V4L2_CID_MPEG_BASE+544)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_RECONCRC_PARAM  (V4L2_CID_MPEG_BASE+545)
 
#define V4L2_CID_MPEG_VIDEOENC_INSERT_VUI (V4L2_CID_MPEG_BASE+546)
 
#define V4L2_CID_MPEG_VIDEOENC_INSERT_AUD (V4L2_CID_MPEG_BASE+547)
 
#define V4L2_CID_MPEG_VIDEOENC_EXTEDED_COLORFORMAT (V4L2_CID_MPEG_BASE+548)
 
#define V4L2_CID_MPEG_VIDEO_DECODE_INSTANCE (V4L2_CID_MPEG_BASE+549)
 
#define V4L2_CID_MPEG_VIDEO_DEVICE_POLL (V4L2_CID_MPEG_BASE+550)
 
#define V4L2_CID_MPEG_SET_POLL_INTERRUPT (V4L2_CID_MPEG_BASE+551)
 
#define V4L2_CID_MPEG_VIDEOENC_TWO_PASS_CBR (V4L2_CID_MPEG_BASE+552)
 
#define V4L2_CID_VIDEO_CONVERT_YUV_RESCALE_METHOD (V4L2_CID_MPEG_BASE+553)
 
#define V4L2_CID_MPEG_VIDEO_MAX_PERFORMANCE (V4L2_CID_MPEG_BASE+554)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_ALLIFRAME_ENCODE (V4L2_CID_MPEG_BASE+555)
 
#define V4L2_CID_MPEG_VIDEO_BUF_API_TYPE (V4L2_CID_MPEG_BASE+556)
 
#define V4L2_CID_MPEG_VIDEO_CUDA_MEM_TYPE (V4L2_CID_MPEG_BASE+557)
 
#define V4L2_CID_MPEG_VIDEO_CUDA_GPU_ID (V4L2_CID_MPEG_BASE+558)
 
#define V4L2_CID_MPEG_VIDEODEC_DROP_FRAME_INTERVAL (V4L2_CID_MPEG_BASE+559)
 
 #define V4L2_CID_MPEG_VIDEOENC_VPX_HEADERS_WITH_FRAME (V4L2_CID_MPEG_BASE+560)
 
#define V4L2_CID_MPEG_VIDEOENC_H265_LEVEL (V4L2_CID_MPEG_BASE+561)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_SLICE_LEVEL_ENCODE (V4L2_CID_MPEG_BASE+562)
 
#define V4L2_CID_MPEG_VIDEOENC_POC_TYPE (V4L2_CID_MPEG_BASE+563)
 
#define V4L2_CID_MPEG_VIDEOENC_H265_VUI_EXT_SAR_WIDTH (V4L2_CID_MPEG_BASE+564)
 
#define V4L2_CID_MPEG_VIDEOENC_H265_VUI_EXT_SAR_HEIGHT (V4L2_CID_MPEG_BASE+565)
 
#define V4L2_CID_MPEG_VIDEOENC_FORCE_INTRA_FRAME (V4L2_CID_MPEG_BASE+566)
 
#define V4L2_CID_MPEG_VIDEOENC_FORCE_IDR_FRAME (V4L2_CID_MPEG_BASE+567)
 
#define V4L2_CID_MPEG_VIDEO_CUDA_LOW_LATENCY (V4L2_CID_MPEG_BASE+568)
 
#define V4L2_CID_MPEG_VIDEOENC_AV1_HEADERS_WITH_FRAME (V4L2_CID_MPEG_BASE+569)
 
#define V4L2_CID_MPEG_VIDEOENC_AV1_TILE_CONFIGURATION (V4L2_CID_MPEG_BASE+570)
 
#define V4L2_CID_MPEG_VIDEOENC_AV1_ENABLE_SSIMRDO (V4L2_CID_MPEG_BASE+571)
 
#define V4L2_CID_MPEG_VIDEOENC_AV1_DISABLE_CDF_UPDATE (V4L2_CID_MPEG_BASE+572)
 
#define V4L2_CID_MPEG_VIDEOENC_FRAMES_TO_ENCODE (V4L2_CID_MPEG_BASE+573)
 
#define V4L2_CID_MPEG_VIDEOENC_INIT_FRAME_QP (V4L2_CID_MPEG_BASE+574)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_LOSSLESS (V4L2_CID_MPEG_BASE+575)
 
#define V4L2_CID_MPEG_VIDEOENC_H265_CHROMA_FACTOR_IDC (V4L2_CID_MPEG_BASE+576)
 
#define V4L2_CID_MPEG_VIDEOENC_PPE_INIT_PARAMS (V4L2_CID_MPEG_BASE+577)
 
#define V4L2_CID_MPEG_VIDEOENC_CUDA_PRESET_ID (V4L2_CID_MPEG_BASE+578)
 
#define V4L2_CID_MPEG_VIDEOENC_CUDA_TUNING_INFO (V4L2_CID_MPEG_BASE+579)
 
#define V4L2_CID_MPEG_VIDEOENC_CUDA_CONSTQP (V4L2_CID_MPEG_BASE+580)
 
#define V4L2_CID_MPEG_VIDEOENC_H265_DISABLE_AMP (V4L2_CID_MPEG_BASE + 581)
 
#define V4L2_CID_MPEG_VIDEOENC_RECONFIG_FPS (V4L2_CID_MPEG_BASE+582)
 
#define V4L2_CID_MPEG_VIDEO_MAXBITRATE      (V4L2_CID_MPEG_BASE+583)
 
#define V4L2_CID_MPEG_VIDEOENC_VBVBUFSIZE       (V4L2_CID_MPEG_BASE+584)
 
#define V4L2_CID_MPEG_VIDEOENC_VBVINIT      (V4L2_CID_MPEG_BASE+585)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_AQ        (V4L2_CID_MPEG_BASE+586)
 
#define V4L2_CID_MPEG_VIDEOENC_ENABLE_TEMPORAL_AQ       (V4L2_CID_MPEG_BASE+587)
 
#define V4L2_CID_MPEG_VIDEOENC_TARGET_QUALITY (V4L2_CID_MPEG_BASE+588)
 
#define V4L2_CID_MPEG_VIDEOENC_COPY_TIMESTAMP (V4L2_CID_MPEG_BASE+589)
 
#define V4L2_CID_MPEG_VIDEOENC_INTRA_REFRESH (V4L2_CID_MPEG_BASE+590)
 
#define V4L2_CID_ARGUS_AUTO_WHITE_BALANCE_MODE (V4L2_CID_CAMERA_CLASS_BASE+20)
 
#define V4L2_CID_ARGUS_SENSOR_MODE (V4L2_CID_CAMERA_CLASS_BASE+32)
 
#define V4L2_CID_ARGUS_DENOISE_STRENGTH (V4L2_CID_CAMERA_CLASS_BASE+33)
 
#define V4L2_CID_ARGUS_DENOISE_MODE (V4L2_CID_CAMERA_CLASS_BASE+34)
 
#define V4L2_CID_ARGUS_EE_STRENGTH (V4L2_CID_CAMERA_CLASS_BASE+35)
 
#define V4L2_CID_ARGUS_EE_MODE (V4L2_CID_CAMERA_CLASS_BASE+36)
 
#define V4L2_CID_ARGUS_AE_ANTIBANDING_MODE (V4L2_CID_CAMERA_CLASS_BASE+37)
 
#define V4L2_CID_ARGUS_EXPOSURE_COMPENSATION (V4L2_CID_CAMERA_CLASS_BASE+38)
 
#define V4L2_CID_ARGUS_ISP_DIGITAL_GAIN_RANGE (V4L2_CID_CAMERA_CLASS_BASE+39)
 
#define V4L2_CID_ARGUS_COLOR_SATURATION (V4L2_CID_CAMERA_CLASS_BASE+40)
 
#define V4L2_CID_ARGUS_GAIN_RANGE (V4L2_CID_CAMERA_CLASS_BASE+41)
 
#define V4L2_CID_ARGUS_EXPOSURE_TIME_RANGE (V4L2_CID_CAMERA_CLASS_BASE+42)
 
#define V4L2_CID_ARGUS_METADATA (V4L2_CID_CAMERA_CLASS_BASE+43)
 
enum v4l2_skip_frames_type {
    V4L2_SKIP_FRAMES_TYPE_NONE = 0,
    V4L2_SKIP_FRAMES_TYPE_NONREF = 1,
    V4L2_SKIP_FRAMES_TYPE_DECODE_IDR_ONLY = 2,
};
 
enum v4l2_cuda_mem_type {
    V4L2_CUDA_MEM_TYPE_DEVICE = 0,
    V4L2_CUDA_MEM_TYPE_PINNED = 1,
    V4L2_CUDA_MEM_TYPE_UNIFIED = 2,
};
 
enum v4l2_videodec_input_error_type {
    V4L2_DEC_ERROR_NONE = 0x0,
    V4L2_DEC_ERROR_SPS = 0x1,
    V4L2_DEC_ERROR_PPS = 0x2,
    V4L2_DEC_ERROR_SLICE_HDR = 0x4,
    V4L2_DEC_ERROR_MISSING_REF_FRAME = 0x8,
    V4L2_DEC_ERROR_VPS = 0x10,
    V4L2_DEC_ERROR_FORCE32 = 0x7FFFFFFF
};
 
typedef struct v4l2_ctrl_videodec_statusmetadata_
{
    __u32  DecodeError;
    __u32  DecodedMBs;
    __u32  ConcealedMBs;
    __u32  nConcealedFromPOC;
    __u32  FrameDecodeTime;
    __u32 reserved[4];
}v4l2_ctrl_videodec_statusmetadata;
 
typedef struct v4l2_ctrl_videodec_refframe_metadata_
{
    __u32 bPresent;
    __u32 bIdrFrame;
    __u32 bLTRefFrame;
    __u32 bPredicted;
    __u32 nPictureOrderCnt;
    __u32 nFrameNum;
    __u32 nLTRFrameIdx;
    __u32 reserved[4];
} v4l2_ctrl_videodec_refframe_metadata;
 
typedef struct v4l2_ctrl_videodec_currentframe_metadata_
{
    __u32 bRefFrame;
    __u32 bIdrFrame;
    __u32 bLTRefFrame;
    __u32 nPictureOrderCnt;
    __u32 nFrameNum;
    __u32 nLTRFrameIdx;
    __u32 reserved[4];
} v4l2_ctrl_videodec_currentframe_metadata;
 
typedef struct v4l2_ctrl_videodec_dpbinfometadata_
{
    v4l2_ctrl_videodec_currentframe_metadata currentFrame;
    __u32 nActiveRefFrames;
    v4l2_ctrl_videodec_refframe_metadata RPSList[16];
    __u32 reserved[4];
} v4l2_ctrl_videodec_dpbinfometadata;
 
typedef struct v4l2_ctrl_h264dec_bufmetadata_
{
    __u32 nFrameNumBits;
    __u32  FrameType;
    v4l2_ctrl_videodec_dpbinfometadata dpbInfo;
    __u32 reserved[4];
}v4l2_ctrl_h264dec_bufmetadata;
 
typedef struct v4l2_ctrl_hevcdec_bufmetadata_
{
    __u32 nPocLsbBits;
    __u32  FrameType;
    v4l2_ctrl_videodec_dpbinfometadata dpbInfo;
    __u32 reserved[4];
}v4l2_ctrl_hevcdec_bufmetadata;
 
typedef struct v4l2_ctrl_videodec_inputbuf_metadata_
{
    __u32 nBitStreamError;
    __u32 reserved[4];
} v4l2_ctrl_videodec_inputbuf_metadata;
 
typedef struct v4l2_ctrl_videodec_outputbuf_metadata_
{
    __u8 ucColorPrimaries;
    __u8 ucTransferCharacteristics;
    __u8 ucMatrixCoefficients;
    __u32 bValidFrameStatus;
    v4l2_ctrl_videodec_statusmetadata    FrameDecStats;
    union {
        v4l2_ctrl_h264dec_bufmetadata H264DecParams;
        v4l2_ctrl_hevcdec_bufmetadata HEVCDecParams;
    }CodecParams;
    __u32 reserved[4];
} v4l2_ctrl_videodec_outputbuf_metadata;
enum v4l2_mpeg_video_h265_profile
{
    V4L2_MPEG_VIDEO_H265_PROFILE_MAIN = 0,
    V4L2_MPEG_VIDEO_H265_PROFILE_MAIN10 = 1,
    V4L2_MPEG_VIDEO_H265_PROFILE_MAINSTILLPICTURE = 2,
    V4L2_MPEG_VIDEO_H265_PROFILE_FREXT = 3,
 
    V4L2_MPEG_VIDEO_H265_FORCE32 = 0x7FFFFFFF
};
 
enum v4l2_enc_temporal_tradeoff_level_type
{
    V4L2_ENC_TEMPORAL_TRADEOFF_LEVEL_DROPNONE = 0,
    V4L2_ENC_TEMPORAL_TRADEOFF_LEVEL_DROP1IN5,
    V4L2_ENC_TEMPORAL_TRADEOFF_LEVEL_DROP1IN3,
    V4L2_ENC_TEMPORAL_TRADEOFF_LEVEL_DROP1IN2,
    V4L2_ENC_TEMPORAL_TRADEOFF_LEVEL_DROP2IN3,
};
 
enum v4l2_enc_hw_preset_type
{
    V4L2_ENC_HW_PRESET_DISABLE = 0,
    V4L2_ENC_HW_PRESET_ULTRAFAST = 1,
    V4L2_ENC_HW_PRESET_FAST,
    V4L2_ENC_HW_PRESET_MEDIUM,
    V4L2_ENC_HW_PRESET_SLOW,
    V4L2_ENC_HW_PRESET_DEFAULT = 0x7FFFFFFF
};
 
enum v4l2_enc_hw_tuning_info_type
{
    V4L2_ENC_TUNING_INFO_UNDEFINED = 0,
    V4L2_ENC_TUNING_INFO_HIGH_QUALITY = 1,
    V4L2_ENC_TUNING_INFO_LOW_LATENCY,
    V4L2_ENC_TUNING_INFO_ULTRA_LOW_LATENCY,
    V4L2_ENC_TUNING_INFO_LOSSLESS,
    V4L2_ENC_TUNING_INFO_FORCE32 = 0x7FFFFFFF
};
 
typedef struct v4l2_enc_hw_preset_type_param_
{
    enum v4l2_enc_hw_preset_type hw_preset_type;
    __u8 set_max_enc_clock;
    __u32 reserved[4];
}v4l2_enc_hw_preset_type_param;
 
enum v4l2_enc_slice_length_type
{
    V4L2_ENC_SLICE_LENGTH_TYPE_BITS = 0,
    V4L2_ENC_SLICE_LENGTH_TYPE_MBLK,
};
 
enum v4l2_enc_input_metadata_param
{
    V4L2_ENC_INPUT_ROI_PARAM_FLAG = 1,
    V4L2_ENC_INPUT_GDR_PARAM_FLAG = 1 << 1,
    V4L2_ENC_INPUT_RPS_PARAM_FLAG = 1 << 2,
    V4L2_ENC_INPUT_RC_PARAM_FLAG = 1 << 3,
    V4L2_ENC_INPUT_RECONCRC_PARAM_FLAG = 1 << 4,
    V4L2_ENC_INPUT_FORCE32 = 0x7FFFFFFF
};
 
enum v4l2_mpeg_video_h265_level {
 
    V4L2_MPEG_VIDEO_H265_LEVEL_1_0_MAIN_TIER = 0,
    V4L2_MPEG_VIDEO_H265_LEVEL_1_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_2_0_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_2_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_2_1_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_2_1_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_3_0_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_3_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_3_1_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_3_1_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_4_0_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_4_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_4_1_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_4_1_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_0_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_1_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_1_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_2_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_5_2_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_0_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_0_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_1_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_1_HIGH_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_2_MAIN_TIER,
    V4L2_MPEG_VIDEO_H265_LEVEL_6_2_HIGH_TIER,
};
 
#define V4L2_MPEG_VIDEO_BITRATE_MODE_CONSTQP 0x2
 
typedef struct v4l2_enc_slice_length_param_
{
    enum v4l2_enc_slice_length_type slice_length_type;
    __u32   slice_length;
    __u32 reserved[4];
}v4l2_enc_slice_length_param;
 
typedef struct v4l2_enc_virtual_buffer_size_
{
    __u32   size;
}v4l2_enc_virtual_buffer_size;
 
typedef struct v4l2_enc_num_ref_frames_
{
    __u32   frames;
    __u32 reserved[4];
}v4l2_enc_num_ref_frames;
 
typedef struct v4l2_enc_slice_intrarefresh_param_
{
    __u32   interval;
    __u32 reserved[4];
}v4l2_enc_slice_intrarefresh_param;
 
#define V4L2_MAX_ROI_REGIONS 8
 
typedef struct v4l2_enc_ROI_param_
{
    struct v4l2_rect  ROIRect;
    __s32   QPdelta;
    __u32 reserved[4];
} v4l2_enc_ROI_param;
 
typedef struct v4l2_enc_frame_ROI_params_
{
    __u32 num_ROI_regions;
    v4l2_enc_ROI_param ROI_params[V4L2_MAX_ROI_REGIONS];
    __u32   config_store;
    __u32 reserved[4];
}v4l2_enc_frame_ROI_params;
 
enum v4l2_ppe_feature
{
    V4L2_PPE_FEATURE_NONE = 0,
    V4L2_PPE_FEATURE_TAQ = (1 << 0),
    V4L2_PPE_FEATURE_SAQ = (1 << 1),
    V4L2_PPE_FEATURE_FORCE32 = 0x7FFFFFFF
};
 
typedef struct v4l2_enc_ppe_init_params_
{
    __u8 enable_ppe;
    __u32 feature_flags;
    __u8 enable_profiler;
    __s32 wait_time_ms;
    __u8 taq_max_qp_delta;
    __u8 taq_b_frame_mode;
    __u8 saq_max_qp_delta;
    __u32 reserved[3];
}v4l2_enc_ppe_init_params;
 
typedef struct MVInfo_ {
    __s32 mv_x   : 16;
    __s32 mv_y   : 14;
    __u32 weight : 2;
    __u32 reserved[4];
} MVInfo;
 
typedef struct v4l2_ctrl_videoenc_outputbuf_metadata_MV_ {
    __u32 bufSize;
    MVInfo *pMVInfo;
    __u32 reserved[4];
} v4l2_ctrl_videoenc_outputbuf_metadata_MV;
 
#define V4L2_MAX_REF_FRAMES  8
 
typedef struct v4l2_enc_frame_full_prop_
{
    __u32  nFrameId;
    __u8   bIdrFrame;
    __u8   bLTRefFrame;
    __u32  nPictureOrderCnt;
    __u32  nFrameNum;
    __u32  nLTRFrameIdx;
    __u32 reserved[4];
} v4l2_enc_frame_full_prop;
 
typedef struct v4l2_ctrl_videoenc_outputbuf_metadata_
{
    __u8 KeyFrame;
    __u8 EndofFrame;
    __u16 AvgQP;
    __u8 bIsGoldenOrAlternateFrame;
    __u8 bValidReconCRC;
    __u32 ReconFrame_Y_CRC;
    __u32 ReconFrame_U_CRC;
    __u32 ReconFrame_V_CRC;
    __u32 EncodedFrameBits;
    __u32 FrameMinQP;
    __u32 FrameMaxQP;
    __u32 bRPSFeedback_status;
    __u32 nCurrentRefFrameId;
    __u32 nActiveRefFrames;
    v4l2_enc_frame_full_prop RPSList[V4L2_MAX_REF_FRAMES];
    __u32 reserved[4];
} v4l2_ctrl_videoenc_outputbuf_metadata;
 
typedef struct v4l2_ctrl_video_metadata_
{
    v4l2_ctrl_videodec_inputbuf_metadata *VideoDecHeaderErrorMetadata;
    v4l2_ctrl_videodec_outputbuf_metadata *VideoDecMetadata;
    v4l2_ctrl_videoenc_outputbuf_metadata *VideoEncMetadata;
    v4l2_ctrl_videoenc_outputbuf_metadata_MV *VideoEncMetadataMV;
    __u32 buffer_index;
    __u32 reserved[4];
} v4l2_ctrl_video_metadata;
 
typedef struct v4l2_enc_gdr_params_
{
    __u32 nGDRFrames;
    __u32 reserved[4];
} v4l2_enc_gdr_params;
 
typedef struct v4l2_enc_enable_ext_rps_ctrl_
{
    __u8 bEnableExternalRPS;
    __u8 bGapsInFrameNumAllowed;
    /* TODO : Check for field details. */
    __u32 nH264FrameNumBits;
    /* TODO : Check for field details. */
    __u32 nH265PocLsbBits;
    __u32 reserved[4];
}v4l2_enc_enable_ext_rps_ctr;
 
 
typedef struct _v4l2_enc_frame_prop
{
    __u32 nFrameId;
    __u8 bLTRefFrame;
    __u32 reserved[4];
} v4l2_enc_frame_prop;
 
typedef struct v4l2_enc_frame_ext_rps_ctrl_params_
{
    __u32 nFrameId;
    __u8 bRefFrame;
    __u8 bLTRefFrame;
    __u32 nMaxRefFrames;
    __u32 nActiveRefFrames;;
    __u32 nCurrentRefFrameId;
    v4l2_enc_frame_prop RPSList[V4L2_MAX_REF_FRAMES];
    __u32 reserved[4];
}v4l2_enc_frame_ext_rps_ctrl_params;
 
 
typedef struct v4l2_enc_enable_ext_rate_ctrl_
{
    __u8 bEnableExternalPictureRC;
    __u32 nsessionMaxQP;
    __u32 reserved[4];
}v4l2_enc_enable_ext_rate_ctr;
 
typedef struct v4l2_enc_frame_ext_rate_ctrl_params_
{
    __u32 nTargetFrameBits;
    __u32 nFrameQP;
    __u32 nFrameMinQp;
    __u32 nFrameMaxQp;
    __u32 nMaxQPDeviation;
    __u32 reserved[4];
}v4l2_enc_frame_ext_rate_ctrl_params;
 
typedef struct v4l2_enc_enable_roi_param_
{
    __u8 bEnableROI;
    __u32 reserved[4];
}v4l2_enc_enable_roi_param;
 
typedef struct v4l2_enc_enable_reconcrc_param_
{
    __u8 bEnableReconCRC;
    __u32 reserved[4];
}v4l2_enc_enable_reconcrc_param;
 
typedef struct v4l2_enc_frame_ReconCRC_params_
{
    struct v4l2_rect  ReconCRCRect;
    __u32 reserved[4];
}v4l2_enc_frame_ReconCRC_params;
 
typedef struct v4l2_ctrl_videoenc_input_metadata_
{
    __u32    flag;
    v4l2_enc_frame_ROI_params *VideoEncROIParams;
    v4l2_enc_frame_ReconCRC_params *VideoReconCRCParams;
    v4l2_enc_gdr_params   *VideoEncGDRParams;
    v4l2_enc_frame_ext_rps_ctrl_params *VideoEncRPSParams;
    v4l2_enc_frame_ext_rate_ctrl_params *VideoEncExtRCParams;
    __u32    config_store;
    __u32 reserved[4];
} v4l2_ctrl_videoenc_input_metadata;
 
#define QP_RETAIN_VAL -1
 
typedef struct _v4l2_ctrl_video_qp_range
{
    __u32 MinQpI;
    __u32 MaxQpI;
    __u32 MinQpP;
    __u32 MaxQpP;
    __u32 MinQpB;
    __u32 MaxQpB;
} v4l2_ctrl_video_qp_range;
 
 
typedef struct _v4l2_ctrl_intra_refresh
{
    __u32 enableIntraRefresh;
    __u32 intraRefreshPeriod;
    __u32 intraRefreshCnt;
    __u32 reserved[4];
}v4l2_ctrl_intra_refresh;
 
typedef struct _v4l2_ctrl_video_constqp
{
    __u32 constQpI;
    __u32 constQpP;
    __u32 constQpB;
} v4l2_ctrl_video_constqp;
 
typedef struct _v4l2_ctrl_video_framerate
{
    __u32 fps_n;
    __u32 fps_d;
} v4l2_ctrl_video_framerate;
 
typedef struct _v4l2_ctrl_video_init_qp
{
    __u32 IInitQP;
    __u32 PInitQP;
    __u32 BInitQP;
} v4l2_ctrl_video_init_qp;
 
typedef struct v4l2_enc_av1_tile_config_
{
    __u8 bEnableTile;
    __u32 nLog2RowTiles;
    __u32 nLog2ColTiles;
}v4l2_enc_av1_tile_config;
 
 
enum v4l2_argus_denoise_mode {
    V4L2_ARGUS_DENOISE_MODE_UNKNOWN         = 0,
    V4L2_ARGUS_DENOISE_MODE_OFF             = 1,
    V4L2_ARGUS_DENOISE_MODE_FAST            = 2,
    V4L2_ARGUS_DENOISE_MODE_HIGH_QUALITY    = 3,
    V4L2_ARGUS_DENOISE_MODE_FORCE32         = 0x7FFFFFF
};
 
enum v4l2_argus_edge_enhance_mode {
    V4L2_ARGUS_EDGE_ENHANCE_MODE_UNKNOWN        = 0,
    V4L2_ARGUS_EDGE_ENHANCE_MODE_OFF            = 1,
    V4L2_ARGUS_EDGE_ENHANCE_MODE_FAST           = 2,
    V4L2_ARGUS_EDGE_ENHANCE_MODE_HIGH_QUALITY   = 3,
    V4L2_ARGUS_EDGE_ENHANCE_MODE_FORCE32        = 0x7FFFFFF
};
 
enum v4l2_argus_ac_ae_antibanding_mode {
    V4L2_ARGUS_AE_ANTIBANDING_MODE_UNKNOWN  = 0,
    V4L2_ARGUS_AE_ANTIBANDING_MODE_OFF      = 1,
    V4L2_ARGUS_AE_ANTIBANDING_MODE_AUTO     = 2,
    V4L2_ARGUS_AE_ANTIBANDING_MODE_50HZ     = 3,
    V4L2_ARGUS_AE_ANTIBANDING_MODE_60HZ     = 4,
    V4L2_ARGUS_AE_ANTIBANDING_MODE_FORCE32  = 0x7FFFFFF
};
 
enum v4l2_argus_ac_awb_mode {
    V4L2_ARGUS_AWB_MODE_OFF               = 1,
    V4L2_ARGUS_AWB_MODE_AUTO              = 2,
    V4L2_ARGUS_AWB_MODE_INCANDESCENT      = 3,
    V4L2_ARGUS_AWB_MODE_FLUORESCENT       = 4,
    V4L2_ARGUS_AWB_MODE_WARM_FLUORESCENT  = 5,
    V4L2_ARGUS_AWB_MODE_DAYLIGHT          = 6,
    V4L2_ARGUS_AWB_MODE_CLOUDY_DAYLIGHT   = 7,
    V4L2_ARGUS_AWB_MODE_TWILIGHT          = 8,
    V4L2_ARGUS_AWB_MODE_SHADE             = 9,
    V4L2_ARGUS_AWB_MODE_MANUAL            = 10,
    V4L2_ARGUS_AWB_MODE_FORCE32           = 0x7FFFFFF
};
 
enum v4l2_argus_ae_state {
    V4L2_ARGUS_AeState_Unknown            = 0,
    V4L2_ARGUS_AE_STATE_INACTIVE          = 1,
    V4L2_ARGUS_AE_STATE_SEARCHING         = 2,
    V4L2_ARGUS_AE_STATE_CONVERGED         = 3,
    V4L2_ARGUS_AE_STATE_FLASH_REQUIRED    = 4,
    V4L2_ARGUS_AE_STATE_TIMEOUT           = 5,
    V4L2_ARGUS_AE_STATE_FORCE32           = 0x7FFFFFF
};
 
enum v4l2_argus_awb_state {
    V4L2_ARGUS_AwbState_Unknown           = 0,
    V4L2_ARGUS_AWB_STATE_INACTIVE         = 1,
    V4L2_ARGUS_AWB_STATE_SEARCHING        = 2,
    V4L2_ARGUS_AWB_STATE_CONVERGED        = 3,
    V4L2_ARGUS_AWB_STATE_LOCKED           = 4,
    V4L2_ARGUS_AWB_STATE_FORCE32          = 0x7FFFFFF
};
 
typedef struct _v4l2_argus_denoise_strength
{
    float DenoiseStrength;
}v4l2_argus_denoise_strength;
 
typedef struct _v4l2_argus_edge_enhance_strength
{
    float EdgeEnhanceStrength;
}v4l2_argus_edge_enhance_strength;
 
typedef struct _v4l2_argus_exposure_compensation
{
    float ExposureCompensation;
}v4l2_argus_exposure_compensation;
 
typedef struct _v4l2_argus_ispdigital_gainrange
{
    float MinISPDigitalGainRange;
    float MaxISPDigitalGainRange;
}v4l2_argus_ispdigital_gainrange;
 
typedef struct _v4l2_argus_color_saturation
{
    __u8 EnableSaturation;
    float ColorSaturation;
}v4l2_argus_color_saturation;
 
typedef struct _v4l2_argus_gainrange
{
    float MinGainRange;
    float MaxGainRange;
}v4l2_argus_gainrange;
 
typedef struct _v4l2_argus_exposure_timerange
{
    __u64 MinExposureTimeRange;
    __u64 MaxExposureTimeRange;
}v4l2_argus_exposure_timerange;
 
typedef struct _v4l2_argus_ctrl_metadata
{
    __u8 AeLocked;
    __u8 ValidFrameStatus;
    __u32 BufferIndex;
    __u32 FocuserPosition;
    __u32 AwbCCT;
    __u32 SensorSensitivity;
    __u64 FrameDuration;
    __u64 FrameReadoutTime;
    __u64 SensorExposureTime;
    float IspDigitalGain;
    float SceneLux;
    float SensorAnalogGain;
    enum v4l2_argus_ae_state AEState;
    enum v4l2_argus_awb_state AWBState;
    __u32 reserved[4];
}v4l2_argus_ctrl_metadata;
enum v4l2_nv_buffer_layout {
    V4L2_NV_BUFFER_LAYOUT_PITCH = 0,  
    V4L2_NV_BUFFER_LAYOUT_BLOCKLINEAR = 1, 
};
 
enum v4l2_flip_method {
    V4L2_FLIP_METHOD_IDENTITY = 0, 
    V4L2_FLIP_METHOD_90L = 1,      
    V4L2_FLIP_METHOD_180 = 2,      
    V4L2_FLIP_METHOD_90R = 3,      
    V4L2_FLIP_METHOD_HORIZ = 4,    
    V4L2_FLIP_METHOD_INVTRANS = 5, 
    V4L2_FLIP_METHOD_VERT = 6,     
    V4L2_FLIP_METHOD_TRANS = 7,    
};
 
enum v4l2_interpolation_method {
  V4L2_INTERPOLATION_NEAREST = 1,   
  V4L2_INTERPOLATION_BILINEAR = 2,  
  V4L2_INTERPOLATION_5_TAP = 3,     
  V4L2_INTERPOLATION_10_TAP = 4,    
  V4L2_INTERPOLATION_SMART = 5,     
  V4L2_INTERPOLATION_NICEST = 6,    
};
 
enum v4l2_tnr_algorithm {
  V4L2_TNR_ALGO_ORIGINAL = 0,           
  V4L2_TNR_ALGO_OUTDOOR_LOW_LIGHT = 1,  
  V4L2_TNR_ALGO_OUTDOOR_MEDIUM_LIGHT = 2, 
  V4L2_TNR_ALGO_OUTDOOR_HIGH_LIGHT = 3, 
  V4L2_TNR_ALGO_INDOOR_LOW_LIGHT = 4, 
  V4L2_TNR_ALGO_INDOOR_MEDIUM_LIGHT = 5, 
  V4L2_TNR_ALGO_INDOOR_HIGH_LIGHT = 6, 
};
 
enum v4l2_yuv_rescale_method {
  V4L2_YUV_RESCALE_NONE = 0,
  V4L2_YUV_RESCALE_STD_TO_EXT = 1,
  V4L2_YUV_RESCALE_EXT_TO_STD = 2,
};
 
typedef struct v4l2_ctrl_video_displaydata_
{
    __u32 masteringdisplaydatapresent;
}v4l2_ctrl_video_displaydata;
 
typedef struct _v4l2_ctrl_video_hdrmasteringdisplaydata
{
    // idx 0 : G, 1 : B, 2 : R
    __u16 display_primaries_x[3];       // normalized x chromaticity cordinate. It shall be in the range of 0 to 50000
    __u16 display_primaries_y[3];       // normalized y chromaticity cordinate. It shall be in the range of 0 to 50000
    __u16 white_point_x;    // normalized x chromaticity cordinate of white point of mastering display
    __u16 white_point_y;    // normalized y chromaticity cordinate of white point of mastering display
    __u32 max_display_parameter_luminance;      // nominal maximum display luminance in units of 0.0001 candelas per square metre
    __u32 min_display_parameter_luminance;      // nominal minimum display luminance in units of 0.0001 candelas per square metre
} v4l2_ctrl_video_hdrmasteringdisplaydata;
 
 
typedef struct _v4l2_ctrl_video_device_poll
{
    __u16 req_events;    // Requested events, a bitmask of POLLIN, POLLOUT, POLLERR, POLLPRI.
    __u16 resp_events;    // Returned events a similar bitmask of above events.
} v4l2_ctrl_video_device_poll;
 
#endif /*__V4L2_NV_EXTENSIONS_H__*/