Miscellaneous Configuration

The different settings that do not fit into the other categories are documented in miscellaneous configuration file.

MB1 Feature Fields

These features are Boolean flags that enable or disable functionality in MB1:

Field	Description
disable_spe	Here are the values: 0: Disables load of SPE-FW by MB1. 1: Enables load of SPE-FW by MB1.
enable_dram_page_blacklisting	Here are the values: 0: Disables DRAM ECC page blacklisting feature. 1: Enables DRAM ECC page blacklisting feature.
disable_sc7	Here are the values: 0: Enables SC7-entry/exit support. 1: Enables SC7-entry/exit support.
disable_fuse_visibility	Certain fuses cannot be read or written by default because they are not visible. 0: Keeps the default visibility of fuses. 1: Enables visibility of such fuses.
l2_mss_encrypt_regeneration	Here are the values: On L2 RAMDUMP reset, regenerate MSS encryption keys for the carveouts. This is a bit-field with the following bit-mapping: 1:TZDRAM 3:GSC
se_ctx_save_tz_lock	Restrict SE context save and SHA_CTX_INTEGRITY operation to TZ.
disable_mb2_glitch_protection	Disable checks on DCLS faults, TCM parity error, TCM and cache ECC.
enable_dram_error_injection	Here are the values: 0: Disable DRAM error injection tests 1: Enable DRAM error injection tests
enable_dram_staged_scrubbing	Here are the values: 0: If DRAM ECC is enabled, scrub entire DRAM 1: If DRAM ECC is enabled, scrub DRAM in stages - each BL responsible for the DRAM portions that it uses.
wait_for_debugger_connection	Here is the value: 0: Do not wait for debugger connection at end of MB1.
limit_l1_boot_client_freq	Here are the values: 1: Spin in a while(1) loop at end of MB1 for debugger connection. 0: Keep boot client frequencies (BPMP, SE, CBB, etc) same for L0 and L1 reset.

Clock Data

The following fields allow certain clock-related customization.

Field	Description
bpmp_cpu_nic_divider	Controls the BPMP CPU frequency. 0: Skip programming CLK_SOURCE_BPMP_CPU_NIC[BPMP_CPU_NIC_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_BPMP_CPU_NIC[BPM_CPU_NIC_CLK_DIVISOR].
bpmp_apb_divider	Controls the BPMP APB frequency. 0: Skip programming of CLK_SOURCE_BPMP_APB[BPMP_APB_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_BPMP_APB[BPMP_APB_CLK_DIVISOR].
axi_cbb_divider	Controls the control backbone (CBB) frequency. 0: Skip programming of CLK_SOURCE_AXI_CBB[AXI_CBB_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_AXI_CBB[AXI_CBB_CL_K_DIVISOR].
se_divider	Controls the SE (security engine) frequency. 0: Skip programming of CLK_SOURCE_SE[SE_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_SE[SE_CLK_DIVISOR].
aon_cpu_nic_divider	Controls the AON/SPE CPU frequency. 0: Skip programming of CLK_SOURCE_AON_CPU_NIC[AON_CPU_NIC_CLK_DIVISOR]. on-zero: 1 + Value to be programmed in CLK_SOURCE_AON_CPU_NIC[AON_C←PU_NIC_CLK_DIVISOR].
aon_apb_divider	Controls the AON APB frequency. 0: Skip programming of CLK_SOURCE_AON_CPU_NIC[AON_CPU_NIC_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_AON_CPU_NIC[AON_C←PU_NIC_CLK_DIVISOR].
aon_can0_divider	Controls the AON CAN1 frequency. 0: Skip programming of CLK_SOURCE_CAN1[CAN1_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_CAN1[CAN1_CLK_DIVISOR].
aon_can1_divider	Controls the AON CAN2 frequency. 0: Skip programming of CLK_SOURCE_CAN2[CAN2_CLK_DIVISOR]. non-zero: 1 + Value to be programmed in CLK_SOURCE_CAN2[CAN2_CLK_DIVISOR].
osc_drive_strength	Oscillator drive strength.
pllaon_divn	DIVN value of PLLAON. 0: Use PLLAON_DIVN = 30, PLLAON_DIVM = 1, PLLAON_DIVP = 2. non-zero: 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVN].
pllaon_divm	DIVN value of PLLAON. DIVM value of PLLAON (ignored when clock.pllaon_divn = 0). 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVM].
pllaon_divp	DIVN value of PLLAON. DIVP value of PLLAON (ignored when clock.pllaon_divn = 0). 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVP].
pllaon_divn_frac	Value to be programmed.

AST Data

MB1/MB2 uses AST (address-translation) module for mapping the DRAM carveout for different firmware into the 32-bit virtual address-space of the various auxiliary processor clusters.

MB1 AST Data

Field	Description
mb2_va	Virtual address for MB2 carveout in BPMP-R5 address-space.
spe_fw_va	Virtual address for SPE-FW carveout in AON-R5 address-space.
misc_carveout_va	Virtual address for MISC carveout in SCE-R5 address-space.
rcm_blob_carveout_va	Virtual address for RCM-blob carveout in SCE-R5 address-space.
temp_map_a_carveout_va	Virtual address for temporary mapping A used while loading binaries.
temp_map_a_carveout_size	Size for temporary mapping A used while loading binaries.
temp_map_a_carveout_va	Virtual address for temporary mapping B used while loading binaries.
temp_map_a_carveout_size	Size for temporary mapping B used while loading binaries.

Note

Here is some additional information:

• None of the VA spaces above should overlap with an MMIO region or with each other.

• Size fields should be power of 2.

• VA fields should be aligned to their mapping/carveouts.

Carveout Configuration

Although SDRAM Configuration has MC carveout’s preferred base, size and permissions, it does not have the information that is required to allocate the carveouts by MB1. This information is specified by using the miscellaneous configuration file.

For carveouts that are not protected by MC, all information (including size and preferred base address) is specified using miscellaneous configuration file.

Each MC carveout configuration parameter has the following form:

/{
    misc {
        carveout {
            <carveout-type {
                <parameter = <value>;
            };
        };
    };
};

where:

• carveout-type identifies the carveout and is one of the following:

carveout-type	Description
gsc@[1-31]	GSC carveout for various purposes.
mts	MTS/CPU-uCode carveout.
tzdram	TZDRAM carveout used for SecureOS.
os	OS carveout used for loading OS kernel.
rcm	RCM carveout used for loading RCM-blob during RCM mode (temporary boot carveout).

• <parameter> is one of the following:

Parameter	Description
pref_base	Preferred base address of carveout.
size	Size of carveout (in bytes).
alignment	Alignment of base address of carveout (in bytes).
ecc_protected	When DRAM region-based ECC is enabled and there are non-ECC protected DR←AM regions, whether to allocate the carveout from ECC protected region. 0: Allocate from non ECC protected region 1: Allocate from ECC protected region
bad_page_tolerant	When DRAM page blacklisting is enabled, whether it is OK to have bad pages in the carveout (only possible for very large carveouts and which are handled completely by component that can avoid bad pages using SMMU/MMU). 0: No bad pages allowed for the carveout. 1: Bad pages allowed for the carveout (allocation can be done without filtering bad pages).

The valid combination of the carveouts and their parameters are specified in following table:

Supported carveout-type	pref_base	size	alignment	ecc_protected	bad_page_tolerant
gsc-[1-31]/mts	N/A	N/A	Yes	Yes	Yes
tzdram/mb2/cpubl/misc/os/rcm	Yes	Yes	Yes	Yes	Yes

Coresight Data

Field	Description
cfg_system_ctl	Value to be programmed to CORESIGHT_CFG_SYSTEM_CTL.
cfg_csite_mc_wr_ctrl	Value to be programmed to CORESIGHT_CFG_CSITE_MC_WR_CTRL.
cfg_csite_mc_rd_ctrl	Value to be programmed to CORESIGHT_CFG_CSITE_MC_RD_CTRL.
cfg_etr_mc_wr_ctrl	Value to be programmed to CORESIGHT_CFG_ETR_MC_WR_CTRL.
cfg_etr_mc_rd_ctrl	Value to be programmed to CORESIGHT_CFG_ETR_MC_RD_CTRL.
cfg_csite_cbb_wr_ctrl	Value to be programmed to CORESIGHT_CFG_CSITE_CBB_WR_CTRL.
cfg_csite_cbb_rd_ctrl	Value to be programmed to CORESIGHT_CFG_CSITE_CBB_RD_CTRL.

Firmware Load and Entry Configuration

The firmware configuration is specified as follows:

/{
    misc {
        ...
        ...
        firmware {
                    <firmware-type> {
                            <parameter> = <value>;
            };
        };
    };
};

where <firmware-type> is one of the mb2 or tzdram-e13 and <parameter> is specified in the following table:

Field	Description
load-offset	Offset in the <firmware> carveout where <firmware> binary is loaded.
entry-offset	Offset of the <firmware> entry point in <firmware> carveout.

CPU Configuration

Field	Description
ccplex_platform_features	CPU platform features (should be 0).
clock_mode.clock_burst_policy	CCPLEX clock burst policy.
clock_mode.max_avfs_mode	Highest CCPLEX AVFS mode
nafll_cfg2/fll_init	CCPLEX NAFLL CFG2 [Fll Init]
nafll_cfg2/fll_ldmem	CCPLEX NAFLL CFG2 [Fll Ldmem]
nafll_cfg2/fll_switch_ldmem	CCPLEX NAFLL CFG2 [Fll Switch Ldmem]
nafll_cfg3	CCPLEX NAFLL CFG3
nafll_ctrl1	CCPLEX NAFLL CTRL1
nafll_ctrl2	CCPLEX NAFLL CTRL2
lut_sw_freq_req/sw_override_ndiv	SW override for CCPLEX LUT frequency request
lut_sw_freq_req/ndiv	NDIV for CCPLEX LUT frequency request
lut_sw_freq_req/vfgain	VFGAIN for CCPLEX LUT frequency request
lut_sw_freq_req/sw_override_vfgain	VFGAIN override for CCPLEX LUT frequency request
nafll_coeff/mdiv	MDIV for NAFLL coefficient
nafll_coeff/pdiv	PDIV for NAFLL coefficient
nafll_coeff/fll_frug_main	FLL frug main for NAFLL coefficient
nafll_coeff/fll_frug_fast	FLL frug fast for NAFLL coefficient
adc_vmon.enable	Enable CCPLEX ADC voltage monitor
min_adc_fuse_rev	Minimum ADC fuse revision
pllx_base/divm	PLLX DIVM
pllx_base/divn	PLLX DIVN
pllx_base/divp	PLLX DIVP
pllx_base/enable	Enable PLLX
pllx_base/bypass	PLLX Bypass Enable

Other Configuration

Field	Description
aocluster.evp_reset_addr	AON/SPE reset vector (in SPE BTCM).
carveout_alloc_direction	Carveout allocation direction. 0: End of DRAM 1: End of 2GB DRAM (32b address space) 2: Start of DRAM
se_oem_group	Value to be programmed to SE0_OEM_GROUP_0/SE_RNG1_RNG1_OEM_GROUP_0. (NVHS / NVLS / Lock bits are forced set)
i2c-freq	List of < <i2c controller instance> <Frequency (in KHz) of I2C controller instance > where, I2C controller instance has valid values 0 to 8.

MB1 Soft Fuse Configurations

There are certain platform-specific configurations or decisions in MB1 that are required from the early stages of MB1 even before storage is initialized and MB1-BCT is read (for example, debug port details, certain boot-mode controls, behavior in case of failure, and so on.). To address this requirement, an array of 64 fields is added to signed section of BR-BCT, which is opaque to BR but is consumed by MB1. In recovery mode, BR does not read BR-BCT, so this array is kept part of RCM message and is copied by BR to the same location where BR will have kept it in coldboot as part of BR-BCT. This array is called MB1 software fuses (soft-fuse).

Debug Controls

Field	Description
verbosity	Controls verbosity of debug logs on UART (verbosity increases with increasing value). 0: UART logs disabled 1: Critical prints only 2: Error 3: Warn 4: Info 5: Debug
uart_instance	UART controller number where debug logs are spewed. 0: UARTA (only for simulation platforms) 2: UARTC (open-box debug) 5: UARTF (closed-box debug, USB-Type C over DP_AUX pins) 7: UARTH (closed-box debug, USB-Type C over USB-OTG
usb_2_nvjtag	On-chip controller connected to the USB2 pins. 0: ARMJTAG 1: NVJTAG
swd_usb_port_sel	USB2 port over which SWD should be configured. 0: USB2 Port0 1: USB2 Port1
uart8_usb_port_sel	USB2 port over which UART should be configured. 0: USB2 Port0 1: USB2 Port1
wdt_enable	Enable BPMP WDT 5th-expiry during the execution of MB1/MB2 (boolean).
wdt_period_secs	BPMP WDT time period (in secs) per expiry.

Boot Failure Controls

Field	Description
switch_bootchain	Switch boot chain in case of failure (boolean).
reset_to_recovery	Trigger L1 RCM reset on failure (boolean).
bootchain_switch_mechanism	Used if switch_bootchain is set to 1. 0: Use BR-based boot-chain switching. 1: Use Android A/B based boot-chain switching.
bootchain_retry_count	Maximum number of retries for a single boot-chain (0-15).

On/Off IST Mode Controls

Field	Description
platform_detection_flow	In RCM mode, enter platform detection flow (boolean).
enable_tegrashell	In RCM mode, enter tegrashell mode (allowed only if FUSE_SECURITY_MODE_0 is not blown) (boolean).
enable_IST	Enable Key On/Off IST boot (boolean).
enable_LO_IST	Enable Key ON (L0) IST boot mode (boolean). Used only if EnableIST is set to 1.
enable_dgpu_IST	Enable dGPU IST during IST boot modes (boolean).

Frequency Monitor Controls

Field	Description
vrefRO_calib_override	Override VrefRO Calibration Override based on SoftFuse instead of fuse (boolean).
vrefRO_min_rev_threshold	Program VrefRO frequency adjustment target based on FUSE_VREF_CALIB_0 if (FUSE_ECO_RESERVE_1[3:0] > vrefRO_min_rev_threshold) (Used if vrefRO_calib_override is set to 0).
vrefRO_calib_val	VrefRO Calibration Value used to program VrefRO frequency adjustment target (Used if vrefRO_calib_override is set to 1).
osc_threshold_low	Lower Threshold of the FMON counter for OSC clock
osc_threshold_high	Upper Threshold of the FMON counter for OSC clock.
pmc_threshold_low	Lower Threshold of the FMON counter for 32K clock.
pmc_threshold_high	Upper Threshold of the FMON counter for 32K clock.

The miscellaneous configuration files are in the Linux_for_Tegra/bootloader/generic/BCT directory.

Here is a DTS example of the new miscellaneous configuration file:

/dts-v1/;

#include "tegrabl_carveout_id.h"
#include "tegra234-mb1-bct-misc-common.dtsi"
#include "tegra234-mb1-bct-carveout-l4t.dtsi"
#include "tegra234-mb1-bct-disable-fsi-carveouts.dtsi"

/ {
    misc {
            disable_sc7 = <0>;
            enable_tsec = <0>;
                enable_4pin_ram_code = <1>;

            ///////// SOCTHERM ///////////
            soctherm {
                        max_chip_limit = <0x69>;
                    min_chip_limit = <0xFFFFFFE4>;
            };

            carveout {
                    aux_info@CARVEOUT_CCPLEX_IST {
                                pref_base = <0x0 0x0>;
                            size = <0x0 0x0>; // 0MB
                            alignment = <0x0 0x0>; // 0MB
                    };
            };

                vmon {
                    vdd_soc {
                            soc_vmon_config@0 {
                                    sku_info = <0x0>;
                                    vmin_threshold = <0x1a>;
                                    vmax_threshold = <0x76>;
                            };
                        };

                    vdd_cpu {
                            cpu_vmon_config@0 {
                                    sku_info = <0x0>;
                                        vmin_threshold = <0x15>;
                                    vmax_threshold = <0x7b>;
                            };
                    };
            };
    };
};