Storage Device Configuration
The Storage Device configuration file contains the platform-specific settings for storage devices in the MB1/MB2 stages.
The DTS configuration file is in the following form:
/ {
device {
<storage_device>@instance-# {
<parameter> = <value>;
};
};
};
where:
<storage-device>
is the storage device controller (qspiflash / ufs / sdmmc / sata)<instance-#>
is the instance of the storage controller<parameter>
is controller specific parameter as shown below.
QSPI Flash Parameters
Parameter |
Description |
---|---|
|
QSPI controller clock source:
|
|
Frequency of the clock source in Hz. |
|
QSPI controller frequency in Hz. |
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|
Number of dummy cycles as per the QSPI flash. |
|
TX trimmer value |
|
RX trimmer value |
SDMMC Parameters
Parameter |
Description |
---|---|
clock-source-id |
|
|
Frequency of the clock source in Hz. |
|
|
|
Pull-down offset |
|
Pull-up offset |
|
Enable the HS400 strobe. |
|
HS DQS trim value |
UFS Parameters
Parameter |
Description |
---|---|
|
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|
Maximum number of UFS lanes (1-2) |
|
Alignment of pages that are used for UFS data structures in bytes. |
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SATA Parameters
Parameter |
Description |
---|---|
transfer-speed |
|
The storage device configuration file are kept in the Linux_for_Tegra/bootloader/generic/BCT
directory.
The DTS format example of the storage device configuration file:
/dts-v1/;
#include <define.h>
/ {
device {
qspiflash@0 {
clock-source-id = <PLLC_MUXED>;
clock-source-frequency = <13000000>;
interface-frequency = <13000000>;
enable-ddr-mode;
maximum-bus-width = <QSPI_4_LANE>;
fifo-access-mode = <DMA_MODE>;
read-dummy-cycle = <8>;
trimmer1-val = <0>;
trimmer2-val = <0>;
};
sdmmc@3 {
clock-source-id = <PLLC4_OUT2>;
clock-source-frequency = <52000000>;
best-mode = <HS400>;
pd-offset = <0>;
pu-offset = <0>;
//enable-strobe-hs400; This property is not there means it is disabled dqs-trim-hs400 = <0>;
};
ufs@0 {
max-hs-mode = <HS_GEAR_3>;
max-pwm-mode = <PWM_GEAR_4>;
max-active-lanes = <2>;
page-align-size = <4096>;
enable-hs-mode;
//enable-fast-auto-mode; enable-hs-rate-b;
//enable-hs-rate-a = <0>; init-state = <0>;
};
}
};