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Pinouts Description

NC-SI Sideband Interface

The following table lists the NC-SI management interface pinout descriptions. For further details, please refer to NC-SI Sideband Interface.

Pin Name	Pin Description
GND	Ground
RBT_RDX0	Receive data. Data signals from the network controller to the BMC.
RBT_RDX1
RBT_CRS_DV	Carrier sense/receive data validly
GND	Ground
RBT_TX0	Transmit data. Data signals from the BMC to the network controller
RBT_TX1
RBT_TX_EN	Transmit enable
RBT_REF_CLK	RBT Reference clock
GND	Ground
ARB_OUT	NC-SI hardware arbitration output
ARB_IN	NC-SI hardware arbitration input
GND	Ground
I2C_CLK0	I2C clock (Debug)
I2C_SDA0	I2C Data (Debug)
PKG_ID0	NC-SI PKG_ID [0]
PKG_ID1	NC-SI PKG_ID [1]
RBT_ISOLATE_N	The signal used to indicate the board has powered and is ready for the NC-SI physical layer connection to be present
FNP	ConnectX Flash is NOT present
enable_inband_recovery	PCIe operatiin live fish mode
PPS IN	PPS input for timing applications
PPS OUT	PPS output for timing applications
RSVD3	Reserved
RSVD4	Reserved
RSVD5	Reserved
RSVD6	Reserved
RSVD7	Reserved
RSVD8	Reserved
RSVD9	Reserved
RSVD10	Reserved

MCIO Interface

The tables below list the MCIO connector pinout descriptions, per SuperNIC OPN. For further details, please refer to MCIO Connector.

Default (Socket-Direct) Pinouts for 900-9X81Q-00CN-ST0 and 900-9X81E-00EX-ST0 SuperNICs

Additional Electrical Information	Description/Direction	Pin	Pin	Description/Direction	Additional Electrical Information
	GND	A1	B1	GND
	PERp0	A2	B2	PETp0
	PERn0	A3	B3	PETn0
	GND	A4	B4	GND
	PERp1	A5	B5	PETp1
	PERn1	A6	B6	PETn1
	GND	A7	B7	GND
Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 100k ohm	SMBUS_SCL (IN)	A8	B8	3V3_AUX (IN)	Logic: Same power requirements as 3V3_AUX in PCIe spec Voltage Level: 3.3V
Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 100k ohm	SMBUS_SDA (BID)	A9	B9	FLEXIO0_A	Presence of PU/PD: PD termination 42.2 ohm
	GND	A10	B10	GND
Logic: Push-pull, active low Voltage Level: 3.3V	PERST_A_N (IN)	A11	B11	REFCLK_A_Dp (IN)	Logic: PCIe REFCLK IN
Logic: Active low Voltage Level: 3.3V Presence of PU/PD: PD 200 ohm Recommended implementation on System level: PU 100k ohm	CBL_PRES_A (OUT)	A12	B12	REFCLK_A_Dn (IN)	Logic: PCIe REFCLK IN
	GND	A13	B13	GND
	PERp2	A14	B14	PETp2
	PERn2	A15	B15	PETn2
	GND	A16	B16	GND
	PERp3	A17	B17	PETp3
	PERn3	A18	B18	PETn3
	GND	A19	B19	GND
	PERp4	A20	B20	PETp4
	PERn4	A21	B21	PETn4
	GND	A22	B22	GND
	PERp5	A23	B23	PETp5
	PERn5	A24	B24	PETn5
	GND	A25	B25	GND
Presence of PU/PD: PD termination 42.2 ohm	FLEXIO3_A/I2C_M_SDA_A (NC)	A26	B26	FLEXIO1_A/REFCLK_B_Dp	Presence of PU/PD: PD termination 42.2 ohm
Presence of PU/PD: PD termination 42.2 ohm	FLEXIO4_A/I2C_M_SCL_A (NC)	A27	B27	FLEXIO2_A/REFCLK_B_Dn	Presence of PU/PD: PD termination 42.2 ohm
	GND	A28	B28	GND
Presence of PU/PD: PD termination 42.2 ohm	PERST_B_N (IN)	A29	B29	FLEXIO7_A	Presence of PU/PD: PD termination 42.2 ohm
Presence of PU/PD: PD termination 42.2 ohm	CBL_PRES_B (OUT)	A30	B30	FLEXIO8_A	Presence of PU/PD: PD termination 42.2 ohm
	GND	A31	B31	GND
	PERp6	A32	B32	PETp6
	PERn6	A33	B33	PETn6
	GND	A34	B34	GND
	PERp7	A35	B35	PETp7
	PERn7	A36	B36	PETn7
	GND	A37	B37	GND
	Key
	GND	A38	B38	GND
	PERp8	A39	B39	PETp8
	PERn8	A40	B40	PETn8
	GND	A41	B41	GND
	PERp9	A42	B42	PETp9
	PERn9	A43	B43	PETn9
	GND	A44	B44	GND
	PERp10	A45	B45	PETp10
	PERn10	A46	B46	PETn10
	GND	A47	B47	GND
	PERp11	A48	B48	PETp11
	PERn11	A49	B49	PETn11
	GND	A50	B50	GND
	PERp12	A51	B51	PETp12
	PERn12	A52	B52	PETn12
	GND	A53	B53	GND
	PERp13	A54	B54	PETp13
	PERn13	A55	B55	PETn13
	GND	A56	B56	GND
	PERp14	A57	B57	PETp14
	PERn14	A58	B58	PETn14
	GND	A59	B59	GND
	PERp15	A60	B60	PETp15
	PERn15	A61	B61	PETn15
	GND	A62	B62	GND

Switch Mode Pinouts for 900-9X81E-00EX-DT0 SuperNICs

Additional Electrical Information	Direction	Description/Direction	Pin	Pin	Description/Direction	Additional Electrical Information
		GND	A1	B1	GND
		PERp0	A2	B2	PETp0
		PERn0	A3	B3	PETn0
		GND	A4	B4	GND
		PERp1	A5	B5	PETp1
		PERn1	A6	B6	PETn1
		GND	A7	B7	GND
Logic: Same power requirements as 3V3_AUX in PCIe spec Voltage Level: 3.3V	OUT	3V3_AUX (OUT)	A8	B8	SMBUS_SCL_A (OUT)	Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 45.3k ohm
Logic: Open-drain Voltage Level: 3.3V Recommended implementation on System level: PU resistor	IN	VPP_INT_N (IN)	A9	B9	SMBUS_SDA_A (BID)	Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 45.3k ohm
		GND	A10	B10	GND
Logic: PCIe REFCLK OUT	OUT	REFCLK_A_Dp (OUT)	A11	B11	PERST_A_N (OUT)	Logic: Push-pull, active low Voltage Level: 3.3V
Logic: PCIe REFCLK OUT	OUT	REFCLK_A_Dn (OUT)	A12	B12	CBL_PRES_A (IN)	Logic: Active low Voltage Level: 3.3V Presence of PU/PD: PU 45.3k ohm PD 200 ohm
		GND	A13	B13	GND
		PERp2	A14	B14	PETp2
		PERn2	A15	B15	PETn2
		GND	A16	B16	GND
		PERp3	A17	B17	PETp3
		PERn3	A18	B18	PETn3
		GND	A19	B19	GND
		PERp4	A20	B20	PETp4
		PERn4	A21	B21	PETn4
		GND	A22	B22	GND
		PERp5	A23	B23	PETp5
		PERn5	A24	B24	PETn5
		GND	A25	B25	GND
Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 1.5k ohm	BID	VPP_SDA_A	A26	B26	FLEXIO3_A /PWRBRK/SER_CLK(NC)	Presence of PU/PD: PD termination 42.2 ohm
Logic: Open-drain Voltage Level: 3.3V Presence of PU/PD: PU 1.5k ohm	OUT	VPP_SCL_A	A27	B27	FLEXIO4_A /WAKE/SER_CAPTURE(NC)	Presence of PU/PD: PD termination 42.2 ohm
		GND	A28	B28	GND
Presence of PU/PD: PD termination 42.2 ohm		FLEXIO7_A/USB2_A_Dp /SER_DO(NC)	A29	B29	PERST_B_N	Presence of PU/PD: PD termination 42.2 ohm
Presence of PU/PD: PD termination 42.2 ohm		FLEXIO8_A/USB2_A_Dn/SER_DI(NC)	A30	B30	CBL_PRES_B	Presence of PU/PD: PD termination 42.2 ohm
		GND	A31	B31	GND
		PERp6	A32	B32	PETp6
		PERn6	A33	B33	PETn6
		GND	A34	B34	GND
		PERp7	A35	B35	PETp7
		PERn7	A36	B36	PETn7
		GND	A37	B37	GND
		Key
		GND	A38	B38	GND
		PERp8	A39	B39	PETp8
		PERn8	A40	B40	PETn8
		GND	A41	B41	GND
		PERp9	A42	B42	PETp9
		PERn9	A43	B43	PETn9
		GND	A44	B44	GND
		PERp10	A45	B45	PETp10
		PERn10	A46	B46	PETn10
		GND	A47	B47	GND
		PERp11	A48	B48	PETp11
		PERn11	A49	B49	PETn11
		GND	A50	B50	GND
		PERp12	A51	B51	PETp12
		PERn12	A52	B52	PETn12
		GND	A53	B53	GND
		PERp13	A54	B54	PETp13
		PERn13	A55	B55	PETn13
		GND	A56	B56	GND
		PERp14	A57	B57	PETp14
		PERn14	A58	B58	PETn14
		GND	A59	B59	GND
		PERp15	A60	B60	PETp15
		PERn15	A61	B61	PETn15
		GND	A62	B62	GND

On This Page

Pinouts Description

NC-SI Sideband Interface

MCIO Interface

Default (Socket-Direct) Pinouts for 900-9X81Q-00CN-ST0 and 900-9X81E-00EX-ST0 SuperNICs

Switch Mode Pinouts for 900-9X81E-00EX-DT0 SuperNICs