Pin Description

The Active Optical Cable (AOC) pin assignment is SFF-8679 compliant.

QSFP56 Pin Description 200Gb/s End

Pin	Symbol	Description	Pin	Symbol	Description
1	Ground	Ground	20	Ground	Ground
2	Tx2n	Connected to Port 1 lane Rx2 Inverted Data	21	Rx2n	Connected to Port 1 lane Tx2 Inverted Data
3	Tx2p	Connected to Port 1 lane Rx2 Non-Inverted Data	22	Rx2p	Connected to Port 1 lane Tx2 Non-Inverted Data
4	Ground	Ground	23	Ground	Grounds
5	Tx4n	Connected to Port 2 lane Rx2 Non-Inverted Data	24	Rx4n	Connected to Port 2 lane Tx2 Inverted Data
6	Tx4p	Connected to Port 2 lane Rx2 Inverted Data	25	Rx4p	Connected to Port 2 lane Tx2 Non-Inverted Data
7	Ground	Ground	26	Ground	Ground
8	Mod-SelL	Cable Select	27	ModPrsL	Cable Present
9	ResetL	Cable Reset	28	IntL	Interrupt
10	Vcc Rx	+3.3V Power supply receiver	29	Vcc Tx	+3.3V Power supply transmitter
11	SCL	2-wire serial interface clock	30	Vcc1	+3.3V Power Supply
12	SDA	2-wire serial interface data	31	LPMode	Low Power Mode
13	Ground	Ground	32	Ground	Ground
14	Rx3p	Connected to Port 2 lane Tx1 Non-Inverted Data	33	Tx3p	Connected to Port 2 lane Rx1 Non-Inverted Data
15	Rx3n	Connected to Port 2 lane Tx1 Inverted Data	34	Tx3n	Connected to Port 2 lane Rx1 Inverted Data
16	Ground	Ground	35	Ground	Ground
17	Rx1p	Connected to Port 1 lane Tx1 Non-Inverted Data	36	Tx1p	Connected to Port 1 lane Rx1 Non-Inverted Data
18	Rx1n	Connected to Port 1 lane Tx1 Inverted Data	37	Tx1n	Connected to Port 1 lane Rx1 Inverted Data
19	Ground	Ground	38	Ground	Ground

QSFP56 Pin Description 100Gb/s End

Pin	Symbol	Description	Pin	Symbol	Description
1	Ground	Ground	20	Ground	Ground
2	Tx2n	Connected to lane Rx2 Inverted Data	21	Rx2n	Connected to lane Tx2 Inverted Data
3	Tx2p	Connected to lane Rx2 Non-Inverted Data	22	Rx2p	Connected to lane Tx2 Non-Inverted Data
4	Ground	Ground	23	Ground	Grounds
5	Not connected	Not connected	24	Not connected	Not connected
6	Not connected	Not connected	25	Not connected	Not connected
7	Ground	Ground	26	Ground	Ground
8	Mod-SelL	Cable Select	27	ModPrsL	Cable Present
9	ResetL	Cable Reset	28	IntL	Interrupt
10	Vcc Rx	+3.3V Power supply receiver	29	Vcc Tx	+3.3V Power supply transmitter
11	SCL	2-wire serial interface clock	30	Vcc1	+3.3V Power Supply
12	SDA	2-wire serial interface data	31	LPMode	Low Power Mode
13	Ground	Ground	32	Ground	Ground
14	Not connected	Not connected	33	Not connected	Not connected
15	Not connected	Not connected	34	Not connected	Not connected
16	Ground	Ground	35	Ground	Ground
17	Rx1p	Connected to lane Tx1 Non-Inverted Data	36	Tx1p	Connected to lane Rx1 Non-Inverted Data
18	Rx1n	Connected to lane Tx1 Inverted Data	37	Tx1n	Connected to lane Rx1 Inverted Data
19	Ground	Ground	38	Ground	Ground

QSFP56 Module Pad Layout

The pinout of the 100Gb/s ends of the cable is identical to the 200Gb/s end except that RF lanes 3 and 4 (pins 5, 6, 14, 15, 24, 25, 33, 34) are not used.

Control Signals

This transceiver is SFF-8636 compliant. This means that the control signals shown in the pad layout support the following functions:

Name	Function	Description
ModPrsL	Output, asserted low	Module Present pin, grounded inside the module. Terminated with pull-up in the host system. Asserted low when the transceiver is inserted, whereby the host detects the presence of the transceiver.
ModSelL	Input, asserted Low	Module Select input pin, terminated high in the module. Only when held low by the host, the module responds to 2-wire serial communication commands. The ModSelL enables multiple modules to share a single 2-wire interface bus.
ResetL	Input, asserted Low	Reset input pin, pulled high in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. During reset the host shall disregard all status bits until the module indicates completion of the reset interrupt by asserting IntL signal low with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module completes the reset interrupt without requiring a reset.
LPMode	Input, asserted high	Low Power Mode input, pulled up inside the module. The transceiver starts up in low-power mode, i.e. <1.5 W with the two-wire interface active. The host system can read the power class declaration from the transceiver and determine if it has enough power to enable the high-speed operation/high power mode of the transceiver. This can be done by asserting LPMode low or by use of the Power_over-ride and Power_set control bits (Address A0h, byte 93 bits 0,1).
IntL	Output, asserted low	Interrupt Low is an open-collector output, terminated high in the host system. A “Low” indicates a possible module operational fault or a status critical to the host system, e.g. temperature alarm. The host identifies the source of the interrupt using the 2-wire serial interface. The INTL pin is de-asserted “High” after completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of ‘0’.

The low-speed signals are Low Voltage TTL (LVTTL) compliant (except for SCL and SDA signals).

Diagnostics and Other Features

The transceiver complies with the SFF-8665 specification and has the following key features:

Physical layer link optimization:

Programmable Tx input equalization
Programmable Rx output amplitude
Programmable Rx output pre-emphasis
Tx/Rx CDR control
by default enabled for 100 GbE operation, disable it for 40G operation

Digital Diagnostic Monitoring (DDM):

Rx receive optical power monitor for each lane
Tx transmit optical power monitor for each lane
Tx bias current monitor for each lane
Supply voltage monitor
Transceiver case temperature monitor
Warning and Alarm thresholds for each DDM function (not user changeable)

Other SFF-8636 functions and interrupt indications:

Tx & Rx LOS indication
Tx & Rx LOL indication
Tx fault indication

LOS, LOL, and Tx Fault status flags can be read via the two-wire management interface and are jointly transmitted via the IntL output pin. Relevant advertisement, threshold, and readout registers are found in the SFF-8636 MSA.

On This Page

Pin Description

QSFP56 Pin Description 200Gb/s End

QSFP56 Module Pad Layout

QSFP56 Pin Description 100Gb/s End

QSFP56 Module Pad Layout

Control Signals

Diagnostics and Other Features