Abstract
This cuDNN 8.9.4 Developer Guide explains how to use the NVIDIA cuDNN library. While the NVIDIA cuDNN API Reference provides perfunction API documentation, the Developer Guide gives a more informal endtoend story about cuDNN’s key capabilities and how to use them.
NVIDIA^{®} CUDA^{®} Deep Neural Network LIbrary (cuDNN) is a GPUaccelerated library of primitives for deep neural networks. It provides highly tuned implementations of operations arising frequently in DNN applications:
Beyond just providing performant implementations of individual operations, the library also supports a flexible set of multioperation fusion patterns for further optimization. The goal is to achieve the best available performance on NVIDIA GPUs for important deep learning use cases.
In cuDNN version 7 and older, the API was designed to support a fixed set of operations and fusion patterns. We informally call this the “legacy API”. Starting in cuDNN version 8, to address the quickly expanding set of popular fusion patterns, we added a graph API, which allows the user to express a computation by defining an operation graph, rather than by selecting from a fixed set of API calls. This offers better flexibility versus the legacy API, and for most use cases, is the recommended way to use cuDNN.
Note that while the cuDNN library exposes a C API, we also provide an open source C++ layer which wraps the C API and is considered more convenient for most users. It is, however, limited to just the graph API, and does not support the legacy API.
Before we discuss the details of the graph and legacy APIs, this section introduces the key concepts that are common to both.
2.1. cuDNN Handle
The cuDNN library exposes a host API but assumes that for operations using the GPU, the necessary data is directly accessible from the device.
An application using cuDNN must initialize a handle to the library context by calling cudnnCreate()
. This handle is explicitly passed to every subsequent library function that operates on GPU data. Once the application finishes using cuDNN, it can release the resources associated with the library handle using cudnnDestroy()
. This approach allows the user to explicitly control the library's functioning when using multiple host threads, GPUs, and CUDA streams.
For example, an application can use cudaSetDevice
(prior to creating a cuDNN handle) to associate different devices with different host threads, and in each of those host threads, create a unique cuDNN handle that directs the subsequent library calls to the device associated with it. In this case, the cuDNN library calls made with different handles would automatically run on different devices.
The device associated with a particular cuDNN context is assumed to remain unchanged between the corresponding cudnnCreate()
and cudnnDestroy()
calls. In order for the cuDNN library to use a different device within the same host thread, the application must set the new device to be used by calling cudaSetDevice()
and then create another cuDNN context, which will be associated with the new device, by calling cudnnCreate()
.
2.2. Tensors and Layouts
Whether using the graph API or the legacy API, cuDNN operations take tensors as input and produce tensors as output.
2.2.1. Tensor Descriptor
The cuDNN library describes data with a generic nD tensor descriptor defined with the following parameters:
This tensor definition allows, for example, to have some dimensions overlapping each other within the same tensor by having the stride of one dimension smaller than the product of the dimension and the stride of the next dimension. In cuDNN, unless specified otherwise, all routines will support tensors with overlapping dimensions for forwardpass input tensors, however, dimensions of the output tensors cannot overlap. Even though this tensor format supports negative strides (which can be useful for data mirroring), cuDNN routines do not support tensors with negative strides unless specified otherwise.
2.2.1.1. WXYZ Tensor Descriptor
Tensor descriptor formats are identified using acronyms, with each letter referencing a corresponding dimension. In this document, the usage of this terminology implies:
 all the strides are strictly positive
 the dimensions referenced by the letters are sorted in decreasing order of their respective strides
2.2.1.2. 3D Tensor Descriptor
A 3D tensor is commonly used for matrix multiplications, with three letters: B, M, and N. B represents the batch size (for batch GEMM, set to 1 for single GEMM), M represents the number of rows, and N represents the number of columns. Refer to the CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR
operation for more information.
2.2.1.3. 4D Tensor Descriptor
A 4D tensor descriptor is used to define the format for batches of 2D images with 4 letters: N,C,H,W
for respectively the batch size, the number of feature maps, the height and the width. The letters are sorted in decreasing order of the strides. The commonly used 4D tensor formats are:
NCHW
NHWC
CHWN
2.2.1.4. 5D Tensor Descriptor
A 5D tensor descriptor is used to define the format of the batch of 3D images with 5 letters: N,C,D,H,W
for respectively the batch size, the number of feature maps, the depth, the height, and the width. The letters are sorted in decreasing order of the strides. The commonly used 5D tensor formats are called:
NCDHW
NDHWC
CDHWN
2.2.1.5. FullyPacked Tensors
A tensor is defined as XYZfullypacked
if, and only if:
 the number of tensor dimensions is equal to the number of letters preceding the
fullypacked
suffix  the stride of the ith dimension is equal to the product of the (i+1)th dimension by the (i+1)th stride
 the stride of the last dimension is 1
2.2.1.6. PartiallyPacked Tensors
The partially XYZpacked
terminology only applies in the context of a tensor format described with a superset of the letters used to define a partiallypacked tensor. A WXYZ
tensor is defined as XYZpacked
if, and only if:
 the strides of all dimensions NOT referenced in the
packed
suffix are greater or equal to the product of the next dimension by the next stride  the stride of each dimension referenced in the
packed
suffix in positioni
is equal to the product of the (i+1
)st dimension by the (i+1
)st stride  if the last tensor's dimension is present in the
packed
suffix, its stride is1
For example, an NHWC
tensor WCpacked means that the c_stride
is equal to 1 and w_stride
is equal to c_dim x c_stride
. In practice, the packed
suffix is usually applied to the minor dimensions of a tensor but can be applied to only the major dimensions; for example, an NCHW
tensor that is only Npacked.
2.2.1.7. Spatially Packed Tensors
Spatiallypacked tensors are defined as partiallypacked in spatial dimensions. For example, a spatiallypacked 4D tensor would mean that the tensor is either NCHW HWpacked or CNHW HWpacked.
2.2.1.8. Overlapping Tensors
A tensor is defined to be overlapping if iterating over a full range of dimensions produces the same address more than once. In practice an overlapped tensor will have stride[i1] < stride[i]*dim[i]
for some of the i
from [1,nbDims]
interval.
2.2.2. Data Layout Formats
This section describes how cuDNN tensors are arranged in memory according to several data layout formats.
The recommended way to specify the layout format of a tensor is by setting its strides accordingly. For compatibility with the v7 API, a subset of the layout formats can also be configured through the cudnnTensorFormat_t
enum. The enum is only supplied for legacy reasons and is deprecated.
2.2.2.1. Example Tensor
Consider a batch of images with the following dimensions:
 N is the batch size; 1
 C is the number of feature maps (that is,, number of channels); 64
 H is the image height; 5
 W is the image width; 4
To keep the example simple, the image pixel elements are expressed as a sequence of integers, 0, 1, 2, 3, and so on. Refer to Figure 1.
Figure 1. Example with N=1, C=64, H=5, W=4
In the following subsections, we’ll use the above example to demonstrate the different layout formats.
2.2.2.2. Convolution Layouts
cuDNN supports several layouts for convolution, as described in the following sections.
2.2.2.2.1. NCHW Memory Layout
The above 4D tensor is laid out in the memory in the NCHW format as below:
 Beginning with the first channel (c=0), the elements are arranged contiguously in rowmajor order.
 Continue with second and subsequent channels until the elements of all the channels are laid out. Refer to Figure 2.
 Proceed to the next batch (if N is > 1).
Figure 2. NCHW Memory Layout
2.2.2.2.2. NHWC Memory Layout
For the NHWC memory layout, the corresponding elements in all the C channels are laid out first, as below:
 Begin with the first element of channel 0, then proceed to the first element of channel 1, and so on, until the first elements of all the C channels are laid out.
 Next, select the second element of channel 0, then proceed to the second element of channel 1, and so on, until the second element of all the channels are laid out.
 Follow the rowmajor order of channel 0 and complete all the elements. Refer to Figure 3.
 Proceed to the next batch (if N is > 1).
Figure 3. NHWC Memory Layout
2.2.2.2.3. NC/32HW32 Memory Layout
The NC/32HW32 is similar to NHWC, with a key difference. For the NC/32HW32 memory layout, the 64 channels are grouped into two groups of 32 channels each  first group consisting of channels c0
through c31
, and the second group consisting of channels c32
through c63
. Then each group is laid out using the NHWC format. Refer to Figure 4.
Figure 4. NC/32HW32 Memory Layout
For the generalized NC/xHWx layout format, the following observations apply:
2.2.2.3. MatMul Layouts
As discussed in 3D Tensor Descriptor, matmul uses 3D tensors, described using BMN dimensions. The layout can be specified through the following strides. The following are two examples of recommended layouts:
 Packed Rowmajor: dim [B,M,N] with stride [MN, N, 1], or
 Packed Columnmajor: dim [B,M,N] with stride [MN, 1, M]
Unpacked layouts for 3D tensors are supported as well, but their support surface is more ragged.
2.3. Tensor Core Operations
The cuDNN v7 library introduced the acceleration of computeintensive routines using Tensor Core hardware on supported GPU SM versions. Tensor Core operations are supported beginning with the NVIDIA Volta GPU.
Tensor Core operations accelerate matrix math operations; cuDNN uses Tensor Core operations that accumulate into FP16, FP32, and INT32 values. Setting the math mode to CUDNN_TENSOR_OP_MATH
via the cudnnMathType_t
enumerator indicates that the library will use Tensor Core operations. This enumerator specifies the available options to enable the Tensor Core and should be applied on a perroutine basis.
The default math mode is CUDNN_DEFAULT_MATH
, which indicates that the Tensor Core operations will be avoided by the library. Because the CUDNN_TENSOR_OP_MATH
mode uses the Tensor Cores, it is possible that these two modes generate slightly different numerical results due to different sequencing of the floatingpoint operations.
For example, the result of multiplying two matrices using Tensor Core operations is very close, but not always identical, to the result achieved using a sequence of scalar floatingpoint operations. For this reason, the cuDNN library requires an explicit user optin before enabling the use of Tensor Core operations.
However, experiments with training common deep learning models show negligible differences between using Tensor Core operations and scalar floating point paths, as measured by both the final network accuracy and the iteration count to convergence. Consequently, the cuDNN library treats both modes of operation as functionally indistinguishable and allows for the scalar paths to serve as legitimate fallbacks for cases in which the use of Tensor Core operations is unsuitable. Kernels using Tensor Core operations are available for:
 Convolutions
 RNNs
 MultiHead Attention
For more information, refer to NVIDIA Training with Mixed Precision. For a deep learning compiler, the following are the key guidelines:
 Make sure that the convolution operation is eligible for Tensor Cores by avoiding any combinations of large padding and large filters.
 Transform the inputs and filters to NHWC, prepad channel and batch size to be a multiple of 8.
 Make sure that all userprovided tensors, workspace, and reserve space are aligned to 128bit boundaries. Note that 1024bit alignment may deliver better performance.
2.3.1. Notes on Tensor Core Precision
For FP16 data, Tensor Cores operate on FP16 input, output in FP16, and may accumulate in FP16 or FP32. The FP16 multiply leads to a fullprecision result that is accumulated in FP32 operations with the other products in a given dot product for a matrix with m x n x k
dimensions. Refer to Figure 5.
For an FP32 accumulation, with FP16 output, the output of the accumulator is downconverted to FP16. Generally, the accumulation type is of greater or equal precision to the output type.
Figure 5. Tensor operation with FP16 inputs. The accumulation is in FP32, which could be the input for other kernel features (for example, activation/bias, beta blending, etc). The final output in this example would be FP16.
The cuDNN library provides a declarative programming model for describing computation as a graph of operations. This graph API was introduced in cuDNN 8.0 to provide a more flexible API, especially with the growing importance of operation fusion.
The user starts by building a graph of operations. At a high level, the user is describing a dataflow graph of operations on tensors. Given a finalized graph, the user then selects and configures an engine that can execute that graph. There are several methods for selecting and configuring engines, which have tradeoffs with respect to easeofuse, runtime overhead, and engine performance. The graph API has two entry points:
 NVIDIA cuDNN Backend API (lowest level entry point into the graph API)
 NVIDIA cuDNN Frontend API (convenience layer on top of the C backend API)
We expect that most users prefer the cuDNN frontend API because:
 It is less verbose without loss of control  all functionality accessible through the backend API is also accessible through the frontend API.
 It adds functionality on top of the backend API, like errata filters and autotuning.
 It is open source.
In either case (that is, the backend or frontend API), the high level concepts are the same.
3.1. Key Concepts
As mentioned previously, the key concepts in the graph API are:
3.1.1. Operations and Operation Graphs
An operation graph is a dataflow graph of operations on tensors. It is meant to be a mathematical specification and is decoupled from the underlying engines that can implement it, as there may be more than one engine available for a given graph.
I/O tensors connect the operations implicitly, for example, an operation A may produce a tensor X, which is then consumed by operation B, implying that operation B depends on operation A.
3.1.2. Engines and Engine Configurations
For a given operation graph, there are some number of engines that are candidates for implementing that graph. The typical way to query for a list of candidate engines is through a heuristics query, covered below.
An engine has knobs for configuring properties of the engine, like tile size (refer to cudnnBackendKnobType_t
).
3.1.3. Heuristics
A heuristic is a way to get a list of engine configurations that are intended to be sorted from the most performant to least performant for the given operation graph. There are three modes:
 Intended to be fast and be able to handle most operation graph patterns. It returns a list of engine configs ranked by the expected performance.
 Intended to be more generally accurate than mode A, but with the tradeoff of higher CPU latency to return the list of engine configs. The underlying implementation may fall back to the mode A heuristic in cases where we know mode A can do better.
 Intended to be fast and provide functional fallbacks without expectation of optimal performance.
The recommended workflow is to query either mode A or B and check for support. The first engine config with support is expected to have the best performance.
You can “autotune”, that is, iterate over the list and time for each engine config and choose the best one for a particular problem on a particular device. The cuDNN frontend API provides a convenient function, cudnnFindPlan()
, which does this.
If all the engine configs are not supported, then use the mode fallback to find the functional fallbacks.
Expert users may also want to filter engine configs based on properties of the engine, such as numerical notes, behavior notes, or adjustable knobs. Numerical notes inform the user about the numerical properties of the engine such as whether it does datatype down conversion at the input or during output reduction. The behavior notes can signal something about the underlying implementation like whether or not it uses runtime compilation. The adjustable knobs allow fine grained control of the engine’s behavior and performance.
3.2. Graph API Example with Operation Fusion
The following example implements a fusion of convolution, bias, and activation.
3.2.1. Creating Operation and Tensor Descriptors to Specify the Graph Dataflow
First, create three cuDNN backend operation descriptors.
As can be seen in Figure 6, the user specified one forward convolution operation (using CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR
), a pointwise operation for the bias addition (using CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
with mode CUDNN_POINTWISE_ADD
), and a pointwise operation for the ReLU activation (using CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
with mode CUDNN_POINTWISE_RELU_FWD
). Refer to the NVIDIA cuDNN Backend API for more details on setting the attributes of these descriptors. For an example of how a forward convolution can be set up, refer to the Setting Up An Operation Graph For A Grouped Convolution use case in the cuDNN backend API.
You should also create tensor descriptors for the inputs and outputs of all of the operations in the graph. The graph dataflow is implied by the assignment of tensors (refer to Figure 6), for example, by specifying the backend tensor Tmp0 as both the output of the convolution operation and the input of the bias operation, cuDNN infers that the dataflow runs from the convolution into the bias. The same applies to tensor Tmp1. If the user doesn’t need the intermediate results Tmp0 and Tmp1 for any other use, then the user can specify them to be virtual tensors, so the memory I/Os can later be optimized out.
 Note that graphs with more than one operation node do not support inplace operations (that is, where any of the input UIDs matches any of the output UIDs). Such inplace operations are considered cyclic in later graph analysis and deemed unsupported. Inplace operations are supported for singlenode graphs.
 Also note that the operation descriptors can be created and passed into cuDNN in any order, as the tensor UIDs are enough to determine the dependencies in the graph.
Figure 6. A set of operation descriptors the user passes to the operation graph
3.2.2. Finalizing The Operation Graph
Second, the user finalizes the operation graph. As part of finalization, cuDNN performs the dataflow analysis to establish the dependency relationship between operations and connect the edges, as illustrated in the following figure. In this step, cuDNN performs various checks to confirm the validity of the graph.
Figure 7. The operation graph after finalization
3.2.3. Configuring An Engine That Can Execute The Operation Graph
Third, given the finalized operation graph, the user must select and configure an engine to execute that graph, which results in an execution plan. As mentioned in Heuristics, the typical way to do this is:
3.2.4. Executing The Engine
Finally, with the execution plan constructed and when it comes time to run it, the user should construct the backend variant pack by providing the workspace pointer, an array of UIDs, and an array of device pointers. The UIDs and the pointers should be in the corresponding order. With the handle, the execution plan and variant pack, the execution API can be called and the computation is carried out on the GPU.
3.3. Supported Graph Patterns
The cuDNN Graph API supports a set of graph patterns. These patterns are supported by a large number of engines, each with their own support surfaces. These engines are grouped into four different classes, as reflected by the following four subsections: precompiled single operation engines, generic runtime fusion engines, specialized runtime fusion engines, and specialized precompiled fusion engines. The specialized engines, whether they use runtime compilation or precompilation, are targeted to a set of important use cases, and thus have a fairly limited set of patterns they currently support. Over time, we expect to support more of those use cases with the generic runtime fusion engines, whenever practical.
Since these engines have some overlap in the patterns they support, a given pattern may result in zero, one, or more engines.
3.3.1. Precompiled Single Operation Engines
One basic class of engines includes precompiled engines that support an operation graph with just one operation; specifically: ConvolutionFwd
, ConvolutionBwFilter
, ConvolutionBwData
, or ConvolutionBwBias
. Their more precise support surface can be found in the NVIDIA cuDNN API Reference.
3.3.1.1. ConvolutionFwd
ConvolutionFwd
computes the convolution of X with filter data W. In addition, it uses scaling factors
cudnnConvolutionForward()
.
Figure 8. ConvolutionFwd
Engine
3.3.1.2. ConvolutionBwFilter
ConvolutionBwFilter
computes the convolution filter gradient of the tensor dy. In addition, it uses scaling factors
cudnnConvolutionBackwardFilter()
.
Figure 9. ConvolutionBwFilter
Engine
3.3.1.3. ConvolutionBwData
ConvolutionBwData
computes the convolution data gradient of the tensor dy. In addition, it uses scaling factors
cudnnConvolutionBackwardData()
.
Figure 10. ConvolutionBwData
Engine
3.3.1.4. NormalizationForward
NormalizationForward
computes the normalization output Y
from the input X
. This operation is used in both the inference and training phase. The phases are distinguished by the attribute CUDNN_ATTR_OPERATION_NORM_FWD_PHASE
.
Figure 11. NormalizationForward
Engine
This operation supports different normalization modes which are set by the attribute CUDNN_ATTR_OPERATION_NORM_FWD_MODE
. The dashed lines indicate optional inputs, which are typically used in the batch norm mode of this operation. Currently, the precompiled engines support instance and layer norm while batch norm is supported using a specialized runtime compiled engine (refer to BnAddRelu).
Node and Other Attributes  Instance Normalization Forward  Layer Normalization Forward 

name 
instance 
layer 
operation 
normFwd 
normFwd 
X 
[N, C, (D), H, W], input, I/O type  [N, C, (D), H, W], input, I/O type 
Mean 
[N,C,(1),1,1], output, compute type, only applicable to fmode CUDNN_NORM_FWD_TRAINING 
[N,1,(1),1,1], output, compute type, only applicable to fmode CUDNN_NORM_FWD_TRAINING 
InvVariance 
[N,C,(1),1,1], output, compute type, only applicable to fmode CUDNN_NORM_FWD_TRAINING 
[N,1,(1),1,1], output, compute type, only applicable to fmode CUDNN_NORM_FWD_TRAINING 
Scale 
[1,C,(1),1,1], input, compute type  [1,C,(D),H,W], input, compute type 
Bias 
[1,C,(1),1,1], input, compute type  [1,C,(D),H,W], input, compute type 
Y 
[N, C, (D), H, W], output, I/O type  [N, C, (D), H, W], output, I/O type 
epsilonDesc 
[1,1,1,1], input, constant  [1,1,1,1], input, constant 
mode 
CUDNN_INSTANCE_NORM 
CUDNN_LAYER_NORM 
Supported fmode 
CUDNN_NORM_FWD_TRAINING , CUDNN_NORM_FWD_INFERENCE 
CUDNN_NORM_FWD_TRAINING , CUDNN_NORM_FWD_INFERENCE 
Supported layout  NC(D)HW, N(D)HWC  NC(D)HW, N(D)HWC 
Supported I/O types  FP16, FP32  FP16, FP32 
Supported compute type  FP32  FP32 
Alignment requirements for I/O type  8 bytes aligned  16 bytes aligned 
For each operation, all applicable tensors must have the same layout. Neither mixed I/O types, nor mixed compute types are supported.
3.3.1.5. NormalizationBackward
NormalizationBackward
computes the gradient dX
and the scale and bias gradients dScale
and dBias
. This operation supports multiple modes which are set by the attribute CUDNN_ATTR_OPERATION_NORM_BWD_MODE
. The precompiled engines support instance and layer norm backward while batch norm backward is supported by a specialized runtime compiled engine (refer to DReluForkDBn). The mean and variance saved during the forward training pass is passed as input to theNormBackward
operation.
Figure 12. NormalizationBackward
Engine
Node and Other Attributes  Instance Normalization Backward  Layer Normalization Backward 

name 
instance 
layer 
operation 
normBwd 
normBwd 
X 
[N, C, (D), H, W], input, I/O type  [N, C, (D), H, W], input, I/O type 
Mean 
[N,C,(1),1,1], input, compute type  [N,1,(1),1,1], input, compute type 
InvVariance 
[N,C,(1),1,1], input, compute type  [N,1,(1),1,1], input, compute type 
Scale 
[1,C,(1),1,1], input, compute type  [1,C,(D),H,W], input, compute type 
DY 
[N, C, (D), H, W], input, I/O type  [N, C, (D), H, W], input, I/O type 
DX 
[N, C, (D), H, W], output, I/O type  [N, C, (D), H, W], output, I/O type 
Dscale 
[1,C,(1),1,1], output, compute type  [1,C,(D),H,W], output, compute type 
Dbias 
[1,C,(1),1,1], output, compute type  [1,C,(D),H,W], output, compute type 
mode 
CUDNN_INSTANCE_NORM 
CUDNN_LAYER_NORM 
Supported layout  NC(D)HW, N(D)HWC  NC(D)HW, N(D)HWC 
Supported I/O types  FP16, FP32  FP16, FP32 
Supported compute type  FP32  FP32 
Alignment requirements for I/O type  8 bytes aligned  16 bytes aligned 
For each operation, all applicable tensors must have the same layout. Neither mixed I/O types, nor mixed compute types are supported.
3.3.2. Generic Runtime Fusion Engines
The engines documented in the previous section support singleop patterns. Of course, for fusion to be interesting, the graph needs to support multiple operations. And ideally, we want the supported patterns to be flexible to cover a diverse set of use cases. To accomplish this generality, cuDNN has runtime fusion engines that generate the kernel (or kernels) at runtime based on the graph pattern. This section outlines the patterns supported by these runtime fusion engines (that is, engines with CUDNN_BEHAVIOR_NOTE_RUNTIME_COMPILATION
behavioral note).
We can think of the support surface as covering the follwing generic patterns:
Figure 13. Graphical Representation of the Generic Patterns Supported by the Runtime Fusion Engines
g_{1} is a directed acyclic graph (DAG) that can consist of zero or any number of the following operation:
CUDNN_BACKEND_OPERATION_CONCAT_DESCRIPTOR
CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
g_{2} is a DAG that can consist of zero or any number of the following operations:
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR
CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR
CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR
CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR
CUDNN_BACKEND_OPERATION_SIGNAL_DESCRIPTOR
3.3.2.1. Limitations
While the generic patterns listed previously are widely applicable, there are some cases where we do not have full support.
Limitations Common to all Generic Patterns
Limitations per Generic Pattern
Tensor Layout Requirements
Lastly, there are some layout requirements to the I/O tensors involved in fusion graphs. For more information, refer to the Tensor Descriptor and Data Layout Formats sections. The following table describes the requirements per fusion pattern:
3.3.2.2. Examples of Supported Patterns
The following sections provide examples of supported patterns, in order of increasing complexity. We employ the same color scheme as in the overall pattern to aid in identifying the structure of g_{1} (blue) and g_{2} (purple).
For illustration purposes, we abbreviated the operations used. For a full mapping to the actual backend descriptors, refer to the Mapping with Backend Descriptors.
3.3.2.2.1. Single Operation
The following example illustrates a convolution operation without any operations before or after it. This means, g_{1} and g_{2}, are empty graphs.
Figure 14. This example illustrates the Runtime Fusion Engines with a Single Operation
3.3.2.2.2. Pointwise Operations After Convolution 1
In this example, g_{2} consists of a sequential set of two pointwise operations after the convolution.
Figure 15. ConvolutionFwd
Followed by a DAG with Two Operations
3.3.2.2.3. Pointwise Operations After Convolution 2
Similar to the previous example, g_{2} consists of a sequential set of multiple pointwise operations.
Figure 16. ConvolutionFwd
Followed by a DAG with Three Operations
3.3.2.2.4. Pointwise Operations Before Matrix Multiplication
Pointwise operations can also precede a convolution or matrix multiplication, that is, g_{1} is composed of pointwise operations.
Figure 17. MatMul Preceded by a DAG with Two Operations
3.3.2.2.5. Convolution Producer Node in Middle of DAG
The following pattern shows g_{1} as a DAG of pointwise operations feeding into a convolution. In addition, g_{2} is a DAG consisting of two pointwise operations. Note that the convolution is being consumed in the middle of g_{2} as opposed to g_{2}’s first node. This is a valid pattern.
Figure 18. This example illustrates fusion of operations before and after the ConvolutionFwd
operation. In addition we observe that the output of ConvolutionFwd
can feed anywhere in g_{2}.
3.3.2.3. Operation specific Constraints for the Runtime Fusion Engines
Every operation in the supported generic patterns of the runtime fusion engines is subject to a few specific constraints regarding their parameter surface. The following subsections document these.
Note that these constraints are in addition to (1) any constraints mentioned in the NVIDIA cuDNN Backend API, and (2) limitations in relation to other operations in the directed acyclic graph (DAG), as mentioned in the Limitations section.
3.3.2.3.1. Convolutions
There are three operation nodes that represent different types of convolutions namely:

ConvolutionFwd

This operation represents forward convolution, that is, computing the response tensor of image tensor convoluted with filter tensor. For complete details on the interface, as well as general constraints, refer to the
CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR
section. 
ConvolutionBwFilter

This operation represents convolution backward filters, that is, computing filter gradients from a response and an image tensor. For complete details on the interface, as well as general constraints, refer to the
CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR
section. 
ConvolutionBwData

This operation represents convolution backward data, that is, computing input data gradients from a response and a filter tensor. For complete details on the interface, as well as general constraints, refer to the
CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR
section.
Input Tensor Attribute Name  Output Tensor Attribute Name  

ConvolutionFwd 

CUDNN_ATTR_OPERATION_CONVOLUTION_FORWARD_Y 
ConvolutionBwFilter 

CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_DATA_W 
ConvolutionBwData 

CUDNN_ATTR_OPERATION_CONVOLUTION_BWD_FILTER_X 
The following tables list the constraints for all three operations, in addition to any constraints mentioned in the NVIDIA cuDNN Backend API, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when these operations are used in the runtime fusion engines.
Tensor Data Type  Number of input and output channels for NVIDIA Hopper Architecture  Number of input and output channels for NVIDIA Ampere and Ada Lovelace  Number of input and output channels for NVIDIA Volta/Turing Architecture 

INT8 
Multiple of 4  Multiple of 4  Multiple of 16 
FP8 
Multiple of 16  N/A  N/A 
FP16/BF16 
Multiple of 2  Multiple of 2  Multiple of 8 
FP32(TF32) 
Any value  Any value  Multiple of 4 
Lastly, there are some batch size requirements per operation:
Operation  Batch size for FP8 data type on NVIDIA Hopper Architecture  Batch size for other data types 

ConvolutionFwd 
Any  Any 
ConvolutionBwFilter 
Multiple of 16  Any 
ConvolutionBwData 
Multiple of 16  Any 
The FP8 data type since Hopper architecture has two variants: CUDNN_DATA_FP8_E4M3
and CUDNN_DATA_FP8_E5M2
as I/O data types. Using them as inputs to the operation will result in FP8 Tensor Cores being used. The precision of the accumulation inside the FP8 Tensor Cores is controlled by the compute type, which may have one of two possible values: CUDNN_DATA_FLOAT
and CUDNN_DATA_FAST_FLOAT_FOR_FP8
.
CUDNN_DATA_FAST_FLOAT_FOR_FP8
is faster and sufficiently accurate for inference or the forward pass of training. However, for FP8 training backward pass computations (that is, computing weight and activation gradients), we recommend choosing the more accurate CUDNN_DATA_FLOAT
compute type to preserve a higher level of accuracy which may be necessary for some models.
3.3.2.3.2. MatMul
This operation represents matrixmatrix multiplication: A * B = C. For complete details on the interface, refer to the CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR
section.
The following two tables list the constraints for MatMul operations, in addition to any general constraints as listed in the NVIDIA cuDNN Backend API, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when MatMul is used in the runtime fusion engines. Besides the layouts of operand A, B, and C, there must be row major, column major, and row major, respectively, for the INT8 tensor data type.
Attribute  Support 

CUDNN_ATTR_MATMUL_COMP_TYPE 
CUDNN_DATA_HALF ,CUDNN_DATA_INT32 , and CUDNN_DATA_FLOAT 
Tensor Data Type  Number of input and output channels for NVIDIA Hopper architecture  Innermost dimension for NVIDIA Ampere architecture and NVIDIA Ada Lovelace  Innermost dimension for NVIDIA Volta and NVIDIA Turing architecture 

INT8 
Multiple of 4  Multiple of 4  Multiple of 16 
FP8 
Multiple of 16  N/A  N/A 
FP16/BF16 
Multiple of 2  Multiple of 2  Multiple of 8 
FP32(TF32) 
Any value  Any value  Multiple of 4 
3.3.2.3.3. Pointwise
Represents a pointwise operation that implements the equation Y = op (alpha1 * X)
or Y = op (alpha1 * X, alpha2 * B)
. Refer to the CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
and CUDNN_BACKEND_POINTWISE_DESCRIPTOR
sections for more information and general constraints.
The following table lists the constraints for pointwise operations, in addition to the general constraints listed above, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when these operations are used in the runtime fusion engines.
3.3.2.3.4. GenStats
Represents an operation that generates perchannel statistics. Refer to the CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR
section for more information and general constraints.
The following table lists the constraints for GenStats operations, in addition to the general constraints listed above, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when GenStats operations are used in the runtime fusion engines.
3.3.2.3.5. Reduction
This operation represents reducing values of a tensor in one or more dimensions. Refer to the CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR
section for more information and general constraints.
The following two tables are constraints for Reduction forward operations, in addition to the general constraints listed above, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when Reduction operations are used in the runtime fusion engines.
Attribute  Requirement 

Tensor data type for CUDNN_ATTR_OPERATION_REDUCTION_YDESC 
CUDNN_DATA_FLOAT 
CUDNN_ATTR_REDUCTION_COMP_TYPE 
CUDNN_DATA_FLOAT 
Tensor layout for CUDNN_ATTR_OPERATION_REDUCTION_XDESC and CUDNN_ATTR_OPERATION_REDUCTION_YDESC 
NHWC/NDHWC/BMN fully packed 
CUDNN_ATTR_REDUCTION_OPERATOR 
CUDNN_REDUCE_TENSOR_ADD , CUDNN_REDUCE_TENSOR_MIN , and CUDNN_REDUCE_TENSOR_MAX 
Reduction Operation  Reduction Pattern  

Input  Output  
Standalone reduction operation  [N, C, H, W]  [N, 1, H, W] 
[1, C, 1, 1]  
[1, 1, 1, 1]  
Reduction fused after convolution fprop 
[N, K, P, Q]  [N, 1, P, Q] 
[1, K, 1, 1]  
[1, 1, 1, 1]  
Reduction fused after convolution backward data gradient  [N, C, H, W]  [N, 1, H, W] 
[1, C, 1, 1]  
[1, 1, 1, 1]  
Reduction fused after convolution backward filter gradient  [K, C, R, S]  [K, 1, 1, 1] 
[1, C, R, S]  
[1, 1, 1, 1]  
Reduction fused after matrix multiplication operation  [B, M, N]  [B, M, 1] 
[B, 1, N] 
3.3.2.3.6. ResampleFwd
This operation represents resampling of the spatial dimensions of an image to a desired value. Resampling is supported in both directions, upsampling and downsampling. Downsampling represents the standard operation of pooling, commonly used in convolutional neural networks. Refer to the CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR
section for more information and general constraints.
The following are constraints for Resample operations, in addition to the general constraints listed above, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when Resample forward operations are used in the runtime fusion engines. We allow a choice amongst four modes for resample. All modes have the following common support specifications:
 Supported layout: NHWC or NDHWC, NCHW or NCDHW
 Spatial dimensions supported: 2 or 3
 Input dimensions supported: 4 or 5
 Packed boolean data type is not supported.
 If specified, the index tensor dimension should be equal to the response tensor dimension.
When the tensor format is NCHW/NCDHW, the following additional restrictions apply:
 Upsampling is not supported.
Int64_t
indices are not supported. Only supports symmetric padding using the prepadding backend API.
There are some mode specific restrictions also. The following tables list the values that are allowed for particular parameters. For the parameters not listed, we allow any value which is mathematically correct. The following downsampling modes are supported:
CUDNN_RESAMPLE_AVGPOOL_INCLUDE_PADDING
CUDNN_RESAMPLE_AVGPOOL_EXCLUDE_PADDING
CUDNN_RESAMPLE_MAXPOOL
Attribute  Average Pooling  Max Pooling 

CUDNN_ATTR_RESAMPLE_PADDING_MODE 
CUDNN_ZERO_PAD 
CUDNN_NEG_INF_PAD 
CUDNN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA 
1.0 
1.0 
CUDNN_ATTR_OPERATION_RESAMPLE_FWD_BETA 
0.0 
0.0 
CUDNN_ATTR_RESAMPLE_COMP_TYPE 
CUDNN_DATA_FLOAT 
CUDNN_DATA_FLOAT 
For the upsampling modes, CUDNN_RESAMPLE_NEAREST
is not supported for any combination of parameters. CUDNN_RESAMPLE_BILINEAR
has the following support specifications.
Attribute  Bilinear 

Input dimensions  Equal to 0.5 x output dimensions 
CUDNN_ATTR_RESAMPLE_PRE_PADDINGS 
0.5 
CUDNN_ATTR_RESAMPLE_POST_PADDINGS 
1 
CUDNN_ATTR_RESAMPLE_STRIDES 
0.5 
CUDNN_ATTR_RESAMPLE_WINDOW_DIMS 
2 
Data type for CUDNN_ATTR_OPERATION_RESAMPLE_FWD_XDESC and CUDNN_ATTR_OPERATION_RESAMPLE_FWD_YDESC 
CUDNN_DATA_FLOAT 
CUDNN_ATTR_RESAMPLE_COMP_TYPE 
CUDNN_DATA_FLOAT 
CUDNN_ATTR_OPERATION_RESAMPLE_FWD_ALPHA 
1.0 
CUDNN_ATTR_OPERATION_RESAMPLE_FWD_BETA 
0.0 
CUDNN_ATTR_RESAMPLE_PADDING_MODE 
CUDNN_EDGE_VAL_PAD 
3.3.2.3.6.1. Resampling Index Tensor Dump for Training
For maxpooling resampling mode, an index tensor can be provided to be used as a mask for backpropagation.
Values in the index tensors are:
 Zeroindexed rowmajor position of maximum value of input tensor in the resampling window.
 In case of multiple input pixels with maximum value, the first index in a lefttoright toptobottom scan is selected.
Example of index element selection:
Figure 19. Values In the Index Tensors
Select an appropriate element size for the index tensor. As a reference, any element size such that the maximum zeroindexed window position fits should be sufficient.
3.3.2.3.7. ResampleBwd
This operation represents backward resampling of the spatial dimensions of an output response to a desired value. Resampling is supported in both directions, upsampling and downsampling. Backwards downsampling represents the standard operation of backward pooling, commonly used in convolutional neural networks. Refer to the CUDNN_BACKEND_OPERATION_RESAMPLE_BWD_DESCRIPTOR
section for more information and general constraints.
The following are constraints for Resample backward operations, in addition to the general constraints listed above, and any constraints listed in the Limitations section, in relation to other operations. Note that these additional constraints only apply when Resample backward operations are used in the runtime fusion engines. We allow a choice amongst four modes for resample. All modes have the following common support specifications:
 Supported layout: NHWC or NDHWC, NCHW or NCDHW
 Spatial dimensions supported: 2 or 3
 Input dimensions supported: 4 or 5
 The index tensor should be provided for only max pooling mode, and should adhere to the format described in the resampling forward index dump section.
 The index tensor dimensions should be equal to the input gradient tensor dimensions.
 X, Y, and DY are required when max pooling mode is used.
Int64_t
indices are not supported.
There are some mode specific restrictions also. The following tables list the values that are allowed for particular parameters. For the parameters not listed, we allow any value which is mathematically correct. The following backward downsampling modes are supported:
CUDNN_RESAMPLE_AVGPOOL_INCLUDE_PADDING
CUDNN_RESAMPLE_AVGPOOL_EXCLUDE_PADDING
CUDNN_RESAMPLE_MAXPOOL
Attribute  Average Pooling  Max Pooling 

CUDNN_ATTR_RESAMPLE_PADDING_MODE 
CUDNN_ZERO_PAD 
CUDNN_NEG_INF_PAD 
CUDNN_ATTR_OPERATION_RESAMPLE_BWD_ALPHA 
1.0 
1.0 
CUDNN_ATTR_OPERATION_RESAMPLE_BWD_BETA 
0.0 
0.0 
CUDNN_ATTR_RESAMPLE_COMP_TYPE 
CUDNN_DATA_FLOAT 
CUDNN_DATA_FLOAT 
Backward upsampling modes are currently not supported.
3.3.3. Specialized Runtime Fusion Engines
The specialized runtime fusion engines target and optimize specialized graph patterns that commonly occur in popular deep learning models. These engines offer limited flexibility regarding supported fusion patterns, supported data types, and supported tensor layouts. Long term, these patterns are expected to be more generic.
The following sections highlight the supported patterns.
3.3.3.1. BnAddRelu
In ResNetlike vision models, batch normalization followed by ReLU activation is a commonly occurring pattern. The BNAddRelu
fusion pattern, supported using a runtime compiled engine, aims to optimize this recurring operation graph. It also supports single node multiGPU batch normalization for speeding up batch norm computation in multiGPU systems. The pattern is intended for use in the forward pass during the training phase. The full pattern BNAddRelu
with the add node is used in cases where there are skip connections in the model.
The pattern is illustrated in the following diagram and its options and limitations include:
Figure 20. BnAddRelu
cuDNN Operation Graph
In case of single node multiGPU batch norm, each GPU computes the local statistics based on its input data and writes out the local statistics to the peerTensors
. Each peerTensor
resides on a separate GPU on the node and is used for reading and writing local statistics from the peer GPUs. This is followed by a global stats computation phase where each GPU aggregates the statistics from the peers and computes the global mean and variance for the batch norm output computation on its local data. Apart from the options and limitations listed above, the following additional restrictions apply for using multiGPU batch norm:
Figure 21. Single Node MultiGPU Batch Norm
3.3.3.2. DReluForkDBn
Similar to the BnAddRelu
pattern, the DReluForkDBn
pattern also targets ResNetlike vision networks. It is intended to be used in backpropagation during the training phase. The DReluForkDBn
pattern is supported through a runtime compiled engine that usually complements the BnAddRelu
pattern. It also supports single node multiGPU batch normalization for speeding up batch norm backward computation in multiGPU systems.
The pattern is illustrated in the following diagram and its options and limitations include:
Figure 22. DReluForkDBn
cuDNN Operation Graph
The single node multiGPU version of this pattern is typically used for dScale
and dBias
gradient aggregation across GPUs. For using the multiGPU version, the attribute CUDNN_ATTR_OPERATION_NORM_BWD_PEER_STAT_DESCS
of the NormBackward
operation must be set. Other restrictions for the peerTensors
vector listed in the previous section apply for this pattern as well.
3.3.3.3. Fused Attention fprop
MhaFprop
fusions
There are two key differences to the flash fused attention patterns described in later sections:
 Input sizes supported contain small sequence lengths (<= 512).
 The operation graph is flexible to switch between different types of masks, different operations between the two matrix multiplications, and so on.
Figure 23. Mhafprop
cuDNN Operation Graph
g_{3} can be an empty graph or a single scale operation with the scale being a scalar value (CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR
with mode CUDNN_POINTWISE_MUL
).
g_{4} can be empty or the combination of the following DAGs of cuDNN operations. Each of these DAGs is optional, as shown by the dotted line.
Figure 24. DAGs of cuDNN operations
The combination has to obey the order in which we present them. For example, if you want to use the padding mask and softmax, the padding mask has to appear before softmax.
These operations are commonly used in attention. In the following diagram, we depict how to create a DAG for each of the operations. In later versions, we will be expanding the possible DAGs for g_{3} and g_{4}.
Padding Mask
Figure 25. cuDNN graph depicting DAG:Padding Mask
Causal Mask
Figure 26. cuDNN graph depicting DAG:Causal Mask
Softmax
Figure 27. cuDNN graph depicting DAG:Softmax
Dropout
Figure 28. cuDNN graph depicting DAG:Dropout
g_{4} is capable of storing an intermediate tensor to global memory marked as S
, which can be used for fused multihead attention bprop
. Both DAG:Softmax
and DAG:Dropout
have this capability. Set S
as the output from the last DAG in the graph.
The tensor descriptor marked as S
must have the CUDNN_ATTR_TENSOR_REORDERING_MODE
set to CUDNN_TENSOR_REORDERING_F16x16
. This is because the tensor is stored in a special format and can only be consumed by fused attention bprop
.
There is an additional option of generating the mask on the user end and passing it directly to the pointwise multiply. The mask needs to be of I/O data type FP16/BF16 and S
will store the mask in the sign bit to communicate to bprop
.
Layout requirements of Mhafprop
fusions include:
3.3.3.4. Fused Attention bprop
MhaBprop
fusions are executed in a fused pattern in a single kernel.
$\text{dV}\text{}=\text{}\text{matmul}\text{}\left({\text{g}}_{\text{5}}\text{}\left(\text{S}\right)\text{,}\text{}\text{dO}\right)$
$\text{dS}\text{}=\text{}\text{matmul}\text{}\left(\text{dO}\text{,}\text{}{V}^{T}\right)$
$\text{dQ}\text{}=\text{}\text{matmul}\text{}\left({\text{g}}_{\text{6}}\text{}\left(\text{dS}\right)\text{,}\text{}\text{K}\right)$
$\text{dK}\text{}=\text{}\text{matmul}\text{}\left(\text{Q}\text{,}\text{}{\text{g}}_{\text{7}}\text{}\left(\text{dS}\right)\right)$
cuDNN supports the corresponding backpropagation graph for fused attention. This can be used together with the fused attention fprop
graph to perform training on models that have similar architectures to BERT and T5. This is not compatible with the flash fused attention bprop
operation graph.
Figure 29. Mhabprop
cuDNN Operation Graph
g_{5}, g_{6}, and g_{7} can only support a fixed DAG. We are working towards generalizing these graphs.
Figure 30. cuDNN Graph Depicting g_{5}
g_{6} represents the backward pass of softmax and masking, to get dP
.
Figure 31. cuDNN Graph Depicting g_{6}
There are options for the Mask DAG that you can optin. You can either use the padding/causal mask, general mask as an input, or not do any masking.
Figure 32. cuDNN Graph Depicting Mask DAG
dBias
DAG is useful to calculate the bprop
of the relative positional encoding and is optional and available for you to optin.
Figure 33. cuDNN Graph Depicting dBias
DAG
g_{7} is the transpose of dP
the output of g_{6}.
Figure 34. cuDNN Graph Depicting g_{7}
Layout requirements of Mhabprop
fusions include:
3.3.3.5. Fused Flash Attention fprop
cuDNN supports flash fused to perform scale dot product attention commonly used in models like GPT, BERT, and so on. Currently, support is limited to the following graph depicting forward propagation and inference with limitations on the support size and data types. Support will be expanded in future versions. The graph supports a pattern of BMMScaleCausal MaskSoftmaxDropoutMatmul.
Figure 35. Flash fprop
cuDNN Operation Graph
The compound operations for example: Causal Mask, Softmax, and so on, can be represented using the following operation graphs in cuDNN.
Figure 36. Flash fprop
Causal Mask Operation Graph
Figure 37. Flash fprop
Softmax Operation Graph
Figure 38. Flash fprop
Dropout Operation Graph
Inference mode can be turned on by passing the Softmax
stats as a virtual tensor and setting the RNG node probability to 0.0f
. Currently, the pattern is only supported on A100 and H100 GPUs.
3.3.3.6. Fused Flash Attention bprop
cuDNN supports the corresponding backpropagation graph for fused flash attention. This can be used together with the fprop
graph to perform training on Large Language Models (LLMs).
For the input and output tensors, the limitations from the fprop
graph are carried over. For the bprop
specific tensors, the limitations are as follows:
Figure 39. Flash bprop
cuDNN Operation Graph
Currently, the pattern is only supported on A100 and H100 GPUs.
3.3.4. Specialized PreCompiled Engines
The precompiled specialized engines target and optimize for a specialized graph pattern with a ragged support surface. Because of this targeting, these graphs do not require runtime compilation.
In most cases, the specialized patterns are just special cases of the generic patterns used in the runtime fusion engines, but there are some cases where the specialized pattern does not fit any of the generic patterns. If your graph pattern matches a specialized pattern, you will get at least a pattern matching engine, and you might also get runtime fusion engines as another option.
Currently, the following patterns are supported by the pattern matching engines. Some nodes are optional. Optional nodes are indicated by dashed outlines.
3.3.4.1. ConvBNfprop
In Figure 40, the ConvBNfprop
pattern is illustrated. Its restrictions and options include:
Figure 40. ConvBNfprop
, A PreCompiled Engine, Fuses ConvolutionFwd
and GenStats
With Several Pointwise Operations
Skip connections are commonly observed in ResNetlike models. To support fusions in skip connections, we support a variant of the pattern above, the DBARCS pattern (short for Dual, Scale, Bias, Add, ReLU, Conv genStats). The limitations and options of the DBARCS pattern include:
Figure 41. DBARCS In The convBNfprop
Series For Supporting Fusions Across Skip Connections
3.3.4.2. ConvBNwgrad
In Figure 42, the ConvBNwgrad
pattern is illustrated. Its restrictions and options include:
Figure 42. ConvBNwgrad
, A PreCompiled Engine, Fuses ConvolutionBwFilter
With Several (Optional) Pointwise Operations
3.3.4.3. ConvBiasAct
In the following figure, the ConvBiasAct
pattern is illustrated. Its restrictions and options include:
Figure 43. ConvBiasAct
, A PreCompiled Engine, Fuses ConvolutionFwd
With Several Pointwise Operations
3.3.4.4. ConvScaleBiasAct
In the following figure, the ConvScaleBiasAct
pattern is illustrated. Its restrictions and options include:
Figure 44. ConvScaleBiasAct
, A PreCompiled Engine
This pattern is very similar as ConvBiasAct
. The difference is that here, the scales
${\alpha}_{\text{1}}$ and
${\alpha}_{\text{2}}$ are tensors, not scalars. If they are scalars, this pattern becomes a normal ConvBiasAct
.
3.3.4.5. DgradDreluBNBwdWeight
In Figure 45, the DgradDreluBNBwdWeight
pattern is illustrated. Its restrictions and options include:
DgradDreluBNBwdWeight
is a precompiled engine that can be used in conjunction with the dBNApply
pattern to compute the backwards path of batch norm.
Figure 45. DgradDreluBNBwdWeight
Pattern For Fusions In The Backward Pass
The BNBwdWeight
operation takes in five inputs: X_bn
, mean_bn
, invstddev_bn
, scale_bn
, and dy_bn
(that is, the output from the ReLUBwd
node).
It produces five outputs: gradients of the batch norm scale and bias params, dScale
, dBias
, and coefficients A,B,C. Note that for illustration purposes, the inputs are duplicated. The inputs on the left and right are however exactly the same.
This pattern is typically used in the computation of the Batch Norm Backward Pass.
When computing the backward pass of batch norm, dScale
, dBias
, and dX_bn
are needed. The DgradDreluBnBwdWeight
pattern computes the former two. Using the generated A, B, and C we can use the following dBNApply
pattern to compute dX
, the input gradient, as follows dx_bn = A*dy_bn + B*X_bn +C
.
Figure 46. dBNApply
Pattern For Final Gradient Computation
The dBNApply
pattern was initially supported by a precompiled static engine but is now supported by the generic runtime fusion engine.
Note that the DgradDreluBNBwdWeight
pattern is used in combination with the forward pass pattern ConvBNfprop
. Because of performance reasons, the output of batch norm Y_bn
, which was calculated in ConvBNfprop
(output of scalebias), needs to be recalculated by DgradDreluBnBwdWeight
. The pointwise add node subtracts mean_bn
from X_bn
, hence the alpha2
parameter for that node should be set to 1
.
3.3.4.6. FP8 Fused Flash Attention
cuDNN supports fused flash attention with input and output data types being in FP8 format. This FP8specific graph pattern is supported only on Hopper (H100) GPUs.
Support exists for both training (forward and backward pass) and inference in FP8 format. The training forward pass is slightly different from the inference forward pass regarding whether some intermediate tensors are output or not.
Within the NVIDIA Hopper architecture, there are two new FP8 formats: E4M3 and E5M2. Currently, for forward pass, only when all the inputs and outputs are in E4M3 format is supported. For the backward pass, the support is only when some of the inputs and outputs are in E4M3 and some in E5M2. More general support for the FP8 formats will be added in future releases.
Due to the limited numerical precision of FP8 data type, for practical use cases, you must scale values computed in FP32 format before storing them in FP8 format, and descale the values stored in FP8 format before performing computations on them. For more information, refer to the Transformer Engine FP8 Primer. The following notation is used in this section.
 b  number of batches
 h  number of heads
 d  maximum length of sequences in a batch
 d  embedding dimension size of a word in a sequence
Scaling and Descaling
In the context of FP8, scaling refers to multiplying each element of a FP32 tensor by a quantization factor.
The quantization factor is computed as: (Max representable value in the fp8 format) / (Max absolute value seen in the tensor).
For the E4M3 format, the quantization factor is 448.f/ tensor_amax
(rounded to the nearest lower power of two).
For the E5M2 format, the quantization factor is 57344.f / tensor_amax
(rounded to the nearest lower power of two).
The meaning behind scaling is to spawn the full range of the FP8 format when computing on FP8 values and storing FP8 values, thereby, minimizing the precision loss. True values in FP32 format are multiplied by the quantization factor before storing them as scaled values in FP8 format. Computations on scaled values in FP8 format are descaled by multiplying with the dequantization factor to convert them back to their true values in FP32 format.
Scaling and descaling are critical for convergence with the FP8 data type, hence cuDNN only supports graph patterns for FP8 fused attention with the scaling and descaling nodes present.
Unpadded Tensors
In fused flash attention, the length of different sequences in a batch can be different. The cuDNN operation graph supports an unpadded layout where all the sequences of different lengths in a batch are tightly packed. All the word embeddings after the useful length of the sequence are pushed towards the end of all sequences in the layout.
Forward Pass
The following figure shows the cuDNN operation graph for the fused attention forward pass. The same graph supports forward pass for both training and inference. The operation graph pattern is identified as training when M
and Zinv
tensors are nonvirtual. When M
and Zinv
tensors are virtual, the operation graph pattern is identified as inference.
The FP8 tensors are expected to be scaled and the matrix multiplication computation is performed on the FP8 tensors in the scaled format. All non matrix multiplication computations are performed in FP32 precision. The output of the FP8 matrix multiplication is converted to real values in FP32 by format multiplying with the descale values.
Figure 47. FP8 Fused Attention Forward Pass Operation Graph
Tensor Name  Data Type  Dimensions 

Q 
E4M3  [b, h, s, d] 
K 
E4M3  [b, h, s, d] 
V 
E4M3  [b, h, s, d] 
Attention Scale  FP32 (by value)  [1, 1, 1, 1] 
Descale Q 
FP32  [1, 1, 1, 1] 
Descale K 
FP32  [1, 1, 1, 1] 
Descale V 
FP32  [1, 1, 1, 1] 
Scale S 
FP32  [1, 1, 1, 1] 
Descale S 
FP32  [1, 1, 1, 1] 
Scale O 
FP32  [1, 1, 1, 1] 
RNG Seed  INT64  [1, 1, 1, 1] 
RNG Offset  INT64  [1, 1, 1, 1] 
Dropout Probability (p) or Keep Probability (1  p)  FP32  [1, 1, 1, 1] 
Tensor Name  Data Type  Dimensions 

O 
E4M3  [b, h, s, d] 
Amax_O 
FP32  [1, 1, 1, 1] 
M 
FP32 (training only)  [b, h, s, 1] 
Zinv 
FP32 (training only)  [b, h, s, 1] 
Backward Pass
Figure 48. FP8 Fused Attention Backward Pass Operation Graph
Tensor Name  Data Type  Dimensions 

Q 
E4M3  [b, h, s, d] 
K 
E4M3  [b, h, s, d] 
V 
E4M3  [b, h, s, d] 
O 
E4M3  [b, h, s, d] 
dO 
E5M2  [b, h, s, d] 
M 
FP32  [b, h, s, 1] 
Zinv 
FP32  [b, h, s, 1] 
Attention Scale  FP32 (by value)  [1, 1, 1, 1] 
Descale Q 
FP32  [1, 1, 1, 1] 
Descale K 
FP32  [1, 1, 1, 1] 
Descale V 
FP32  [1, 1, 1, 1] 
Scale S 
FP32  [1, 1, 1, 1] 
Descale S 
FP32  [1, 1, 1, 1] 
Descale O 
FP32  [1, 1, 1, 1] 
Descale dO 
FP32  [1, 1, 1, 1] 
Scale dS 
FP32  [1, 1, 1, 1] 
Descale dS 
FP32  [1, 1, 1, 1] 
Scale dQ 
FP32  [1, 1, 1, 1] 
Scale dK 
FP32  [1, 1, 1, 1] 
Scale dV 
FP32  [1, 1, 1, 1] 
RNG Seed  INT64  [1, 1, 1, 1] 
RNG Offset  INT64  [1, 1, 1, 1] 
Dropout Probability (p) or Keep Probability (1  p)  FP32  [1, 1, 1, 1] 
Tensor Name  Data Type  Dimensions 

dQ 
E5M2  [b, h, s, d] 
dK 
E5M2  [b, h, s, d] 
dV 
E5M2  [b, h, s, d] 
Amax_dQ 
FP32  [1, 1, 1, 1] 
Amax_dK 
FP32  [1, 1, 1, 1] 
Amax_dV 
FP32  [1, 1, 1, 1] 
Amax_dS 
FP32 (virtual tensor dS is of E5M2 type) 
[1, 1, 1, 1] 
3.3.5. Mapping with Backend Descriptors
For readability, the operations used in this section are abbreviated. The mapping with the actual backend descriptors can be found in this table:
Notation used in this section  Backend descriptor 

Pointwise:scale 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_MUL and with operand B broadcasting into operand X 
Pointwise:bias 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_ADD and with operand B broadcasting into operand X 
Pointwise:add 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_ADD and with operand B with same dimensions as X 
Pointwise:mul 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_MUL and with operand B with same dimensions as X 
Pointwise:ReLU 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_RELU_FWD 
Pointwise:ReLUBwd 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_RELU_BWD 
Pointwise:tanh 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_TANH_FWD 
Pointwise:sigmoid 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_SIGMOID_FWD 
Pointwise:ELU 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with mode CUDNN_POINTWISE_ELU_FWD 
Pointwise:{ReLU,tanh,sigmoid,ELU} 
CUDNN_BACKEND_OPERATION_POINTWISE_DESCRIPTOR with one of the following modes:

MatMul 
CUDNN_BACKEND_OPERATION_MATMUL_DESCRIPTOR 
ConvolutionFwd 
CUDNN_BACKEND_OPERATION_CONVOLUTION_FORWARD_DESCRIPTOR 
ConvolutionBwFilter 
CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_FILTER_DESCRIPTOR 
ConvolutionBwData 
CUDNN_BACKEND_OPERATION_CONVOLUTION_BACKWARD_DATA_DESCRIPTOR 
GenStats 
CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR 
ResampleFwd 
CUDNN_BACKEND_OPERATION_RESAMPLE_FWD_DESCRIPTOR 
GenStats 
CUDNN_BACKEND_OPERATION_GEN_STATS_DESCRIPTOR 
Reduction 
CUDNN_BACKEND_OPERATION_REDUCTION_DESCRIPTOR 
BnBwdWeight 
CUDNN_BACKEND_OPERATION_BN_BWD_WEIGHTS_DESCRIPTOR 
NormForward 
CUDNN_BACKEND_OPERATION_NORM_FORWARD_DESCRIPTOR 
NormBackward 
CUDNN_BACKEND_OPERATION_NORM_BACKWARD_DESCRIPTOR 
BOOLEAN/packedBOOLEAN 

INT8 
CUDNN_DATA_INT8 
FP8 
CUDNN_DATA_FP8_E4M3 or CUDNN_DATA_FP8_E5M2 
FP16 
CUDNN_DATA_HALF 
BF16 
CUDNN_DATA_BFLOAT16 
FP32 
CUDNN_DATA_FLOAT 
TF32 
A tensor core operation mode used to accelerate floating point convolutions or matmuls. This can be used for an operation with compute type CUDNN_DATA_FLOAT , on NVIDIA Ampere architecture or later and be disabled with NVIDIA_TF32_OVERRIDE=1 . 
4.1. Convolution Functions
4.1.1. Prerequisites
For the supported GPUs, the Tensor Core operations will be triggered for convolution functions only when cudnnSetConvolutionMathType()
is called on the appropriate convolution descriptor by setting the mathType
to CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
.
4.1.2. Supported Algorithms
When the prerequisite is met, the below convolution functions can be run as Tensor Core operations:
Refer to the following table for a list of supported algorithms:
Supported Convolution Function  Supported Algos 

cudnnConvolutionForward 

cudnnConvolutionBackwardData 

cudnnConvolutionBackwardFilter 

4.1.3. Data and Filter Formats
The cuDNN library may use padding, folding, and NCHWtoNHWC transformations to call the Tensor Core operations. For more information, refer to Tensor Transformations.
For algorithms other than *_ALGO_WINOGRAD_NONFUSED
, when the following requirements are met, the cuDNN library will trigger the Tensor Core operations:
4.2. RNN Functions
4.2.1. Prerequisites
Tensor Core operations are triggered for these RNN functions only when cudnnSetRNNMatrixMathType()
is called on the appropriate RNN descriptor setting mathType
to CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
.
4.2.2. Supported Algorithms
When the above prerequisites are met, the RNN functions below can be run as Tensor Core operations:
Refer to the following table for a list of supported algorithms:
RNN Function  Support Algos 

All RNN functions that support Tensor Core operations. 

4.2.3. Data and Filter Formats
When the following requirements are met, then the cuDNN library triggers the Tensor Core operations:
For more information, refer to Features of RNN Functions.
4.2.4. Features of RNN Functions
Refer to the following table for a list of features supported by each RNN function.
For each of these terms, the shortform versions shown in the parenthesis are used in the tables below for brevity: CUDNN_RNN_ALGO_STANDARD
(_ALGO_STANDARD
), CUDNN_RNN_ALGO_PERSIST_STATIC
(_ALGO_PERSIST_STATIC
), CUDNN_RNN_ALGO_PERSIST_DYNAMIC
(_ALGO_PERSIST_DYNAMIC
), and CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
(_ALLOW_CONVERSION
).
Functions  I/O layout supported  Supports variable sequence length in batch  Commonly supported 

cudnnRNNForwardInference() 
Only Sequence major, packed (nonpadded)  Only with Require input sequences descending sorted according to length. 
Mode (cell type) supported: Algo supported^{1} (refer to the table for for information on these algorithms): Math mode supported: (will automatically fall back if run on preVolta or if algo doesn’t support Tensor Cores)
Direction mode supported: RNN input mode: 
cudnnRNNForwardTraining() 

cudnnRNNBackwardData() 

cudnnRNNBackwardWeights() 

cudnnRNNForwardInferenceEx() 
Sequence major unpacked Batch major unpacked^{2} Sequence major packed^{3} 
Only with For unpacked layout, no input sorting required. ^{4} For packed layout, require input sequences descending sorted according to length. 

cudnnRNNForwardTrainingEx() 

cudnnRNNBackwardDataEx() 

cudnnRNNBackwardWeightsEx() 
The following table provides the features supported by the algorithms referred in the above table: CUDNN_RNN_ALGO_STANDARD
, CUDNN_RNN_ALGO_PERSIST_STATIC
, and CUDNN_RNN_ALGO_PERSIST_DYNAMIC
.
Features  _ALGO_STANDARD 
_ALGO_PERSIST_STATIC 
CUDNN_RNN_ALGO_PERSIST_STATIC_SMALL_H 
_ALGO_PERSIST_DYNAMIC 

Half input Single accumulation Half output 
Supported Half intermediate storage Single accumulation 

Single input Single accumulation Single output 
Supported If running on Volta, with Otherwise: Single intermediate storage Single accumulation 

Double input Double accumulation Double output 
Supported Double intermediate storage Double accumulation 
Not Supported  Not Supported  Supported Double intermediate storage Double accumulation 
LSTM recurrent projection  Supported  Not Supported  Not Supported  Not Supported 
LSTM cell clipping  Supported  
Variable sequence length in batch  Supported  Not Supported  Not Supported  Not Supported 
Tensor Cores  Supported For half input/output, acceleration requires setting
Acceleration requires For single input/output on NVIDIA Volta, NVIDIA Xavier, and NVIDIA Turing, acceleration requires setting
Acceleration requires For single input/output on NVIDIA Ampere architecture, acceleration requires setting
Acceleration requires 
Not Supported, will execute normally ignoring CUDNN_TENSOR_OP_MATH ^{10} or _ALLOW_CONVERSION ^{11} 

Other limitations  Max problem size is limited by GPU specifications. 
Forward RNN:

Requires real time compilation through NVRTC 
4.3. Tensor Transformations
A few functions in the cuDNN library will perform transformations such as folding, padding, and NCHWtoNHWC conversion while performing the actual function operation.
4.3.1. Conversion Between FP32 and FP16
The cuDNN API Reference allows you to specify that FP32 input data may be copied and converted to FP16 data internally to use Tensor Core operations for potentially improved performance. This can be achieved by selecting CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
enum for cudnnMathType_t
. In this mode, the FP32 tensors are internally downconverted to FP16, the Tensor Op math is performed, and finally upconverted to FP32 as outputs. For more information, refer to Figure 49.
Figure 49. Tensor Operation with FP32 Inputs
For Convolutions
For convolutions, the FP32toFP16 conversion can be achieved by passing the CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
enum value to the cudnnSetConvolutionMathType()
call.
// Set the math type to allow cuDNN to use Tensor Cores:
checkCudnnErr(cudnnSetConvolutionMathType(cudnnConvDesc, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION));
For RNNs
For RNNs, the FP32toFP16 conversion can be achieved by passing the CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
enum value to the cudnnSetRNNMatrixMathType()
call to allow FP32 data to be converted for use in RNNs.
// Set the math type to allow cuDNN to use Tensor Cores:
checkCudnnErr(cudnnSetRNNMatrixMathType(cudnnRnnDesc, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION));
4.3.2. Padding
For packed NCHW data, when the channel dimension is not a multiple of 8, then the cuDNN library will pad the tensors as needed to enable Tensor Core operations. This padding is automatic for packed NCHW data in both the CUDNN_TENSOR_OP_MATH
and the CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
cases.
4.3.3. Folding
In the folding operation, the cuDNN library implicitly performs the formatting of input tensors and saves the input tensors in an internal workspace. This can lead to an acceleration of the call to Tensor Cores.
With folding or channelfolding, cuDNN can implicitly format the input tensors within an internal workspace to accelerate the overall calculation. Performing this transformation for the user often allows cuDNN to use kernels with restrictions on convolution stride to support a strided convolution problem.
4.3.4. Conversion Between NCHW And NHWC
Tensor Cores require that the tensors be in the NHWC data layout. Conversion between NCHW and NHWC is performed when the user requests Tensor Op math. However, a request to use Tensor Cores is just that, a request and Tensor Cores may not be used in some cases. The cuDNN library converts between NCHW and NHWC if and only if Tensor Cores are requested and are actually used.
If your input (and output) are NCHW, then expect a layout change.
NonTensor Op convolutions will not perform conversions between NCHW and NHWC.
In very rare and difficulttoqualify cases that are a complex function of padding and filter sizes, it is possible that Tensor Ops is not enabled. In such cases, users can prepad to enable the Tensor Ops path.
4.4. Mixed Precision Numerical Accuracy
When the computation precision and the output precision are not the same, it is possible that the numerical accuracy will vary from one algorithm to the other.
For example, when the computation is performed in FP32 and the output is in FP16, the CUDNN_CONVOLUTION_BWD_FILTER_ALGO_0
(ALGO_0
) has lower accuracy compared to the CUDNN_CONVOLUTION_BWD_FILTER_ALGO_1
(ALGO_1
). This is because ALGO_0
does not use extra workspace, and is forced to accumulate the intermediate results in FP16, that is, half precision float, and this reduces the accuracy. The ALGO_1
, on the other hand, uses additional workspace to accumulate the intermediate values in FP32, that is, full precision float.
This section includes a random set of topics and concepts.
5.1. Thread Safety
The cuDNN library is threadsafe. Its functions can be called from multiple host threads, so long as the threads do not share the same cuDNN handle simultaneously.
When creating a perthread cuDNN handle, it is recommended that a single synchronous call of cudnnCreate()
be made first before each thread creates its own handle asynchronously.
Per cudnnCreate()
, for multithreaded applications that use the same device from different threads, the recommended programming model is to create one (or a few, as is convenient) cuDNN handles per thread and use that cuDNN handle for the entire life of the thread.
5.2. Reproducibility (Determinism)
By design, most of cuDNN's routines from a given version generate the same bitwise results across runs when executed on GPUs with the same architecture. There are some exceptions. For example, the following routines do not guarantee reproducibility across runs, even on the same architecture, because they use atomic operations in a way that introduces truly random floating point rounding errors:
Across different architectures, no cuDNN routines guarantee bitwise reproducibility. For example, there is no guarantee of bitwise reproducibility when comparing the same routine run on NVIDIA Volta™ and NVIDIA Turing™, NVIDIA Turing, and NVIDIA Ampere architecture.
5.3. Scaling Parameters
Many cuDNN routines like cudnnConvolutionForward()
accept pointers in host memory to scaling factors alpha
and beta
. These scaling factors are used to blend the computed values with the prior values in the destination tensor as follows (refer to Figure 50):
dstValue = alpha*computedValue + beta*priorDstValue
The dstValue
is written to after being read.
Figure 50. Scaling Parameters for Convolution
When beta
is zero, the output is not read and may contain uninitialized data (including NaN).
These parameters are passed using a host memory pointer. The storage data types for alpha
and beta
are:
float
for HALF and FLOAT tensors, anddouble
for DOUBLE tensors.
For improved performance use beta = 0.0
. Use a nonzero value for beta only when you need to blend the current output tensor values with the prior values of the output tensor.
Type Conversion
When the data input x
, the filter input w
and the output y
are all in INT8 data type, the function cudnnConvolutionBiasActivationForward()
will perform the type conversion as shown in Figure 51:
Accumulators are 32bit integers that wrap on overflow.
Figure 51. INT8 for cudnnConvolutionBiasActivationForward
5.4. cuDNN API Compatibility
Beginning in cuDNN 7, the binary compatibility of a patch and minor releases is maintained as follows:
5.5. Deprecation Policy
cuDNN uses a streamlined, twostep, deprecation policy for all API and enum changes to enable a fast pace of innovation:
This depreciation scheme allows us to retire the deprecated API in just one major release. Functionality that is deprecated in the current major release can be compiled without any changes.The backward compatibility ends when another major cuDNN release is introduced.
Prototypes of deprecated functions will be prepended in cuDNN’s headers using the CUDNN_DEPRECATED
macro. When the DCUDNN_WARN_DEPRECATED
switch is passed to the compiler, any deprecated function call in your code will emit a compiler warning, for example:
warning: ‘cudnnStatus_t cudnnSetRNNMatrixMathType(cudnnRNNDescriptor_t, cudnnMathType_t)’ is deprecated [Wdeprecateddeclarations]
or
warning C4996: 'cudnnSetRNNMatrixMathType': was declared deprecated
The above warnings are disabled by default to avoid potential build breaks in software setups where compiler warnings are treated as errors. Similarly, for deprecated enum values, the compiler emits a warning when attempting to use a deprecated value:
warning: ‘EXAMPLE_VAL’ is deprecated: value not allowed [Wdeprecateddeclarations]
or
warning C4996: ‘EXAMPLE_VAL’: was declared deprecated
Special Case: API Behavior Change
To help ease the transition and avoid any surprises to developers, a behavior change between two major versions of a specific API function is accommodated by suffixing the function with a _v
tag followed by the current, major cuDNN version. In the next major release, the deprecated function is removed, and its name is never reused. (Brandnew API’s are first introduced without the _v
tag).
Updating a function’s behavior in this way uses the API’s name to embed the cuDNN version where the API call was modified. As a result, the API changes will be easier to track and document.
Let us explain this process through an example using two subsequent, major cuDNN releases, version 8 and 9. In this example, an API function foo()
changes its behavior from cuDNN v7 to cuDNN v8.
 Major release 8

The updated API is introduced as
foo_v8()
. The deprecated APIfoo()
is kept unchanged to maintain backward compatibility until the next major release.  Major release 9

The deprecated API
foo()
is permanently removed and its name is not reused. Thefoo_v8()
function supersedes the retired callfoo()
.
5.6. GPU And Driver Requirements
For the latest compatibility software versions of the OS, CUDA, the CUDA driver, and the NVIDIA hardware, refer to the NVIDIA cuDNN Support Matrix.
5.7. Convolutions
The convolution functions are:
5.7.1. Convolution Formulas
This section describes the various convolution formulas implemented in cuDNN convolution functions for the cudnnConvolutionForward()
path.
The convolution terms described in the table below apply to all the convolution formulas that follow.
Term  Description 

$x$  Input (image) Tensor 
$w$  Weight Tensor 
$y$  Output Tensor 
$n$  Current Batch Size 
$c$  Current Input Channel 
$C$  Total Input Channels 
$H$  Input Image Height 
$W$  Input Image Width 
$k$  Current Output Channel 
$K$  Total Output Channels 
$p$  Current Output Height Position 
$q$  Current Output Width Position 
$G$  Group Count 
$\mathit{pad}$  Padding Value 
$u$  Vertical Subsample Stride (along Height) 
$\mathit{v}$  Horizontal Subsample Stride (along Width) 
${\mathit{dil}}_{\mathit{h}}$  Vertical Dilation (along Height) 
${\mathit{dil}}_{\mathit{w}}$  Horizontal Dilation (along Width) 
$r$  Current Filter Height 
$R$  Total Filter Height 
$s$  Current Filter Width 
$S$  Total Filter Width 
${C}_{g}$  $\frac{C}{G}$ 
${K}_{g}$  $\frac{K}{G}$ 
Convolution (convolution mode set to CUDNN_CROSS_CORRELATION
)
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{C}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p+r,\; q+s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with Padding
${x}_{\mathit{<0,\; <0}}\phantom{\rule{5px}{0ex}}=0$
${x}_{\mathit{>H,\; >W}}\phantom{\rule{5px}{0ex}}=0$
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{C}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p+rpad,\; q+spad}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with SubsampleStriding
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{C}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; (p*u)\; +\; r,\; (q*v)\; +\; s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with Dilation
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{C}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p\; +\; (r*dilh),\; q\; +\; (s*dilw)}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution (convolution mode set to CUDNN_CONVOLUTION
)
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{C}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p\; +\; r,\; q\; +\; s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,\; c,\; Rr1,\; Ss1}}$
Convolution using Grouped Convolution
${C}_{g}=\frac{C}{G}$
${K}_{g}=\frac{K}{G}$
${y}_{\mathit{n,\; k,\; p,\; q}}=\underset{c}{\overset{{C}_{g}}{\sum}}\phantom{\rule{5px}{0ex}}\underset{r}{\overset{R}{\sum}}\phantom{\rule{5px}{0ex}}\underset{s}{\overset{S}{\sum}}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; Cg*floor(k/Kg)+c,\; p+r,\; q+s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
5.7.2. Grouped Convolutions
cuDNN supports grouped convolutions by setting groupCount
> 1 for the convolution descriptor convDesc
, using cudnnSetConvolutionGroupCount()
.
By default, the convolution descriptor convDesc
is set to groupCount
of 1.
Basic Idea
Conceptually, in grouped convolutions, the input channels and the filter channels are split into a groupCount
number of independent groups, with each group having a reduced number of channels. The convolution operation is then performed separately on these input and filter groups.
For example, consider the following: if the number of input channels is 4, and the number of filter channels of 12. For a normal, ungrouped convolution, the number of computation operations performed are 12*4.
If the groupCount
is set to 2, then there are now two input channel groups of two input channels each, and two filter channel groups of six filter channels each.
As a result, each grouped convolution will now perform 2*6 computation operations, and two such grouped convolutions are performed. Hence the computation savings are 2x: (12*4)/(2*(2*6))
.
cuDNN Grouped Convolution
Refer to Convolution Formulas for the math behind the cuDNN grouped convolution.
Example
Below is an example showing the dimensions and strides for grouped convolutions for NCHW format, for 2D convolution.
The symbols *
and /
are used to indicate multiplication and division.
5.7.3. Best Practices for 3D Convolutions
These guidelines are applicable to 3D convolution and deconvolution functions starting in cuDNN v7.6.3.
The following guidelines are for setting the cuDNN library parameters to enhance the performance of 3D convolutions. Specifically, these guidelines are focused on settings such as filter sizes, padding and dilation settings. Additionally, an applicationspecific usecase, namely, medical imaging, is presented to demonstrate the performance enhancement of 3D convolutions with these recommended settings. Specifically, these guidelines are applicable to the following functions and their associated data types:
For more information, refer to the NVIDIA cuDNN API Reference.
5.7.3.1. Recommended Settings
The following table shows the recommended settings while performing 3D convolutions for cuDNN.
Platform  NVIDIA Hopper architecture NVIDIA Ampere architecture NVIDIA Turing architecture NVIDIA Volta architecture 

Convolution (3D or 2D)  3D and 2D  
Convolution or deconvolution (fprop , dgrad , or wgrad ) 


Grouped convolution size 
Not supported for INT8 

Data layout format (NHWC /NCHW )^{12} 
NDHWC  
Input/output precision (FP16, FP32, INT8, or FP64)  FP16, FP32^{13}, INT8^{14}  
Accumulator (compute) precision (FP16, FP32, INT32 or FP64)  FP32, INT32  
Filter (kernel) sizes  No limitation  
Padding  No limitation  
Image sizes  2 GB limitation for a tensor  
Number of channels  C 

K 


Convolution mode  Crosscorrelation and convolution  
Strides  No limitation  
Dilation  No limitation  
Data pointer alignment  All data pointers are 16bytes aligned. 
5.7.3.2. Limitations
Your application will be functional but could be less performant if the model has channel counts lower than 32 (gets worse the lower it is).
If the above is in the network, use cuDNNFind
to get the best option.
5.8. Environment Variables
cuDNN’s behavior can be influenced through a set of environment variables. The following environment variables are officially supported by cuDNN:
For more information about these variables, refer to the NVIDIA cuDNN API Reference.
Except for the environment variables listed above, we provide no support or guarantee on the use of any other environment variables prefixed by CUDNN_
.
The following sections help answer the most commonly asked questions regarding typical use cases.
6.1. Error Reporting And API Logging
The cuDNN error reporting and API logging is a utility for recording the cuDNN API execution and error information. For each cuDNN API function call, all input parameters are reported in the API logging. If errors occur during the execution of the cuDNN API, a traceback of the error conditions can also be reported to help troubleshooting. This functionality is disabled by default, and can be enabled using the methods described in the later part of this section through three logging severity levels: CUDNN_LOGINFO_DBG
, CUDNN_LOGWARN_DBG
and CUDNN_LOGERR_DBG
.
The log output contains variable names, data types, parameter values, device pointers, process ID, thread ID, cuDNN handle, CUDA stream ID, and metadata such as time of the function call in microseconds.
For example, when the severity level CUDNN_LOGINFO_DBG
is enabled, the user will receive the API loggings, such as:
cuDNN (v8300) function cudnnSetActivationDescriptor() called:
mode: type=cudnnActivationMode_t; val=CUDNN_ACTIVATION_RELU (1);
reluNanOpt: type=cudnnNanPropagation_t; val=CUDNN_NOT_PROPAGATE_NAN (0);
coef: type=double; val=1000.000000;
Time: 20171121T14:14:21.366171 (0d+0h+1m+5s since start)
Process: 21264, Thread: 21264, cudnn_handle: NULL, cudnn_stream: NULL.
Starting in cuDNN 8.3.0, when the severity level CUDNN_LOGWARN_DBG
or CUDNN_LOGERR_DBG
are enabled, the log output additionally reports an error traceback such as the example below (currently only cuDNN version 8 graph APIs and legacy convolution APIs are using this error reporting feature). This traceback reports the relevant error/warning conditions, aiming to provide the user hints for troubleshooting purposes. Within the traceback, each message may have their own severity and will only be reported when the respective severity level is enabled. The traceback messages are printed in the reverse order of the execution so the messages at the top will be the root cause and tend to be more helpful for debugging.
cuDNN (v8300) function cudnnBackendFinalize() called:
Info: Traceback contains 5 message(s)
Error: CUDNN_STATUS_BAD_PARAM; reason: out <= 0
Error: CUDNN_STATUS_BAD_PARAM; reason: is_valid_spacial_dim(xSpatialDimA[dim], wSpatialDimA[dim], ySpatialDimA[dim], cDesc.getPadLowerA()[dim], cDesc.getPadUpperA()[dim], cDesc.getStrideA()[dim], cDesc.getDilationA()[dim])
Error: CUDNN_STATUS_BAD_PARAM; reason: is_valid_convolution(xDesc, wDesc, cDesc, yDesc)
Error: CUDNN_STATUS_BAD_PARAM; reason: convolution.init(xDesc, wDesc, cDesc, yDesc)
Error: CUDNN_STATUS_BAD_PARAM; reason: finalize_internal()
Time: 20211005T17:11:07.935640 (0d+0h+0m+15s since start)
Process=87720; Thread=87720; GPU=NULL; Handle=NULL; StreamId=NULL.
There are two methods, as described below, to enable the error/warning reporting and API logging. For convenience, the log output can be handled by the builtin default callback function, which will direct the output to a log file or the standard I/O as designated by the user. The user may also write their own callback function to handle this information programmably, and use the to pass in the function pointer of their own callback function.
Method 1: Using Environment Variables
To enable API logging using environment variables, follow these steps:
Refer to Table 32 for the impact on the performance of API logging using environment variables. The CUDNN_LOG{INFO,WARN,ERR}_DBG
notation in the table header means the conclusion is applicable to either one of the environment variables.
Environment variables  CUDNN_LOG{INFO,WARN,ERR}_DBG=0 
CUDNN_LOG{INFO,WARN,ERR}_DBG=1 

CUDNN_LOGDEST_DBG not set 
No logging output No performance loss 
No logging output No performance loss 

No logging output No performance loss 
No logging output No performance loss 

No logging output No performance loss 
Logging to Some performance loss 

No logging output No performance loss 
Logging to Some performance loss 
Method 2: Using the API
To use API function calls to enable API logging, refer to the API description of cudnnSetCallback()
and cudnnGetCallback()
.
6.2. FAQs
Q: I’m not sure if I should use cuDNN for inference or training. How does it compare with TensorRT?
A: cuDNN provides the building blocks for common routines such as convolution, matmul, normalization, attention, pooling, activation and RNN/LSTMs. You can use cuDNN for both training and inference. However, where it differs from TensorRT is that the latter (TensorRT) is a programmable inference accelerator; just like a framework. TensorRT sees the whole graph and optimizes the network by fusing/combining layers and optimizing kernel selection for improved latency, throughout, power efficiency and for reducing memory requirements.
A rule of thumb you can apply is to check out TensorRT, see if it meets your inference needs, if it doesn't, then look at cuDNN for a closer, more indepth perspective.
Q: How does heuristics in cuDNN work? How does it know what is the optimal solution for a given problem?
A: NVIDIA actively monitors the Deep Learning space for important problem specifications such as commonly used models. The heuristics are produced by sampling a portion of these problem specifications with available computational choices. Over time, more models are discovered and incorporated into the heuristics.
Q: Is cuDNN going to support running arbitrary graphs?
A: No, we don’t plan to become a framework and execute the whole graph one op at a time. At this time, we are focused on a subgraph given by the user, where we try to produce an optimized fusion kernel. We will document the rules regarding what can be fused and what cannot. The goal is to support general and flexible fusion, however, it will take time and there will be limits in what it can do in the cuDNN version 8.0.0 launch.
Q: What’s the difference between TensorRT, TensorFlow/XLA’s fusion, and cuDNN’s fusion?
A: TensorRT and TensorFlow are frameworks; they see the whole graph and can do global optimization, however, they generally only fuse pointwise ops together or pattern match to a limited set of precompiled fixed fusion patterns like convbiasrelu. On the other hand, cuDNN targets a subgraph, but can fuse convolutions with pointwise ops, thus providing potentially better performance. CuDNN fusion kernels can be utilized by TensorRT and TensorFlow/XLA as part of their global graph optimization.
Q: Can I write an application calling cuDNN directly?
A: Yes, you can call the C/C++ API directly. Usually, data scientists would wait for framework integration and use the Python API which is more convenient. However, if your use case requires better performance, you can target the cuDNN API directly.
Q: How does mixed precision training work?
A: Several components need to work together to make mixed precision training possible. CuDNN needs to support the layers with the required datatype config and have optimized kernels that run very fast. In addition, there is a module called automatic mixed precision (AMP) in frameworks which intelligently decides which op can run in a lower precision without affecting convergence and minimize the number of type conversions/transposes in the entire graph. These work together to give you speed up. For more information, refer to Mixed Precision Numerical Accuracy.
Q: How can I pick the fastest convolution kernels with cuDNN version 8.0.0?
A: In the API introduced in cuDNN v8, convolution kernels are grouped by similar computation and numerical properties into engines. Every engine has a queryable set of performance tuning knobs. A computation case such as a convolution operation graph can be computed using different valid combinations of engines and their knobs, known as an engine configuration. Users can query an array of engine configurations for any given computation case ordered by performance, from fastest to slowest according to cuDNN’s own heuristics. Alternately, users can generate all possible engine configurations by querying the engine count and available knobs for each engine. This generated list could be used for autotuning or the user could create their own heuristics.
Q: Why is cuDNN version 8.0 convolution API call much slower on the first call than subsequent calls?
A: Due to the library split, cuDNN version 8.0 API will only load the necessary kernels on the first API call that requires it. In previous versions, this load would have been observed in the first cuDNN API call that triggers CUDA context initialization, typically cudnnCreate()
. In version 8.0, this is delayed until the first sublibrary call that triggers CUDA context initialization. Users who desire to have CUDA context preloaded can call the new cudnnCnnInferVersionCheck()
API (or its related cousins), which has the side effect of initializing a CUDA context. This will reduce the run time for all subsequent API calls.
Q: How do I build the cuDNN version 8.0.0 split library?
A: cuDNN v8.0 library is split into multiple sublibraries. Each library contains a subset of the API. Users can link directly against the individual libraries or link with a dlopen
layer which follows a plugin architecture.
To link against an individual library, users can directly specify it and its dependencies on the linker command line. For example, for infer libraries: lcudnn_adv_infer
, lcudnn_cnn_infer
, or lcudnn_ops_infer
.
For all libraries, lcudnn_adv_train
, lcudnn_cnn_train
, lcudnn_ops_train
, lcudnn_adv_infer
, lcudnn_cnn_infer
, and lcudnn_ops_infer
.
The dependency order is documented in the NVIDIA cuDNN 8.0.0 Preview Release Notes and the NVIDIA cuDNN API Reference.
Alternatively, the user can continue to link against a shim layer (libcudnn
) which can dlopen
the correct library that provides the implementation of the function. When the function is called for the first time, the dynamic loading of the library takes place.
Linker argument:
lcudnn
Q: What are the new APIs in cuDNN version 8.0.0?
A: The new cuDNN APIs are listed in the cuDNN 8.0.0 Release Notes as well as in the API changes for cuDNN 8.0.0.
6.3. Support
Support, resources, and information about cuDNN can be found online at https://developer.nvidia.com/cudnn. This includes downloads, webinars, NVIDIA Developer Forums, and more.
We appreciate all types of feedback. Consider posting on the forums with questions, comments, and suspected bugs that are appropriate to discuss publicly. cuDNNrelated posts are reviewed by the cuDNN engineering team, and internally we will file bugs where appropriate. It’s helpful if you can paste or attach an API log to help us reproduce. External users can also file bugs directly by following these steps:
 Register for the NVIDIA Developer website.
 Log in to the developer site.
 Click on your name in the upper right corner.
 Click My account > My Bugs and select Submit a New Bug.
 Fill out the bug reporting page. Be descriptive and if possible, provide the steps that you are following to help reproduce the problem. If possible, paste or attach an API log.
 Click Submit a bug.
Some of the cuDNN library routines were derived from code developed by others and are subject to the following:
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CUDNN_RNN_PADDED_IO_ENABLED
through cudnnSetRNNPaddingMode()
.
CUDNN_RNN_PADDED_IO_ENABLED
through cudnnSetRNNPaddingMode()
.
CUDNN_RNN_PADDED_IO_ENABLED
through cudnnSetRNNPaddingMode()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
CUDNN_TENSOR_OP_MATH
or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION
can be set through cudnnSetRNNMatrixMathType()
.
NHWC
/NCHW
corresponds to NDHWC
/NCDHW
in 3D convolution.
CUDNN_TENSOROP_MATH_ALLOW_CONVERSION
preAmpere. Default TF32 math in NVIDIA Ampere architecture.
dgrad
and wgrad
. INT8 3D convolutions are only supported in the backend API. Refer to the tables in for more information.