DOCA Documentation v2.6.0
DOCA SDK 2.6.0

NVIDIA DOCA Glossary

Term

Description

ACS

Access control services

ATF

Arm-trusted firmware

BDF address

Bus, device, function address. This is the device's PCIe bus address to uniquely identify the specific device.

BFB

BlueField bootstream

BGP

Border gateway protocol

BMC

Board management controller

BUF

Buffer

BSP

BlueField support package

CBS

Committed burst size

CIR

Committed information rate

CMDQ

Command queue

CPDS

Control pipe dynamic size

CTX

Context

DEK

Data encryption key

DMA

Direct memory access

DOCA

DPU SDK

DPA

Data path accelerator; a n auxiliary processor designed to accelerate data-path operations

DPCP

Direct packet control plane

DPDK

Data plane development kit

DPI

Deep packet inspection

DPU

Data processing unit, the third pillar of the data center with CPU and GPU

DW

Dword

EBS

Excess burst size

ECE

Enhanced connection establishment

ECPF

Embedded CPU physical function

EIR

Excess information rate

eMMC

Embedded multi-media card

ESP

EFI system partition

ESP header

Encapsulating security payload

EU

Execution unit. HW thread; a logical DPA processing unit.

FIPS

Federal Information Processing Standards

FPGA

Field-programmable gate arrays

FW

Firmware

GDB

GNU debugger

HCA

Host-channel adapter

Host

When referring to "the host" this documentation is referring to the server host. When referring to the Arm based host, the documentation will specifically call out "Arm host".

  • Server host OS refers to the Host Server OS (Linux or Windows)

  • Arm host refers to the AARCH64 Linux OS which is running on the BlueField Arm Cores

HW

Hardware

hwmon

Hardware monitoring

IB

InfiniBand

ICM

Interface configuration memory

ICV

Integrity check value

IDE

Integrated development environment

IKE

Internet key exchange

IR

Intermediate representation

LSO

Large send offload

LTO

Link-time optimization

MFT

Mellanox firmware tools

MLNX_OFED

Mellanox OpenFabrics Enterprise Distribution

MSB

Most significant bit

MSS

Memory subsystem

MST

Mellanox software tools

MTU

Maximum transmission unit

NAT

Network address translation

NIC

Network interface card

NIST

National Institute of Standards and Technology

NS

Namespace

OOB

Out-of-band

OS

Operating system

OVS

Open vSwitch

PBS

Peak burst size

PCIe

PCI Express; Peripheral Component Interconnect Express

PF

Physical function

PE

Progress engine

PIR

Peak information rate

PK

Platform key

PKA

Public key accelerator

POC

Proof of concept

PUD

Process under debug

RD

Route distinguisher

RDMA

Remote direct memory access

RegEx

Regular expression

REQ

Request

RES

Response

RN

Request node

RN-F – Fully coherent request node

RN-D – IO coherent request node with DVM support

RN-I – IO coherent request node

RNG

Random number generator/generation

RoCE

Ethernet and RDMA over converged Ethernet

RQ

Receive queue

RShim

Random shim

RSP

Remote serial protocol

RT

Route target

RTOS

Real-time operating system

RTT

Round-trip time

RX

Receive

RXP

Regular expression processor

SA

Security association

SBSA

Server base system architecture

SDK

Software development kit

SF

Sub-function or scalable function

SG

Scatter-gather

SHA

Secure hash algorithm

SNAP

Storage-defined network-accelerated processing

SPDK

Storage performance development kit

SQ

Send queue

SR-IOV

Single-root IO virtualization

SVI

Switch virtual interface

Sync event

Synchronization event

TAI

International Atomic Time

TIR

Transport interface receive

TIS

Transport interface send

TLS

Transport layer security

TX

Transmit

UDS

Unix domain socket

UEFI

Unified extensible firmware interface

UTC

Coordinated Universal Time

VF

Virtual function

VFE

Virtio full emulation

VM

Virtual machine

VMA

NVIDIA® Messaging Accelerator

VNI

VXLAN network identifier

VPI

Virtual protocol interconnect

VRF

Virtual routing and forwarding

VTEP

VXLAN tunnel endpoint

WorkQ or workq

Work queue

WQE

Work queue elements

WR

Write

XLIO

NVIDIA® Accelerated IO

© Copyright 2024, NVIDIA. Last updated on May 7, 2024.