QSPI Access

Detailed Description

Declares the APIs for Quickboot accessing QSPI.

Data Structures
struct	QspiTransfer
	Holds QSPI Transfer data. More...
struct	QspiControllerData
	Holds QSPI hardware controller context data. More...

Macros
#define	DEBUG_QSPI   0
#define	PRINT_QSPI_DBG_MESSAGES(...)
#define	PRINT_QSPI_REG_ACCESS(...)
#define	QSPI_CONTROLLERS_MAX   1
#define	QSPI_MAX_BIT_LENGTH   31
#define	QSPI_8Bit_BIT_LENGTH   7
#define	QSPI_FIFO_DEPTH   64
#define	BYTES_PER_WORD   4
#define	QSPI_HW_TIMEOUT   100000
	Defines the read time-out, in milliseconds. More...

Typedefs
typedef struct QspiTransfer	QspiTransfer
	Holds QSPI Transfer data. More...

Enumerations
enum	QspiBusWidth {   QSPI_BUS_WIDTH_X1,   QSPI_BUS_WIDTH_X2,   QSPI_BUS_WIDTH_X4 }
	Defines the QSPI bus widths. More...
enum	NvQspiChipSelect {   ACTIVE_LOW = 0,   ACTIVE_HIGH }
	Defines the QSPI chip selection. More...
enum	QspiXferType_t {   SYNC,   ASYNC }
	Defines the transfer types. More...
enum	QspiOpMode_t {   SDR_MODE = 0,   DDR_MODE }
	Defines the QSPI controller and Flash chip operating mode. More...

Functions
NvError	NvQspiInit (void *pdata)
	Initializes the specified QSPI controller. More...
NvError	QspiHwProcReadAsyncWaitDMAComplete (NvU32 Instance)
	Waits until the IO from the DMA is complete. More...
NvError	NvQspiTransaction (QspiTransfer *Transfers, NvU8 Numoftransfers, NvU32 Instance)
	Performs QSPI transactions for write and read. More...
void	NvQspiShutdown (NvU32 Instance)
	Shuts down the QSPI controller. More...
void	QspiDumpRegisters (NvU32 Instance)
	Dumps the registers of the QSPI controller. More...

Macro Definition Documentation

#define BYTES_PER_WORD   4

Definition at line 61 of file qspi.h.

#define DEBUG_QSPI   0

Definition at line 36 of file qspi.h.

#define PRINT_QSPI_DBG_MESSAGES

(

...

)

Definition at line 41 of file qspi.h.

#define PRINT_QSPI_REG_ACCESS

(

...

)

Definition at line 42 of file qspi.h.

#define QSPI_8Bit_BIT_LENGTH   7

Definition at line 59 of file qspi.h.

#define QSPI_CONTROLLERS_MAX   1

Definition at line 48 of file qspi.h.

#define QSPI_FIFO_DEPTH   64

Definition at line 60 of file qspi.h.

#define QSPI_HW_TIMEOUT   100000

Defines the read time-out, in milliseconds.

Definition at line 64 of file qspi.h.

#define QSPI_MAX_BIT_LENGTH   31

Definition at line 58 of file qspi.h.

Typedef Documentation

typedef struct QspiTransfer QspiTransfer

Holds QSPI Transfer data.

The message consists of multiple transfers.

Enumeration Type Documentation

enum NvQspiChipSelect

Defines the QSPI chip selection.

Enumerator
ACTIVE_LOW
ACTIVE_HIGH

Definition at line 67 of file qspi.h.

enum QspiBusWidth

Defines the QSPI bus widths.

Enumerator
QSPI_BUS_WIDTH_X1
QSPI_BUS_WIDTH_X2
QSPI_BUS_WIDTH_X4

Definition at line 52 of file qspi.h.

enum QspiOpMode_t

Defines the QSPI controller and Flash chip operating mode.

Enumerator
SDR_MODE	0 [IO on single edge of clock]
DDR_MODE	1 [IO on rising and falling edge of clock]

Definition at line 82 of file qspi.h.

enum QspiXferType_t

Defines the transfer types.

Enumerator
SYNC	=0
ASYNC	=1

Definition at line 74 of file qspi.h.

Function Documentation

NvError NvQspiInit

(

void *

pdata

)

Initializes the specified QSPI controller.

Parameters

[in]

pdata

A pointer to the QSPI controller platform data gotten from board file.

Returns

NvError_Success Initialization is successful.

void NvQspiShutdown

(

NvU32

Instance

)

Shuts down the QSPI controller.

Parameters

Instance

QSPI Controller Instance. Nv_Qspi1

NvError NvQspiTransaction	(	QspiTransfer *	Transfers,
		NvU8	Numoftransfers,
		NvU32	Instance
	)

Performs QSPI transactions for write and read.

Parameters

Transfers	A pointer to an array of qspi transfers. Each message consists of multiple transfers. For QSPI Flash - <CMD><ADDRESS><DATA>.
Numoftransfers	Number of transfers.
Instance	QSPI Controller Instance.

Return values

NvError_Success

No Error

void QspiDumpRegisters

(

NvU32

Instance

)

Dumps the registers of the QSPI controller.

Parameters

Instance

Qspi Controller Instance. Nv_Qspi1

NvError QspiHwProcReadAsyncWaitDMAComplete

(

NvU32

Instance

)

Waits until the IO from the DMA is complete.

Parameters

Instance

Qspi Controller Instance. Nv_Qspi1, ... Nv_Qspi6

Returns

NvError_Success Initialization is successful.