qspi.h

Go to the documentation of this file.

/*
 * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef _QB_QSPI_H_
#define _QB_QSPI_H_

#include <device.h>
#include <nvcommon.h>
#include <nverror.h>

// Enable this to print debug messages.
// #define DEBUG_QSPI 1

#define DEBUG_QSPI 0
#if DEBUG_QSPI
#define PRINT_QSPI_DBG_MESSAGES(...)    pr_info(__VA_ARGS__)
#define PRINT_QSPI_REG_ACCESS(...)  pr_info(__VA_ARGS__)
#else
#define PRINT_QSPI_DBG_MESSAGES(...)
#define PRINT_QSPI_REG_ACCESS(...)
#endif

#ifdef CONFIG_T19x
#define QSPI_CONTROLLERS_MAX 2
#else
#define QSPI_CONTROLLERS_MAX 1
#endif

enum QspiBusWidth{
    QSPI_BUS_WIDTH_X1,
    QSPI_BUS_WIDTH_X2,
    QSPI_BUS_WIDTH_X4,
};

#define QSPI_MAX_BIT_LENGTH      31
#define QSPI_8Bit_BIT_LENGTH     7
#define QSPI_FIFO_DEPTH          64
#define BYTES_PER_WORD           4

#define QSPI_HW_TIMEOUT          100000

typedef enum
{
    ACTIVE_LOW = 0,
    ACTIVE_HIGH,
} NvQspiChipSelect;

typedef enum
{
    SYNC, 
    ASYNC 
} QspiXferType_t;


typedef enum {
    SDR_MODE = 0, 
    DDR_MODE      
} QspiOpMode_t;

typedef struct QspiTransfer
{
  NvU8 *Txbuf;         
  NvU8 *Rxbuf;         
  NvU32 Mode;          
  NvU32 Writelen;      
  NvU32 Readlen;       
  NvU32 Speed_hz;      
  NvU32 BusWidth;      
  NvU32 DummyCycles;   
  QspiXferType_t type; 
  QspiOpMode_t OpMode; 
} QspiTransfer;

typedef struct
{
    NvU32 Instance;           
    NvU32 BaseAddr;           

    QspiOpMode_t OpMode;
    NvU32 DmaChannel;         
    NvU32 DmaClient;          
    NvU32 ReadStartTimeinUs;  
    NvU32 WriteStartTimeinUs; 

    NvU32 ChipSelectLevel;

    NvU32 CSActiveBwPkts;
    NvU32 CyclesBwPkts;       
    NvU32 TxClkTapDelay;      
    NvU32 RxClkTapDelay;      
    NvU32 QuadState;          

    QspiTransfer Transfers[3];
} QspiControllerData;

NvError NvQspiInit(void *pdata);

NvError
QspiHwProcReadAsyncWaitDMAComplete(NvU32 Instance);

NvError
NvQspiTransaction(
        QspiTransfer *Transfers,
        NvU8 Numoftransfers,
        NvU32 Instance);

void NvQspiShutdown(NvU32 Instance);

void QspiDumpRegisters(NvU32 Instance);

#endif /* _QB_QSPI_H_ */