sdmmc.h

Go to the documentation of this file.

/*
 * Copyright (c) 2010-2018, NVIDIA CORPORATION.  All Rights Reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef INCLUDED_SDMMC_H
#define INCLUDED_SDMMC_H
#include <device.h>
#include <clock_reg.h>
#include <nvboot_sdmmc_param.h>

#define MAX_SDMMC_INSTANCE 4

#define SDMMC_COMMAND_TIMEOUT_IN_US 100000
#define SDMMC_OP_COND_TIMEOUT_IN_US 1000000
#define SDMMC_READ_TIMEOUT_IN_US 200000
#define SDMMC_TIME_OUT_IN_US 100000

#define NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES 16
#define NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES 512
#define NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES 512

#define DEBUG_SDMMC 0

typedef enum
{
    SdmmcResponseType_NoResponse = 0,
    SdmmcResponseType_R1 = 1,
    SdmmcResponseType_R2 =2,
    SdmmcResponseType_R3 =3,
    SdmmcResponseType_R4 = 4,
    SdmmcResponseType_R5 = 5,
    SdmmcResponseType_R6 = 6,
    SdmmcResponseType_R7 = 7,
    SdmmcResponseType_R1B = 8,
    SdmmcResponseType_Num,
    SdmmcResponseType_Force32 = 0x7FFFFFFF
} SdmmcResponseType;

typedef enum
{
    SdmmcCommand_GoIdleState = 0,
    SdmmcCommand_EmmcSendOperatingConditions = 1,
    SdmmcCommand_AllSendCid = 2,
    SdmmcCommand_EmmcSetRelativeAddress = 3,
    SdmmcCommand_EsdSendRelativeAddress = 3,
    SdmmcCommand_Switch = 6,
    SdmmcCommand_SelectDeselectCard = 7,
    SdmmcCommand_EsdSendInterfaceCondition = 8,
    SdmmcCommand_EmmcSendExtendedCsd = 8,
    SdmmcCommand_SendCsd = 9,
    SdmmcCommand_StopTransmission =12,
    SdmmcCommand_SendStatus = 13,
    SdmmcCommand_SetBlockLength = 16,
    SdmmcCommand_ReadSingle = 17,
    SdmmcCommand_ReadMultiple = 18,
    SdmmcCommand_SetBlockCount = 23,
    SdmmcCommand_WriteSingle = 24,
    SdmmcCommand_WriteMultiple = 25,
    SdmmcCommand_EsdAppSendOperatingCondition = 41,
    SdmmcCommand_EsdSelectPartition = 43,
    SdmmcCommand_EsdAppSendScr = 51,
    SdmmcCommand_EsdAppCommand = 55,
    SdmmcCommand_Force32 = 0x7FFFFFFF
} SdmmcCommand;

typedef enum
{
    SdmmcState_Idle = 0,
    SdmmcState_Ready,
    SdmmcState_Ident,
    SdmmcState_Stby,
    SdmmcState_Tran,
    SdmmcState_Data,
    SdmmcState_Rcv,
    SdmmcState_Prg,
    SdmmcState_Force32 = 0x7FFFFFFF
} SdmmcState;

typedef enum
{
    SdmmcAccessRegion_UserArea = 0,
    SdmmcAccessRegion_BootPartition1,
    SdmmcAccessRegion_BootPartition2,
    SdmmcAccessRegion_Num,
    SdmmcAccessRegion_Unknown,
    SdmmcAccessRegion_Force32 = 0x7FFFFFFF
} SdmmcAccessRegion;

typedef enum
{
    NvBootSdmmcCardType_Emmc = 0,
    NvBootSdmmcCardType_Esd,
    NvBootSdmmcCardType_Num,
    NvBootSdmmcCardType_Force32 = 0x7FFFFFFF
} NvBootSdmmcCardType;

typedef enum
{
    NvBootSdmmcCardClock_Identification = 0,
    NvBootSdmmcCardClock_DataTransfer_SDR20,
    NvBootSdmmcCardClock_DataTransfer_HS50,
    NvBootSdmmcCardClock_DataTransfer_DDR50,
    NvBootSdmmcCardClock_DataTransfer_HS400,
    NvBootSdmmcCardClock_Num,
    NvBootSdmmcCardClock_Force32 = 0x7FFFFFFF
} NvBootSdmmcCardClock;
typedef enum
{
    SdmmcInit_All = 0,
    SdmmcInit_CMD0n1,
    SdmmcInit_InitSkipCMD0,
    SdmmcInit_InitSkipIdentification,
} SdmmcInitLevel;

typedef struct
{
    NvU32 Instance;
    NvU8 ClockDivisor;

    NvU16 CardClockDivisor;

    NvBool Mantissa;

    NvBootSdmmcDataWidth DataWidth;

    /* Clock info */
    QbClocksInfo SdmmcClock;

    /* Tap and Trim values */
    NvU32 TapVal;
    NvU32 TrimVal;

    /* AutoCal PD and PU offset */
    NvU32 AutoCalPdOffset;
    NvU32 AutoCalPuOffset;

    NvBool DisableHS400;

    SdmmcInitLevel SdmmcInitType;
    NvBool Support64BitDmaAddr;
}QbSdmmcInfo;

struct QbSdmmcDriverPrivInfo
{
    NvBool IsEsd;
    NvU8 BlockSizeLog2;
    NvU8 PageSizeLog2;
    NvU8 PagesPerBlockLog2;
    NvU32 CardRca;
    NvU32 SdmmcResponse[NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES / sizeof(NvU32)];
    QbDeviceStatus DeviceStatus;
    NvU32 XferStartTime;
    NvBool HighSpeedMode;
    NvBool EnhancedStrobeMode;
    NvBool IsHighCapacityCard;
    NvU8 SpecVersion;
    NvU8 ExtCsdSpecVersion;
    NvU32 EmmcBootPartitionSize;
    SdmmcAccessRegion CurrentAccessRegion;
    NvBootSdmmcCardClock CurrentClockRate;
    NvU8 SdmmcInternalBuffer[NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES];
    NvU8 taac;
    NvU8 nsac;
    NvU8 TranSpeed;
    NvU8 TranSpeedInMHz;
    NvBool HostSupportsHighSpeedMode;
    NvBool CardSupportsHighSpeedMode;
    NvU8 PageSizeLog2ForCapacity;
    NvU8 PowerClass26MHz360V;
    NvU8 PowerClass52MHz360V;
    NvU8 PowerClass26MHz195V;
    NvU8 PowerClass52MHz195V;
    NvU8 BootConfig;
    NvBool IsHighVoltageRange;
    NvU8 MaxPowerClassSupported;
    NvU32 NumOfBlocks;
    NvU32 XferTimeOutInUs;
    NvU8 SdmmcBootModeBuffer[NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES];
    NvBool BootModeReadInProgress;
    NvU8 CardSupportSpeed;
    NvU8 PowerClass52MHzDdr360V;//PWR_CL_DDR_52_360
    NvU8 PowerClass52MHzDdr195V;//PWR_CL_DDR_52_195
    NvU8 PowerClass200MHzDdr180V;//PWR_CL_DDR_200_180
    NvU8 IsDdrMode;
    NvBool IsPLLP;

    NvU32 RegPhyBase;
    NvU32 RegLen;
    NvU32 RegVirtBase;
    QbSdmmcInfo *pdata;
    NvU32 VendorClockCtrl;
    SdmmcInitLevel SdmmcInitType;

    NvBool DisableHS400;
    // Flag to indicate if the card is in ready state.
    NvBool IsCardReady;
    NvBool Support64BitDmaAddr;
};

/*
 * Performs SDMMC driver initialization.
 * Called by QB initialization code.
 */
NvS32 QbSdmmcInit(void);

NvError
QbSdmmcRead(QbDriver DriverType, NvU32 Instance, void *Buffer, NvU64 Size, NvU64 Offset);

/*
 * Debug function to dump sdmmc controller registers to console
 */
void QbSdmmcDumpTegraRegs(NvU32 RegBase);

/*
 * Debug function to dump interrupt status registers
 */
void QbSddmmcPrintInterruptStatus(NvU32 InterruptStatus);
#endif /* #ifndef INCLUDED_SDMMC_H */