Storage Device Configuration¶

The Storage Device configuration file contains the platform-specific settings for storage devices in the MB1/MB2 stages.

The DTS configuration file is in the following form:

/ {
   device {
    <storage_device>@instance-# {
       <parameter> = <value>;
    };
   };
};

where:

<storage-device> is the storage device controller (qspiflash / ufs / sdmmc / sata)
<instance-#> is the instance of the storage controller
<parameter> is controller specific parameter as shown below.

QSPI Flash Parameters¶

Parameter	Description
`clock-source-id`	QSPI controller clock source: 1: CLK_M 3: PLLP_OUT0 4: PLLM_OUT0 5: PLLC_OUT0 6: PLLC4_MUXED
`clock-source-frequency`	Frequency of the clock source in Hz.
`interface-frequency`	QSPI controller frequency in Hz.
`enable-ddr-mode`	0: QSPI SDR mode 1: QSPI DDR mode
`maximum-bus-width`	Maximum QSPI bus width. 0: QSPIx1 lane 2: QSPIx4 lane
`filo-access-mode`	0: PIO mode 1: DMA mode
`ready-dummy-cycle`	Number of dummy cycles as per the QSPI flash.
`trimmer1-val`	TX trimmer value
`trimmer1-val`	RX trimmer value

SDMMC Parameters¶

Parameter	Description
clock-source-id	SDMMC controller clock source 0: PLLP_OUT0 1: PLLC4_OUT2_LJ 2: PLLC4_OUT0_LJ 3: PLLC4_OUT2 4: PLLC4_OUT1 5: PLLC4_OUT1_LJ 6: CLK_M 7: PLLC4_VCO
`clock-source-frequency`	Frequency of the clock source in Hz.
`best-mode`	Highest supported mode of operation. 0: SDR26 1: DDR52 2: HS200 3: HS400
`pd-offset`	Pull-down offset
`pu-offset`	Pull-up offset
`enable-strobe-hs400`	Enable the HS400 strobe.
`dqs-trim-hs400`	HS DQS trim value

UFS Parameters¶

Parameter	Description
`max-hs-mode`	Highest HS mode that is supported by the UFS device. 1: HS GEAR1 2: HS GEAR2 3: HS GEAR3
`max-pwm-mode`	Highest PWM mode that is supported by the UFS device. 1: PWM GEAR1 2: PWM GEAR2 3: PWM GEAR3 4: PWM GEAR4
`max-archive-lanes`	Maximum number of UFS lanes (1-2)
`page-align-size`	Alignment of pages that are used for UFS data structures in bytes.
`enable-hs-mode`	Determines whether to enable UFS HS mode. 0: disable 1: enable
`enable-fast-auto-mode`	Determines whether to enable fast auto mode. 0: disable 1: enable
`enable-hs-rate-a`	Determines whether to enable the HS rate A. 0: disable 1: enable
`enable-hs-rate-b`	Determines whether to enable the HS rate B. 0: disable 1: enable
`init-state`	Initial state of the UFS device at the MB1 entry. 0: UFS is not initialized by BootROM. 1: UFS is initialized by BootROM.

SATA Parameters¶

Parameter	Description
transfer-speed	0: GEN1 1: GEN2

The storage device configuration file are kept in the hardware/nvidia/platform/t23x/<platform>/bct/ directory.

The new DTS format example of the storage device configuration file:

/dts-v1/;
#include <define.h>

/ {
   device {
       qspiflash@0 {
           clock-source-id = <PLLC_MUXED>;
           clock-source-frequency = <13000000>;
           interface-frequency = <13000000>;
           enable-ddr-mode;
           maximum-bus-width = <QSPI_4_LANE>;
           fifo-access-mode = <DMA_MODE>;
           read-dummy-cycle = <8>;
           trimmer1-val = <0>;
           trimmer2-val = <0>;
       };
       sdmmc@3 {
           clock-source-id = <PLLC4_OUT2>;
           clock-source-frequency = <52000000>;
           best-mode = <HS400>;
           pd-offset = <0>;
           pu-offset = <0>;
           //enable-strobe-hs400; This property is not there means it is disabled dqs-trim-hs400 = <0>;
      };
      ufs@0 {
          max-hs-mode = <HS_GEAR_3>;
          max-pwm-mode = <PWM_GEAR_4>;
          max-active-lanes = <2>;
          page-align-size = <4096>;
          enable-hs-mode;
          //enable-fast-auto-mode; enable-hs-rate-b;
          //enable-hs-rate-a = <0>; init-state = <0>;
      };
   }
};

Here is the previous CFG format:

// QSPI flash 0
device.qspiflash.0.clock-source-id = 6;
device.qspiflash.0.clock-source-frequency = 13000000; device.qspiflash.0.interface-frequency = 13000000; device.qspiflash.0.enable-ddr-mode = 0;
device.qspiflash.0.maximum-bus-width = 2;
device.qspiflash.0.fifo-access-mode = 1;
device.qspiflash.0.read-dummy-cycle = 8;
device.qspiflash.0.trimmer1-val = 0;
device.qspiflash.0.trimmer2-val = 0;

// Sdmmc 3
device.sdmmc.3.clock-source-id = 3; //PLLP_OUT0 device.sdmmc.3.clock-source-frequency = 52000000; device.sdmmc.3.best-mode = 3; //1=DDR52, 3=HS400 device.sdmmc.3.pd-offset = 0;
device.sdmmc.3.pu-offset = 0;
device.sdmmc.3.enable-strobe-hs400 = 0;
device.sdmmc.3.dqs-trim-hs400 = 0;

// Ufs 0
device.ufs.0.max-hs-mode = 3;
device.ufs.0.max-pwm-mode = 4;
device.ufs.0.max-active-lanes = 2;
device.ufs.0.page-align-size = 4096;
device.ufs.0.enable-hs-mode = 1;
device.ufs.0.enable-fast-auto-mode = 0;
device.ufs.0.enable-hs-rate-b = 1;
device.ufs.0.enable-hs-rate-a = 0;
device.ufs.0.init-state = 0;