BootROM Reset PMIC Configuration¶
For some T23x platforms, BootROM might be required to bring PMIC rails to OTP values in the L1 and L2 reset boot paths. This process is completed by issuing I2C commands, which are encoded in AO scratch registers by MB1, and are based on the BootROM reset configuration in MB1 BCT.
The reset cases where the BootROM issues these commands includes the following:
Watchdog 5 expiry
Watchdog 4 expiry
SC7 exit
SC8 exit
SW-Reset
AO-Tag/sensor reset
VF Sensor reset
HSM reset
Each reset case can have three sets of AO blocks of commands.
Each AO block has multiple blocks, and each block can have multiple commands.
In the configuration file, AO blocks are specified first, and the reset conditions are initialized with the AO block IDs.
Specifying AO Blocks¶
Each AO block-related line in the configuration file is of the following format:
/{
<ResetType>-<Ao-comamnd-index> = <&AoBlock-Label> reset {
<AoBlock-Label>: aoblock@<aoblock-index> {
<parameter> = <value>;
...
block@<block-index> {
<parameter> = <value>;
};
};
<AoBlock-Label>: aoblock@<aoblock-index> {
...
}
};
};
<node> |
<parameter> |
Description |
<reset-type>- <Ao-command-index> |
<&AoBlock-Label> |
|
aoblock@ <AoBlock-index> |
command-retries- count |
Specifies the number of command attempts allowed for Ao-block with <AoBlock-index> |
delay-between- command-us |
Specifies the delay (in microseconds), in between different commands. The delay is calculated as 1 << n microseconds where n is provided by this parameter. |
|
wait-before- start-bus-clear- us |
Specifies the wait timeout (in microseconds), before issuing the bus clear command for given AO block. The wait time is calculated as 1 << n microseconds where n is provided by this parameter. |
|
block@<block-index> |
<command-type> |
<command-type> can only be one value - i2c-controller. That is the only one supported. |
count |
Specifies the number of commands in the block <block-index> |
|
i2c-controller id |
I2C controller instance |
|
slave-addr |
7-bit I2C slave address |
|
reg-data-size |
Register size in bits. Valid values are 0 (1-byte), 8 (1-byte), and 16 (2-byte) |
|
reg-addr-size |
Register address size in bits. Valid values are 0 (1-byte), 8 (1-byte), and 16 (2-byte) |
|
commands |
List of <Address Value> pairs where value to be written to the I2C slave register address <reg-addr> for the command indexed by <command-index> |
Here is a new DTS example of the BootROM reset configuration file:
/dts-v1/;
/ {
reset {
// Each reset path can point to upto three aoblocks
// This is a map of reset paths to aoblocks
// <reset-path>-<index-pointer> = <aoblock-id>
// index-number should be 0, 1 or 2
// aoblock-id is the id of the one of the blocks mentioned above sensor-aotag-1 = <&aoblock0>;
sc7-1 = <&aoblock2>;
aoblock0: aoblock@0 {
command-retries-count = <1>;
delay-between-commands-us = <1>;
wait-before-start-bus-clear-us = <1>;
block@0 {
i2c-controller;
slave-add = <0x3c>; // 7BIt:0x3c
reg-data-size = <8>;
reg-add-size = <8>;
commands {
command@0 {
reg-addr = <0x42>;
value = <0xda>;
};
command@1 {
reg-addr = <0x41>;
value = <0xf8>;
};
};
};
};
// Shutdown: Set MAX77620
// Register ONOFFCNFG2, bit SFT_RST_WK = <0>
// Register ONOFFCNFG1, bit SFT_RST = <1> aoblock1: aoblock@1 {
// Shutdown: Set MAX77620
// Register ONOFFCNFG2, bit SFT_RST_WK = <0>
// Register ONOFFCNFG1, bit SFT_RST = <1>
command-retries-count = <1>;
delay-between-commands-us = <1>;
wait-before-start-bus-clear-us = <1>;
block@0 {
i2c-controller;
slave-add = <0x3c>; // 7BIt:0x3c reg-data-size = <8>;
reg-add-size = <8>;
commands {
command@0 {
reg-addr = <0x42>;
value = <0x5a>;
} ;
command@1 {
reg-addr = <0x41>;
value = <0xf8>;
};
};
};
};
// SC7 exit
// Clear PMC_IMPL_DPD_ENABLE_0[ON]=0 during SC7 exit aoblock2: aoblock@2 {
command-retries-count = <1>;
delay-between-commands-us = <256>;
wait-before-start-bus-clear-us = <1>; block@0 {
mmio;
commands {
command@0 {
reg-addr = <0x0c360010>;
value = <0x0>;
};
};
};
Here is the previous CFG format:
// CFG Version 1.0
// This contains the BootROM commands in MB1 for multiple reset paths. reset.major = 1;
reset.minor = 0;
// Automatic power cycling: Set MAX77620
// Register ONOFFCNFG2, bit SFT_RST_WK = 1 (default is "0" after cold boot), // Register ONOFFCNFG1, bit SFT_RST = 1
reset.aoblock[0].command-retries-count = 1;
reset.aoblock[0].delay-between-commands-us = 1;
reset.aoblock[0].wait-before-start-bus-clear-us = 1;
reset.aoblock[0].block[0].type = 1; // I2C Type
reset.aoblock[0].block[0].slave-add = 0x3c; // 7BIt:0x3c
reset.aoblock[0].block[0].reg-data-size = 8;
reset.aoblock[0].block[0].reg-add-size = 8;
reset.aoblock[0].block[0].commands[0].0x42 = 0xda;
reset.aoblock[0].block[0].commands[1].0x41 = 0xf8;
// Shutdown: Set MAX77620
// Register ONOFFCNFG2, bit SFT_RST_WK = 0
// Register ONOFFCNFG1, bit SFT_RST = 1
reset.aoblock[1].command-retries-count = 1;
reset.aoblock[1].delay-between-commands-us = 1;
reset.aoblock[1].wait-before-start-bus-clear-us = 1;
reset.aoblock[1].block[0].type = 1; // I2C Type
reset.aoblock[1].block[0].slave-add = 0x3c; // 7BIt:0x3c
reset.aoblock[1].block[0].reg-data-size = 8;
reset.aoblock[1].block[0].reg-add-size = 8;
reset.aoblock[1].block[0].commands[0].0x42 = 0x5a;
reset.aoblock[1].block[0].commands[1].0x41 = 0xf8;
// SC7 exit
// Clear PMC_IMPL_DPD_ENABLE_0[ON]=0 during SC7 exit
reset.aoblock[2].command-retries-count = 1;
reset.aoblock[2].delay-between-commands-us = 256;
reset.aoblock[2].wait-before-start-bus-clear-us = 1;
reset.aoblock[2].block[0].type = 0; // MMIO Type
reset.aoblock[2].block[0].commands[0].0x0c360010 = 0x0;
// Shutdown in sensor/ao-tag
// no commands for other case
reset.sensor-aotag.aocommand[0] = 1;
reset.sc7.aocommand[0] = 2;