Pad Voltage DT Binding

Tegra pins and pads are designed to support multiple voltage levels at a given interface. They can operate at 1.2 volts (V), 1.8 V or 3.3 V. Based on the interface and power tree of a given platform, the software must write to the correct voltage of these pads to enable interface. If pad voltage is higher than the I/O power rail, then the pin does not work on that level. If pad voltage is lower than the I/O power rail, then it can damage the SoC pads. Consequently, configuring the correct pad voltage is required based on the power tree.

The Pad voltage DTSI is generated by using the pinmux spread sheet.

The prod configuration files are in the Linux_for_Tegra/bootloader/generic/BCT directory.

Here is the example of the DTS format of pad-voltage configuration file:

#define IO_PAD_VOLTAGE_1_2V 1200000
#define IO_PAD_VOLTAGE_1_8V 1800000
#define IO_PAD_VOLTAGE_3_3V 3300000
/dts-v1/;
/ {
          pmc@c360000 {
              io-pad-defaults {
                      sdmmc1_hv {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_3_3V>;
                      };

                          eqos {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
                      };

                      qspi {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
                      };

                      g2 {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_8V>;
                          };

                      ao_hv {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_3_3V>;
                      };

                      g9 {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_3_3V>;
                      };

                      ufs {
                              nvidia,io-pad-init-voltage = <IO_PAD_VOLTAGE_1_2V>;
                      };

              };
      };
};