Miscellaneous Configuration#

The different settings that do not fit into the other categories are documented in miscellaneous configuration file.

MB1 Feature Fields#

These features are Boolean flags that enable or disable functionality in MB1:

Field

Description

enable_dram_page_retirement

  • 0: Disable DRAM page retirement.

  • 1: Enable DRAM page retirement feature.

enable_dram_staged_scrubbing

  • 0: If DRAM ECC is enabled, scrub entire DRAM.

  • 1: If DRAM ECC is enabled, scrub DRAM in stages.

enable_tz_encryption

  • 0: Disable TZ encryption.

  • 1: Enable TZ encryption.

enable_vpr_encryption

  • 0: Disable VPR encryption.

  • 1: Enable VPR encryption.

disable_l2_tz_encryption_regeneration

  • 0: Enable L2 TZ encryption regeneration.

  • 1: Disable L2 TZ encryption regeneration.

disable_vpr_encryption_regeneration

  • 0: Enable VPR encryption regeneration.

  • 1: Disable VPR encryption regeneration.

enable_nsdram_encryption

  • 0: Disable NSDRAM encryption.

  • 1: Enable NSDRAM encryption.

enable_gsc_encryption

  • 0: Disable GSC encryption.

  • 1: Enable GSC encryption.

disable_gsc_encryption_regeneration

  • 0: Enable GSC encryption regeneration.

  • 1: Disable GSC encryption regeneration.

enable_vpr_resize

  • 0: Disable VPR resize.

  • 1: Enable VPR resize.

disable_fsi

  • 0: Enable FSI.

  • 1: Disable FSI.

disable_powergate_xusb

  • 0: Enable XUSB powergate.

  • 1: Disable XUSB powergate.

disable_die0_hpse_boot

  • 0: Enable die0 HPSE boot.

  • 1: Disable die0 HPSE boot.

disable_die1_hpse_boot

  • 0: Enable die1 HPSE boot.

  • 1: Disable die1 HPSE boot.

disable_die0_strongbox_boot

  • 0: Enable die0 strongbox boot.

  • 1: Disable die0 strongbox boot.

disable_die1_strongbox_boot

  • 0: Enable die1 strongbox boot.

  • 1: Disable die1 strongbox boot.

enable_ufs_init

  • 0: Disable UFS initialization.

  • 1: Enable UFS initialization.

enable_igpu

  • 0: Disable IGPU.

  • 1: Enable IGPU.

enable_wdt

  • 0: Disable watchdog timer.

  • 1: Enable watchdog timer.

enable_rcm_usb3

  • 0: Disable RCM USB3.

  • 1: Enable RCM USB3.

disable_wdt_globally

  • 0: Enable watchdog timer globally.

  • 1: Disable watchdog timer globally.

enable_pllref_ufs

  • 0: Disable PLLREF UFS.

  • 1: Enable PLLREF UFS.

enable_secondary_storage_in_mb1

  • 0: Disable secondary storage in MB1.

  • 1: Enable secondary storage in MB1.

die0_pmc_dpd_aux_unclamp

  • 0: Clamp die 0 PMC DPD aux.

  • 1: Unclamp die 0 PMC DPD aux.

die1_pmc_dpd_aux_unclamp

  • 0: Clamp die 1 PMC DPD aux.

  • 1: Unclamp die 1 PMC DPD aux.

enable_dram_error_injection_sbe

  • 0: Disable DRAM error injection SBE.

  • 1: Enable DRAM error injection SBE.

enable_dram_error_injection_dbe

  • 0: Disable DRAM error injection DBE.

  • 1: Enable DRAM error injection DBE.

enable_pcie_c2_ep

  • 0: Disable PCIE C2 EP.

  • 1: Enable PCIE C2 EP.

disable_snor_provisioning

  • 0: Enable SNOR provisioning.

  • 1: Disable SNOR provisioning.

disable_vmon_soc_min_reset

  • 0: Enable VMON SOC minimum reset.

  • 1: Disable VMON SOC minimum reset.

disable_vmon_soc_max_reset

  • 0: Enable VMON SOC maximum reset.

  • 1: Disable VMON SOC maximum reset.

disable_vmon_mss_min_reset

  • 0: Enable VMON MSS minimum reset.

  • 1: Disable VMON MSS minimum reset.

disable_vmon_mss_max_reset

  • 0: Enable VMON MSS maximum reset.

  • 1: Disable VMON MSS maximum reset.

disable_vmon_cpu_min_reset

  • 0: Enable VMON CPU minimum reset.

  • 1: Disable VMON CPU minimum reset.

disable_vmon_cpu_max_reset

  • 0: Enable VMON CPU maximum reset.

  • 1: Disable VMON CPU maximum reset.

disable_vmon_fsi_min_reset

  • 0: Enable VMON FSI minimum reset.

  • 1: Disable VMON FSI minimum reset.

disable_vmon_fsi_max_reset

  • 0: Enable VMON FSI maximum reset.

  • 1: Disable VMON FSI maximum reset.

enable_mcu_error_reporting

  • 0: Disable MCU error reporting.

  • 1: Enable MCU error reporting.

disable_boot_on_last_err

  • 0: Enable boot on last error.

  • 1: Disable boot on last error.

enable_reset_reason_reporting

  • 0: Disable reset reason reporting.

  • 1: Enable reset reason reporting.

num_boot_chains

  • Number of boot chains (0–3).

PSC-BL Synchronization Features#

T264 introduces PSC-BL (Platform Security Controller for Bootloader) synchronization features for enhanced security and multi-die support:

Field

Description

disable_preprod_firewalls

Disable pre-production firewalls for development.

enable_igpu_display_sdm

Enable IGPU display SDM (Security Domain Manager).

enable_mdm_mode

Enable MDM (Modem) mode for communication features.

disable_die0_fsi

Disable FSI (Fabric Switch Interface) on die 0.

disable_die1_fsi

Disable FSI on die 1.

enable_characterization_prep

Enable characterization preparation mode.

disable_sc7

Disable SC7 (system suspend) functionality.

disable_die0_igpufw_boot

Disable IGPU firmware boot on die 0.

disable_die1_igpufw_boot

Disable IGPU firmware boot on die 1.

log_level

Debug log level (0–15).

enable_special_thresholds

Enable special voltage and thermal thresholds.

Multi-SKU Support Configuration#

The T264 platform supports multi-SKU functionality for automatic SKU detection and configuration. When enabled, the system can automatically detect the SKU variant using GPIO pins and apply appropriate configurations.

Field

Description

test_sku_selection

Test SKU selection value for validation purposes (0–15).

num_sku_select_gpios

Number of GPIOs used for SKU selection (0–3).

sku_select_gpio_cfg_addr

GPIO configuration addresses for SKU selection pins.

sku_select_gpio_padctl_addr

GPIO pad control addresses for SKU selection pins.

The multi-SKU support allows different product variants to share the same base configuration while automatically applying variant-specific settings based on hardware strapping pins.

Clock Data#

The T264 platform provides enhanced clock configuration capabilities with support for multiple NAFLL instances and advanced clock management features.

Clock Feature Control#

Field

Description

switch_bpmp_clk_nafll

Switch BPMP clock to NAFLL:

  • 0: Use default clock source.

  • 1: Switch BPMP clock to NAFLL.

switch_mcf_to_nafll

Switch MCF to NAFLL:

  • 0: Use default clock source.

  • 1: Switch MCF clock to NAFLL.

bpmp_vmon_enable

Enable BPMP voltage monitor:

  • 0: Disable BPMP voltage monitoring.

  • 1: Enable BPMP voltage monitoring.

Clock Dividers#

Field

Description

bpmp_cpu_nic_clk_divisor

BPMP CPU NIC clock divisor.

bpmp_apb_clk_divisor

BPMP APB clock divisor.

axi_cbb_clk_divisor

AXI CBB clock divisor.

tz_se_clk_divisor

TZ SE clock divisor.

aon_apb_clk_divisor

AON APB clock divisor.

NAFLL Configuration#

The T264 platform supports multiple NAFLL (Noise-Aware FLL) instances:

NAFLL Instance

Description

BPMP NAFLL

NAFLL configuration for BPMP subsystem.

CPU NAFLL

NAFLL configuration for CPU cluster.

MCF NAFLL

NAFLL configuration for Memory Controller Fabric.

IST NAFLL

NAFLL configuration for IST subsystem.

SCF NAFLL

NAFLL configuration for System Controller Fabric.

CPU Clock Configuration#

Field

Description

scf_enable_nafll

Enable SCF NAFLL.

scf_enable_pllp

Enable PLLP for SCF.

cpu_enable_nafll

Enable CPU cluster NAFLL.

cpu_enable_pllx

Enable PLLX for CPU cluster.

Carveout Configuration#

Although SDRAM configuration has MC carveout’s preferred base, size and permissions, it does not have the information that is required to allocate the carveouts by MB1. This information is specified by using the miscellaneous configuration file.

For carveouts that are not protected by MC, all information (including size and preferred base address) is specified using the miscellaneous configuration file.

Each MC carveout configuration parameter has the following form:

/{
    misc {
        carveout {
            <carveout-type> {
                <parameter> = <value>;
            };
        };
    };
};

  • <carveout-type> identifies the carveout and is one of the following:

    Carveout Type

    Description

    gsc@[1–31]

    GSC carveout for various purposes.

    mts

    MTS/CPU-uCode carveout.

    tzdram

    TZDRAM carveout used for SecureOS.

    os

    OS carveout used for loading OS kernel.

    rcm

    RCM carveout used for loading RCM-blob during RCM mode (temporary boot carveout).

  • <parameter> is one of the following:

    Parameter

    Description

    pref_base

    Preferred base address of carveout.

    size

    Size of carveout (in bytes).

    alignment

    Alignment of base address of carveout (in bytes).

    ecc_protected

    When DRAM region-based ECC is enabled and there are non-ECC protected DRAM regions, whether to allocate the carveout from ECC protected region:

    • 0: Allocate from non-ECC protected region.

    • 1: Allocate from ECC protected region.

    bad_page_tolerant

    When DRAM page blacklisting is enabled, whether bad pages in the carveout are OK (only possible for very large carveouts that are handled completely by components that can avoid bad pages using SMMU/MMU):

    • 0: No bad pages allowed for the carveout.

    • 1: Bad pages allowed for the carveout. Allocation can be done without filtering bad pages.

    socket_mask

    Indicate the sockets on which the carveout will be allocated.

    allow_remote_access

    Indicate whether carveout access from remote sockets is allowed.

The valid combination of the carveouts and their parameters are specified in following table:

Supported carveout-type

pref_base

size

alignment

ecc_protected

bad_page_tolerant

socket_mask

allow_remote_access

gsc-[1–31] and mts

n/a

n/a

Yes

Yes

Yes

Yes

Yes

tzdram, mb2, cpubl, misc, os, and rcm

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Firmware Load and Entry Configuration#

The firmware configuration is specified as follows:

/{
    misc {
        ...
        firmware {
        <firmware-type> {
            <parameter> = <value>;
            };
        };
    };
};

In this syntax, <firmware-type> is one of the MB2 or TZDRAM-E13 and <parameter> is specified in the following table:

Field

Description

load-offset

Offset in the <firmware> carveout where <firmware> binary is loaded.

entry-offset

Offset of the <firmware> entry point in <firmware> carveout.

CPU Configuration#

The T264 CPU configuration is simplified compared to T234:

Field

Description

ccplex_platform_features

CCPLEX platform features configuration.

arb_weights

CPU UCF router arbitration weights for memory controller switches.

cpu_data_reserved

Reserved CPU data for future use.

Other Configuration#

Field

Description

carveout_alloc_direction

Carveout allocation direction:

  • 0: End of DRAM.

  • 1: End of 2-GB DRAM (32-bit address space).

  • 2: Start of DRAM.

i2c_bus_frequency

I²C bus frequencies in KHz for each controller (0–8).

pmc_rst_req_cfg

PMC reset request configuration.

wdt_period_secs

Watchdog timer period (1 ms to 1000 s).

rcm_usb3_port

RCM USB3 port configuration.

Debug Configuration#

The T264 debug configuration includes:

Field

Description

uart_instance

UART instance for debug output (0–3).

log_level

Debug log level (0–5):

  • 0: Disabled

  • 1: Critical

  • 2: Error

  • 3: Warning

  • 4: Info

  • 5: Debug

enable_kernel_first_ras

Enable kernel first RAS (Reliability, Availability, Serviceability).

UTC Parameters Configuration#

T264 includes UTC (Unified Trace Collector) parameter configuration:

Field

Description

disable_utc_fifo

Disable UTC FIFO functionality.

enable_utc

Enable UTC functionality.

default_rx_client

Default RX client configuration (0–15).

Frequency Monitor Controls#

Field

Description

vrefRO_calib_override

Override VrefRO calibration based on SoftFuse instead of fuse (Boolean).

vrefRO_min_rev_threshold

Program VrefRO frequency adjustment target based on FUSE_VREF_CALIB_0 if (FUSE_ECO_RESERVE_1[3:0] > vrefRO_min_rev_threshold). Used if vrefRO_calib_override is set to 0.

vrefRO_calib_val

VrefRO calibration value used to program VrefRO frequency adjustment target. Used if vrefRO_calib_override is set to 1.

osc_threshold_low

Lower threshold of the FMON counter for OSC clock.

osc_threshold_high

Upper threshold of the FMON counter for OSC clock.

pmc_threshold_low

Lower threshold of the FMON counter for 32K clock.

pmc_threshold_high

Upper threshold of the FMON counter for 32K clock.

fsi_threshold_low

Lower threshold of the FMON counter for FSI clock (minimum value 1996).

fsi_threshold_high

Upper threshold of the FMON counter for FSI clock (maximum value 6004).

Voltage Monitor Configuration#

The following voltage monitor domains are supported for monitoring and protection:

Voltage Domain

Description

vdd_soc

SOC voltage domain monitoring for core logic power supply.

vdd_cpu

CPU voltage domain monitoring for CPU cluster power supply.

vdd_mss

MSS (Memory SubSystem) voltage domain monitoring for memory controller power supply.

vdd_fsi

FSI (Fabric Switch Interface) voltage domain monitoring for interconnect power supply.

vdd_gpu

GPU voltage domain monitoring for graphics processing unit power supply.

Each voltage monitor domain supports the following configuration parameters:

Parameter

Description

sku_info

SKU information for voltage threshold selection.

vmin_threshold

Minimum voltage threshold for undervoltage protection.

vmax_threshold

Maximum voltage threshold for overvoltage protection.

TSC Controls Configuration#

T264 introduces Time Stamp Counter (TSC) controls for precise timing and synchronization:

Parameter

Description

tsc_capture_config_ptx

TSC capture configuration for PTX.

tsc_capture_control_ptx

TSC capture control for PTX.

tsc_locking_adjust_configuration

TSC locking adjustment configuration.

tsc_locking_control

TSC locking control settings.

tsc_locking_config

TSC locking configuration parameters.

IST OEM Authentication Keys#

T264 supports IST (In-System Test) OEM authentication keys for secure testing:

Parameter

Description

ist_rsa_pub_params

IST RSA public parameters (192 words).

ist_oem_cust_values

IST OEM custom values (16 words).

C2C Parameters Configuration#

T264 supports C2C (Chip-to-Chip) parameters for multi-socket configurations:

Parameter

Description

c2c_params

C2C parameters configuration for each socket.

Fuse Alias Data Configuration#

T264 supports fuse aliasing for various SKU configurations:

Parameter

Description

sku_type

SKU type identifier.

num_fuses

Number of fuses to alias.

fuses

Fuse configuration data, including offset and values.

UPHY Configuration#

T264 supports UPHY (Universal PHY) configuration:

Parameter

Description

uphy_config

UPHY configuration data for each socket, UPHY instance, and lane.

Voltage Regulator Configuration#

T264 supports voltage regulator configuration:

Parameter

Description

num_words

Number of configuration words.

data

Voltage regulator configuration data.

VDD Fuse Data Configuration#

T264 supports VDD fuse data configuration:

Parameter

Description

vdd_fuse_gpio_cfg_addr

VDD fuse GPIO configuration address.

vdd_fuse_gpio_padctl_addr

VDD fuse GPIO pad control address.

vdd_fuse_gpio_output_addr

VDD fuse GPIO output address.

toggle_vdd_fuse

Toggle VDD fuse flag.

Bandwidth Limiter Settings (MBWT)#

T264 supports Memory Bandwidth Throttling (MBWT) for MSS clients:

Parameter

Description

ctrl0

Bandwidth limiter settings control for MSS clients.

dram_freq_mhz

DRAM frequency in MHz.

data

MBWT configuration details for each client.

NVDISPLAY Configuration#

T264 supports NVDISPLAY PMC sticky-bit programming:

Parameter

Description

pmc_2sor0_force_internal

PMC 2SOR0 force internal.

pmc_2sor1_force_internal

PMC 2SOR1 force internal.

pmc_2sor_vpr_secure_mode

PMC 2SOR VPR secure mode.

Secondary Storage Configuration#

T264 supports secondary storage device information:

Parameter

Description

secondary_storage_dev

Secondary storage device information, including type and instance.

The miscellaneous configuration files are in the Linux_for_Tegra/bootloader/generic/BCT directory.

The following is a DTS example of the new miscellaneous configuration file:

/ {
    mb1_bct {
        psc_shared_features {
#ifdef ENABLE_MULTI_SKU_SUPPORT
            enable_multi_sku_support = <1>;
#else
            enable_multi_sku_support = <0>;
#endif
#ifdef DISABLE_PREPROD_FIREWALLS
            disable_preprod_firewalls = <1>;
#else
            disable_preprod_firewalls = <0>;
#endif
            enable_igpu_display_sdm = <0>;
            enable_mdm_mode = <1>;
            enable_special_thresholds = <0>;
        };
        non_psc_shared_features {
#if defined(ENABLE_DRAM_ECC_PRL)
            enable_dram_page_retirement = <1>;
#else
            enable_dram_page_retirement = <0>;
#endif
            enable_vpr_resize = <0>;
            carveout_alloc_direction = <1>;
            enable_tz_encryption = <1>;
            enable_vpr_encryption = <1>;
        };

        carveout {
            aux_info@CARVEOUT_CCPLEX_IST {
                size = <0x0 0x8000000>; // 128MB
                alignment = <0x0 0x200000>; // 2MB
                socket_mask = <0x3>;
                allow_remote_access = <1>;
            };
        };
        ///////// VMON ///////////
        vmon {
            vrefo_calib_override = <0>;
            vrefo_min_rev_threshold = <1>;
            vrefo_calib_val = <0>;
            min_adc_fuse_rev = <1>;
            vdd_soc {
                soc_vmon_config@0 {
                    sku_info = <0x00>;
                    vmin_threshold = <0x0F>; // 7 bit long
                    vmax_threshold = <0x72>; // 7 bit long
                };
                soc_vmon_config@1 {
                    sku_info = <0xA3>;       // TA1080SA
                    vmin_threshold = <0x15>; // 7 bit long
                    vmax_threshold = <0x72>; // 7 bit long
                };
            };
        };
    };
};