Changes and New Feature History

Bug Fixes

See Bug Fixes in this Firmware Version section.

Lane Margin

Lane Margin is a signal integrity diagnostic feature that measures the electrical “eye margin” of high-speed serial lanes, the physical data paths that carry bits over interfaces like PCIe, SerDes, or Ethernet links.

PCIe Trace Function

Added a new NVLOG TLV type to support PCIe logger functionality. This enhancement enables logging and debugging of PCIe-related events through the NVLOG infrastructure, improving traceability and issue analysis.

Passing Metadata Registers between the NIC Layer and the E-Switch (esw) Layer

This enhancement enables seamless metadata propagation across layers, allowing flow steering rules and packet processing logic to share contextual information such as flow identifiers, source context, or policy tags. It improves coordination between NIC and E-Switch pipelines, enabling more flexible traffic handling and advanced offload capabilities.

DPA (Data Path Accelerator) Partition Creation

Access control was added to ensure that only the VHCA instance that created a DPA partition is permitted to modify or delete it.

DPA Manifest

A new DPA Manifest mechanism was introduced to define and manage application permissions.

DPA TIMER

DPA TIMER functionality has been exposed through the MTCTR access register, allowing direct access by applications.

Parallel Suspends of VFs

Added support for parallel suspend operations across multiple VFs.

RTT RTC Timestamp

Added support for using the real-time clock to fill the request and response timestamps in hardware-generated RTT packets.

To enable this feature, set REAL_TIME_CLOCK_ENABLE in mlxconfig and configure ROCE_CC_RTT_TIMESTAMP_FORMAT to 0x02 (REAL_TIME) .

For additional details, see Known Issue 4496642 in the Known Issues section.

PCC NP IFA2 GNS

Enables customers to specify the corresponding GNS values that will be forwarded to the DOCA PCC NP feature. When multiple slots are configured with IFA2, the GNS settings in pcc_config and pcc_np_config must be identical across all slots using IFA2.

Enhanced Error Recovery for GGA QPs

When a GGA QP encounters a memory access (address translation) issue in one VM or Function, it no longer enters an error state. Instead, the QP now recovers from the error, sends an error CQE to the software, and continues serving other VMs and Functions.

Unlike RDMA QPs, the error CQE may redundantly reference a valid mkey, therefore, the software should re-construct all mkeys that received error CQE notifications.

Enable/Disable ECN in Upstream

Added the ability to enable or disable ECN in the upstream by allowing the MODIFY_CONG_STATUS and QUERY_CONG_STATUS commands in mlx5_fwctl.

Link Speed per-lane

Enabled 50G per-lane link speed and improved LED behavior for clearer network status indication. Traffic LED now blinks when traffic is active and reflects accurate link status.

Scan chain secondary LED behavior fixed, now correctly reflects link activity instead of remaining constantly on 900-9X85E-00EX-MJA.

API to Write PSP Master Key

Added a new API to write PSP Master Key. This API allows writing a new PSP Master Key, which will be used to generate new SPI/key pairs. The previous key remains valid for decryption until the key rotation process is completed.

ADP-RETX Timeout Profile

Firmware now allows the ADP-RETX timeout profile to be configured even when there are open QPs.

PCI Logs

PCI logs are now reported via the existing NC-SI OEM command Get Log Info (Command = 0x0, Parameter = 0x2F).

Adaptive Hot-plug System (AHS)

Added support for Adaptive Hotplug System (AHS) alongside the existing NHP solution, enhancing hotplug flexibility and system adaptability.

Additional STE Action

The ASO object pointer size has been increased from 24 bits to 32 bits, eliminating the previous limitation of ~16 million ASO objects per GVMI and enabling significantly greater scalability for future expansions.

NV Configuration

Added an NV configuration option to allow disabling XDR.

Note: Disabling SDR or enabling configurations not supported by the INI file remains unsupported.

MVCAP (Multi-Version Capability)

Added support for MVCAP (Multi-Version Capability) functionality enabling improved compatibility and version management across multiple components.

Bug Fixes

See Bug Fixes in this Firmware Version section.

Security Hardening Enhancements

This release contains important reliability improvements and security hardening enhancements. NVIDIA recommends upgrading your devices firmware to this release to improve the devices’ firmware security and reliability.

PCIe TLP Processing Hints (TPH) and Steering Tag (ST)

Enabled PCIe TLP Processing Hints (TPH) and Steering Tag (ST) during MKey creation.

Note: The steering tag index in the MKey creation must reference an MSIX entry containing the actual steering tag value.

PCIe Congestion Events

Added support for the general PCIe congestion object to monitor and receive events related to inbound and outbound PCIe congestion. A threshold can be configured to specify when the firmware should send an event to the software.

This capability is activated by setting the mlxconfig parameter PCIE_CONGESTION_MONITOR.

RDMA QP

When an RDMA QP encounters a memory access an issue caused by address translation, it can recover without transitioning to an error state. The QP will send an error CQE to notify the software while continuing to serve other VMs and functions.

PPCNT Counters

Firmware now supports new counters in the PPCNT register to track multicast and unicast packets transmitted and received. The counters include:

• port_multicast_xmit_pkts_high

• port_multicast_xmit_pkts_low

• port_multicast_rcv_pkts_high

• port_multicast_rcv_pkts_low

• port_unicast_xmit_pkts_high

• port_unicast_xmit_pkts_low

• port_unicast_rcv_pkts_high

• port_unicast_rcv_pkts_low

Safely Identify DPUs/SmartNICs is a Machine and PCIe Slot

A new access register is introduced that accepts a type, length, and R/W command.

• Write operation: Allocates a new ICMC buffer of the specified size (aligned to 64B) and stores the provided data. If a buffer for the given type already exists, the data in the ICMC is overwritten, and the locked area is adjusted accordingly

• Read operation: If a buffer exists, its data is copied out. If not, the access register returns a size of 0 or an explicit error

The length can be stored within the data in the ICMC, and the type is mapped to 256B chunks (due to access register limitations), so the VA of the buffer is calculated as (base + (type << 8)). The first 4 bytes store a validity flag and the length. If length storage is unnecessary (e.g., null-terminated data), a hardware read can use a cache-line hit as a validity bit.

This feature is designed for limited use cases and does not address multi-host scenarios or broader ICMC utilization implications.

Latency Histogram Counter

Introduced a new latency histogram counter that measures the distribution of read operation latencies from our device to the PCI link, providing better visibility into PCI read performance and potential bottlenecks.

Incoming NC-SI Messages Validation for the payload_len Field

Added an extra validation for the payload_len field in incoming NC-SI messages. Previously, invalid packets might have been accepted; now, such packets are silently dropped.

RSS with Crypto Offload

Added support for RSS with crypto offload enabling the NIC to parallelize packet processing across CPU cores while performing encryption/decryption in hardware. Additionally, introduced a new l4_type_ext parameter with values: 0 (None), 1 (TCP), 2 (UDP), 3 (ICMP).

SPDM

Updated SPDM measurements report to version 1.1.

Bug Fixes

See Bug Fixes in this Firmware Version section.

Bug Fixes

See Bug Fixes in this Firmware Version section.