What can I help you with?
NVIDIA ConnectX-8 SuperNIC User Manual

MCIO Harness Pinouts

The table below lists the MCIO connector pinouts of the MCIO harness included in the PCIe Auxiliary Kit. For the MCIO connector pinouts on the ConnectX-8 SuperNIC, refer to MCIO Interface.

Additional Electrical Information

Description/Direction

Pin

Pin

Description/Direction

Additional Electrical Information

GND

A1

B1

GND

PETp0

A2

B2

PERp0

PETn0

A3

B3

PERn0

GND

A4

B4

GND

PETp1

A5

B5

PERp1

PETn1

A6

B6

PERn1

GND

A7

B7

GND

Logic: Same power requirements as 3V3_AUX in PCIe spec

Voltage Level: 3.3V

3V3_AUX (IN)

A8

B8

SMBUS_SCL (IN)

Logic: Open-drain

Voltage Level: 3.3V

Presence of PU/PD: PU 100k ohm

Presence of PU/PD: PD termination 42.2 ohm

FLEXIO0_A

A9

B9

SMBUS_SDA (BID)

Logic: Open-drain

Voltage Level: 3.3V

Presence of PU/PD: PU 100k ohm

GND

A10

B10

GND

Logic: PCIe REFCLK IN

REFCLK_A_Dp (IN)

A11

B11

PERST_A_N (IN)

Logic: Push-pull, active low

Voltage Level: 3.3V

Logic: PCIe REFCLK IN

REFCLK_A_Dn (IN)

A12

B12

CBL_PRES_A (OUT)

Logic: Active low

Voltage Level: 3.3V

Presence of PU/PD: PD 200 ohm

Recommended implementation on System level: PU 100k ohm

GND

A13

B13

GND

PETp2

A14

B14

PERp2

PETn2

A15

B15

PERn2

GND

A16

B16

GND

PETp3

A17

B17

PERp3

PETn3

A18

B18

PERn3

GND

A19

B19

GND

PETp4

A20

B20

PERp4

PETn4

A21

B21

PERn4

GND

A22

B22

GND

PETp5

A23

B23

PERp5

PETn5

A24

B24

PERn5

GND

A25

B25

GND

Presence of PU/PD: PD termination 42.2 ohm

FLEXIO1_A/REFCLK_B_Dp

A26

B26

FLEXIO3_A/I2C_M_SDA_A (NC)

Presence of PU/PD: PD termination 42.2 ohm

Presence of PU/PD: PD termination 42.2 ohm

FLEXIO2_A/REFCLK_B_Dn

A27

B27

FLEXIO4_A/I2C_M_SCL_A (NC)

Presence of PU/PD: PD termination 42.2 ohm

GND

A28

B28

GND

Presence of PU/PD: PD termination 42.2 ohm

FLEXIO7_A

A29

B29

PERST_B_N (IN)

Presence of PU/PD: PD termination 42.2 ohm

Presence of PU/PD: PD termination 42.2 ohm

FLEXIO8_A

A30

B30

CBL_PRES_B (OUT)

Presence of PU/PD: PD termination 42.2 ohm

GND

A31

B31

GND

PETp6

A32

B32

PERp6

PETn6

A33

B33

PERn6

GND

A34

B34

GND

PETp7

A35

B35

PERp7

PETn7

A36

B36

PERn7

GND

A37

B37

GND

Key

GND

A38

B38

GND

PETp8

A39

B39

PERp8

PETn8

A40

B40

PERn8

GND

A41

B41

GND

PETp9

A42

B42

PERp9

PETn9

A43

B43

PERn9

GND

A44

B44

GND

PETp10

A45

B45

PERp10

PETn10

A46

B46

PERn10

GND

A47

B47

GND

PETp11

A48

B48

PERp11

PETn11

A49

B49

PERn11

GND

A50

B50

GND

PETp12

A51

B51

PERp12

PETn12

A52

B52

PERn12

GND

A53

B53

GND

PETp13

A54

B54

PERp13

PETn13

A55

B55

PERn13

GND

A56

B56

GND

PETp14

A57

B57

PERp14

PETn14

A58

B58

PERn14

GND

A59

B59

GND

PETp15

A60

B60

PERp15

PETn15

A61

B61

PERn15

GND

A62

B62

GND

© Copyright 2025, NVIDIA. Last updated on Jun 3, 2025.