Pin Description

The AOC is OSFP MSA Specification for OSFP Octal Small Form Factor Pluggable Module Rev. 1.12 compliant, see www.osfpmsa.org.

Pin

Symbol

Description

Pin

Symbol

Description

1

GND

Ground

31

GND

Ground

2

Tx2p

Transmitter Non-Inverted Data Input

32

Rx2p

Receiver Non-Inverted Data Output

3

Tx2n

Transmitter Inverted Data Input

33

Rx2n

Receiver Inverted Data

Output

4

GND

Ground

34

GND

Grounds

5

Tx4p

Transmitter Non-Inverted Data Input

35

Rx4p

Receiver Non-Inverted Data Output

6

Tx4n

Transmitter Inverted Data Input

36

Rx4n

Receiver Inverted Data

Output

7

GND

Ground

37

GND

Ground

8

Tx6p

Transmitter Non-Inverted Data Input

38

Rx6p

Receiver Non-Inverted Data Output

9

Tx6n

Transmitter Inverted Data Input

39

Rx6n

Receiver Inverted Data Output

10

GND

Ground

40

GND

Ground

11

Tx8p

Transmitter Non-Inverted Data input

41

Rx8p

Receiver Non-Inverted Data Output

12

Tx8n

Transmitter Inverted Data Input

42

Rx8n

Receiver Inverted Data Output

13

GND

Ground

43

GND

Ground

14

SCL

2-wire serial interface clock

44

INT / RSTn

Module Interrupt / Module Reset

15

VCC

+3.3V Power

45

VCC

+3.3V Power

16

VCC

+3.3V Power

46

VCC

+3.3V Power

17

LPWn / PRSn

Low-Power Mode / Module Present

47

SDA

2-wire Serial interface data

18

GND

Ground

48

GND

Ground

19

Rx7n

Receiver Inverted Data Output

49

Tx7n

Transmitter Inverted Data Input

20

Rx7p

Receiver Non-Inverted Data Output

50

Tx7p

Transmitter Non-Inverted Data Input

21

GND

Ground

51

GND

Ground

22

Rx5n

Receiver Inverted Data Output

52

Tx5n

Transmitter Inverted Data Input

23

Rx5p

Receiver Non-Inverted Data Output

53

Tx5p

Transmitter Non-Inverted Data Input

24

GND

Ground

54

GND

Ground

25

Rx3n

Receiver Inverted Data Output

55

Tx3n

Transmitter Inverted Data Input

26

Rx3p

Receiver Non-Inverted Data Output

56

Tx3p

Transmitter Non-Inverted Data Input

27

GND

Ground

57

GND

Ground

28

Rx1n

Receiver Inverted Data Output

58

Tx1n

Transmitter Inverted Data Input

29

Rx1p

Receiver Non-Inverted Data Output

59

Tx1p

Transmitter Non-Inverted Data Input

30

GND

Ground

60

GND

Ground

OSFP Module Pad Layout

image2022-1-12_13-27-13.png

The Active Optical Cable (AOC) pin assignment is SFF-8679 compliant.

Pin

Symbol

Description

Pin

Symbol

Description

1

Ground

Ground

20

Ground

Ground

2

Tx2n

Connected to Port 1 lane Rx2 Inverted Data

21

Rx2n

Connected to Port 1 lane Tx2 Inverted Data

3

Tx2p

Connected to Port 1 lane Rx2 Non-Inverted Data

22

Rx2p

Connected to Port 1 lane Tx2 Non-Inverted Data

4

Ground

Ground

23

Ground

Grounds

5

Tx4n

Connected to Port 2 lane Rx2 Non-Inverted Data

24

Rx4n

Connected to Port 2 lane Tx2 Inverted Data

6

Tx4p

Connected to Port 2 lane Rx2 Inverted Data

25

Rx4p

Connected to Port 2 lane Tx2 Non-Inverted Data

7

Ground

Ground

26

Ground

Ground

8

Mod-SelL

Cable Select

27

ModPrsL

Cable Present

9

ResetL

Cable Reset

28

IntL

Interrupt

10

Vcc Rx

+3.3V Power supply receiver

29

Vcc Tx

+3.3V Power supply transmitter

11

SCL

2-wire serial interface clock

30

Vcc1

+3.3V Power Supply

12

SDA

2-wire serial interface data

31

LPMode

Low Power Mode

13

Ground

Ground

32

Ground

Ground

14

Rx3p

Connected to Port 2 lane Tx1 Non-Inverted Data

33

Tx3p

Connected to Port 2 lane Rx1 Non-Inverted Data

15

Rx3n

Connected to Port 2 lane Tx1 Inverted Data

34

Tx3n

Connected to Port 2 lane Rx1 Inverted Data

16

Ground

Ground

35

Ground

Ground

17

Rx1p

Connected to Port 1 lane Tx1 Non-Inverted Data

36

Tx1p

Connected to Port 1 lane Rx1 Non-Inverted Data

18

Rx1n

Connected to Port 1 lane Tx1 Inverted Data

37

Tx1n

Connected to Port 1 lane Rx1 Inverted Data

19

Ground

Ground

38

Ground

Ground

QSFP56 Module Pad Layout

image2021-8-22_12-21-54.png

This AOC has CMIS 4.0 (check for update, e.g. to CMIS 5) compliant management interface and OSFP 4.1 (check for update) compliant form factor and interfaces. This implies that the control signals shown in the pad layout are implemented with the following functions:

Name

Function

Description

LPWn/PRSn

Input/output

Multi-level signal for low power control from host to module and module presence indication from module to host. This signal requires the circuit as described in the OSFP Specification [ ].

INT/RSTn

Input,/output

Multi-level signal for interrupt request from module to host and reset control from host to module. This signal requires the circuit as described in the OSFP Specification [ ].

SCL

BiDir

2-wire serial clock signal. Requires pull-up resistor to 3.3V on host.

SDA

Bidir

2-wire serial data signal. Requires pull-up resistor to 3.3V on host.

This AOC is SFF-8636 compliant. This means that the control signals shown in the pad layout support the following functions:

Name

Function

Description

ModPrsL

Output

Module Present pin, grounded inside the module. Terminated with pull-up in the host system. Asserted low when the transceiver is inserted, whereby the host detects the presence of the transceiver.

ModSelL

Input

Module Select, terminated high in the module. Only when held low by the host, the module responds to 2-wire serial communication commands. The ModSelL enables multiple modules to share a single 2-wire interface bus.

ResetL

Input

Reset, pulled high in the module. A low level on the ResetL pin for longer than the minimum pulse length (t_Reset_init) initiates a complete module reset, returning all user module settings to their default state. During reset the host shall disregard all status bits until the module indicates completion of the reset interrupt by asserting IntL signal low with the Data_Not_Ready bit negated. Note that on power up (including hot insertion) the module completes the reset interrupt without requiring a reset.

LPMode

Input

Low Power Mode input, pulled up inside the module. The transceiver starts up in low power mode, i.e. <1.5 W with the two-wire interface active. The host system can read the power class declaration from the transceiver and determine if it has enough power to enable the high-speed operation/high power mode of the transceiver. This can be done by asserting LPMode low or by use of the Power_over-ride and Power_set control bits (Address A0h, byte 93 bits 0,1).

IntL

OC output

Interrupt Low, terminated high in the host system. A “Low” indicates a possible module operational fault or a status critical to the host system, e.g. temperature alarm. The host identifies the source of the interrupt using the 2-wire serial interface. The INTL pin is de-asserted “High” after completion of reset, when byte 2 bit 0 (Data Not Ready) is read with a value of ‘0’.

SCL

BiDir

2-wire serial clock signal. Requires pull-up resistor to 3.3V on host.

SDA

Bidir

2-wire serial data signal. Requires pull-up resistor to 3.3V on host.

The low-speed signals are Low Voltage TTL (LVTTL) compliant (except for SCL and SDA signals).

The AOC complies with the SFF-8665 specification and has the following key features:

Physical layer link optimization:

  • Programmable Tx input equalization

  • Programmable Rx output amplitude

  • Programmable Rx output pre-emphasis

  • Tx/Rx CDR control
    by default enabled for 100 GbE operation, disable it for 40G operation

Digital Diagnostic Monitoring (DDM):

  • Rx receive optical power monitor for each lane

  • Tx transmit optical power monitor for each lane

  • Tx bias current monitor for each lane

  • Supply voltage monitor

  • Transceiver case temperature monitor

  • Warning and Alarm thresholds for each DDM function (not user changeable)

Other SFF-8636 functions and interrupt indications:

  • Tx & Rx LOS indication

  • Tx & Rx LOL indication

  • Tx fault indication

LOS, LOL, and Tx Fault status flags can be read via the two-wire management interface and are jointly transmitted via the IntL output pin. Relevant advertisement, threshold, and readout registers are found in the SFF-8636 MSA.

© Copyright 2023, NVIDIA. Last updated on Jan 16, 2024.