Pin Description
The transceiver’s pin assignment is SFF-8679 compliant.
Table 2: QSFP28 Pin Function Definition
|
Pin |
Logic |
Symbol |
Description |
Plug Sequence |
Notes |
|
1 |
GND |
Ground |
1 |
1 |
|
|
2 |
CML-I |
Tx2n |
Transmitter Inverted Data Input |
3 |
|
|
3 |
CML-I |
Tx2p |
Transmitter Non-Inverted Data Input |
3 |
|
|
4 |
GND |
Ground |
1 |
1 |
|
|
5 |
CML-I |
Tx4n |
Transmitter Inverted Data Input |
3 |
|
|
6 |
CML-I |
Tx4p |
Transmitter Non-Inverted Data Input |
3 |
|
|
7 |
GND |
Ground |
1 |
1 |
|
|
8 |
LVTTL-I |
ModselL |
Module Select |
3 |
|
|
9 |
LVTTL-I |
ResetL |
Module Reset |
3 |
|
|
10 |
Vcc Rx |
+3.3V Power Supply Receiver |
2 |
2 |
|
|
11 |
LVCMOS-I/O |
SCL |
2-wire serial interface clock |
3 |
|
|
12 |
LVCMOS-I/O |
SDA |
2-wire serial interface data |
3 |
|
|
13 |
GND |
Ground |
1 |
1 |
|
|
14 |
CML-O |
Rx3p |
Receiver Non-Inverted Data Output |
3 |
|
|
15 |
CML-O |
Rx3n |
Receiver Inverted Data Output |
3 |
|
|
16 |
GND |
Ground |
1 |
1 |
|
|
17 |
CML-O |
Rx1p |
Receiver Non-Inverted Data Output |
3 |
|
|
18 |
CML-O |
Rx1n |
Receiver Inverted Data Output |
3 |
|
|
19 |
GND |
Ground |
1 |
1 |
|
|
20 |
GND |
Ground |
1 |
1 |
|
|
21 |
CML-O |
Rx2n |
Receiver Inverted Data Output |
3 |
|
|
22 |
CML-O |
Rx2p |
Receiver Non-Inverted Data Output |
3 |
|
|
23 |
GND |
Ground |
1 |
1 |
|
|
24 |
CML-O |
Rx4n |
Receiver Inverted Data Output |
3 |
|
|
25 |
CML-O |
Rx4p |
Receiver Non-Inverted Data Output |
3 |
|
|
26 |
GND |
Ground |
1 |
1 |
|
|
27 |
LVTTL-O |
ModPrsL |
Module Present |
3 |
|
|
28 |
LVTTL-O |
IntL |
Interrupt |
3 |
|
|
29 |
Vcc Tx |
+3.3V Power supply transmitter |
2 |
2 |
|
|
30 |
Vcc1 |
+3.3V Power supply |
2 |
2 |
|
|
31 |
LVTTL-I |
LPMode |
Low Power Mode |
3 |
|
|
32 |
GND |
Ground |
1 |
1 |
|
|
33 |
CML-I |
Tx3p |
Transmitter Non-Inverted Data Input |
3 |
|
|
34 |
CML-I |
Tx3n |
Transmitter Inverted Data Input |
3 |
|
|
35 |
GND |
Ground |
1 |
1 |
|
|
36 |
CML-I |
Tx1p |
Transmitter Non-Inverted Data Input |
3 |
|
|
37 |
CML-I |
Tx1n |
Transmitter Inverted Data Input |
3 |
|
|
38 |
GND |
Ground |
1 |
1 |
Notes:
GND is the symbol for signal and supply (power) common for the QSFP28 module. All are common within the module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.
VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering see SFF-8679.
QSFP28 Module Pad Layout:
The MMS1V70 is SFF-8636 compliant, thus the control signals shown in the pad layout are implemented with the following functions:
|
ModPrsL |
Output, asserted low |
Pull-up by host when no transceiver/cable is present. Connected to ground inside the transceiver. Hence, asserted low when a transceiver/cable is plugged in. |
|
ModSelL |
Input, asserted Low |
Module Select input pin, terminated high in the module. Only when held low by the host, the module responds to 2-wire serial communication commands. The ModSelL enables multiple modules to share a single 2-wire interface bus. |
|
ResetL |
Input, asserted Low |
Reset input pin, pulled high in the module. A low level on the ResetL pin for longer than the minimum length initiates a module reset. When de-asserted the transceiver starts its initialization procedure. See the CMIS specification Error! Reference source not found. for details. |
|
LPMode |
Input, asserted high |
Low Power Mode input, pulled up inside the module. Hardware control signal for forcing the transceiver into low-power state. Can be overwritten by low-power mode command. |
|
IntL |
Output, asserted low |
Interrupt Low is an open-collector output, terminated high in the host system. A “Low” indicates a possible module operational fault or a status critical to the host system, e.g. temperature alarm. The host identifies the source of the interrupt using the 2-wire serial interface. |
The low-speed signals are Low Voltage TTL (LVTTL) compliant (except for SCL and SDA signals).
The transceiver complies with the SFF-8665 specification and has the following key features:
Physical layer link optimization:
Programmable Tx input equalization
Programmable Rx output amplitude
Programmable Rx output pre-emphasis
Tx/Rx CDR control
by default enabled for 100 GbE operation, disable it for 40G operation
Digital Diagnostic Monitoring (DDM):
Rx receive optical power monitor for each lane
Tx transmit optical power monitor for each lane
Tx bias current monitor for each lane
Supply voltage monitor
Transceiver case temperature monitor
Warning and Alarm thresholds for each DDM function (not user changeable)
Other SFF-8636 functions and interrupt indications:
Tx & Rx LOS indication
Tx & Rx LOL indication
Tx fault indication
LOS, LOL, and Tx Fault status flags can be read via the two-wire management interface and are jointly transmitted via the IntL output pin. Relevant advertisement, threshold, and readout registers are found in the SFF-8636 MSA.