38 #define PRINT_QSPI_DBG_MESSAGES(...) pr_info(__VA_ARGS__)
39 #define PRINT_QSPI_REG_ACCESS(...) pr_info(__VA_ARGS__)
41 #define PRINT_QSPI_DBG_MESSAGES(...)
42 #define PRINT_QSPI_REG_ACCESS(...)
46 #define QSPI_CONTROLLERS_MAX 2
48 #define QSPI_CONTROLLERS_MAX 1
58 #define QSPI_MAX_BIT_LENGTH 31
59 #define QSPI_8Bit_BIT_LENGTH 7
60 #define QSPI_FIFO_DEPTH 64
61 #define BYTES_PER_WORD 4
64 #define QSPI_HW_TIMEOUT 100000
NvU32 QuadState
Quad state.
QspiOpMode_t OpMode
DDR or SDR mode taken from the DT/ board file.
NvU32 Mode
QSPI X1 or X2 or X4 xfer mode.
NvU32 ChipSelectLevel
CS assert level, Active Low or Active High.
Holds QSPI Transfer data.
NvError NvQspiTransaction(QspiTransfer *Transfers, NvU8 Numoftransfers, NvU32 Instance)
Performs QSPI transactions for write and read.
struct QspiTransfer QspiTransfer
Holds QSPI Transfer data.
NvU32 Instance
QSPI hardware controller instance.
NvU8 * Txbuf
TX buffer address.
Holds QSPI hardware controller context data.
NvU8 * Rxbuf
RX buffer address.
NvU32 CyclesBwPkts
Idle clock cycles between two packets.
QspiOpMode_t OpMode
DDR or SDR mode of xfer.
NvU32 ReadStartTimeinUs
Time at which the read xfer is started.
1 [IO on rising and falling edge of clock]
QspiXferType_t
Defines the transfer types.
QspiBusWidth
Defines the QSPI bus widths.
QspiOpMode_t
Defines the QSPI controller and Flash chip operating mode.
void NvQspiShutdown(NvU32 Instance)
Shuts down the QSPI controller.
NvU32 CSActiveBwPkts
For software type CS, 1 enables the CS.
NvU32 BaseAddr
QSPI hardware register base address.
NvU32 BusWidth
QSPI controller FIFO width.
NVIDIA Quickboot Interface: Error Handling (Parker)
NvU32 RxClkTapDelay
Rx TAP delay for sampling data.
NvU32 DummyCycles
Clock cycles between two transaction.
NvU32 DmaClient
Time at which the read xfer is started.
NvU32 WriteStartTimeinUs
Time at which the write xfer is started.
0 [IO on single edge of clock]
NvU32 Speed_hz
QSPI clock frequency.
NVIDIA Quickboot Interface: Device Drivers
NvU32 DmaChannel
GPCDMA channel number if DMA is enabled for QSPI IO.
QspiXferType_t type
ASYNC or SYNC xfer.
NvQspiChipSelect
Defines the QSPI chip selection.
NvU32 TxClkTapDelay
Tx TAP delay for sampling data.
NvError NvQspiInit(void *pdata)
Initializes the specified QSPI controller.
void QspiDumpRegisters(NvU32 Instance)
Dumps the registers of the QSPI controller.
NvError QspiHwProcReadAsyncWaitDMAComplete(NvU32 Instance)
Waits until the IO from the DMA is complete.