Self-Qualification Packet — Submission Procedure

Step-wise administrative procedure for a BESS partner to assemble and submit a self-qualification packet to NVIDIA. This procedure defines the qualification pathways, ordered packet artifact structure, and per-test evidence map covering all twelve qualification tests.

Companion to: BESS Self-Qualification Guidelines
Audience: BESS Partners and NVIDIA Reviewers
Correspondence: Single channel—Partner and NVIDIA

Governing Principle—Single Channel of Correspondence

The BESS Partner (OEM) owns compliance and is NVIDIA’s sole point of contact. Regardless of who executes the tests, all correspondence, submissions, and clarifications flow only between the BESS Partner and NVIDIA. Test labs and third-party experts are subcontracted to the partner and never correspond with NVIDIA directly.

Figure 1 Correspondence Model

Single Channel Rule

No lab-to-NVIDIA correspondence is permitted. Testing and expertise are subcontracted to the BESS Partner.

NVIDIA Reviewer: Corresponds only with the BESS Partner.
BESS Partner (OEM): Owns compliance and subcontracts labs/experts as needed.
Lab/Experts: Work for the partner only; no direct lab-to-NVIDIA correspondence.

Qualification Pathways

The partner may choose one pathway for all tests, or mix pathways by test.

Figure 2 Pathway Selection

Mixed Pathways Permitted

A partner may mix pathways per test (for example, self-perform Tests 1 to 3, run EMT validation by EPRI, and perform ride-through at Flat Iron). Any third-party work must include signed attestation in Artifact 10.

Step-Wise Administrative Procedure

The following timeline defines the end-to-end administrative workflow, from partner intake through NVIDIA disposition.

Process Timeline

Step	Owner	Action	Output
0	Partner	Register & Intake: Register intent, execute NDA, open NVOnline record	Submission record ID
1	Partner	PRD Response: Respond line by line to PRD Table 2 (Core Requirements): Comply / Deviate / Exception	PRD response matrix
2	Partner	Disclosures: Complete materials, safety, and compliance disclosures	Disclosure set
3	Partner	Select Pathway(s): Select pathway A/B/C per test; contract lab/experts if used	Test plan and scope attestation
4	Partner / Lab / Expert	Execute 12 Tests: Execute all twelve qualification tests (hardware, HIL, and model-only as specified)	Raw data and plots per Appendix A
5	Partner	Assemble Packet: Assemble packet in required 00-10 artifact order	Complete self-qualification packet
6	Partner	Submit: Submit package via NVOnline (Appendix E steps)	Submitted packet and notification
7	Partner and NVIDIA	Review & Clarification: Resolve review comments through single channel	Resolved review log
8	NVIDIA	Disposition: Issue disposition: Qualified / Conditional / Gaps	Qualified products may be listed on Marketplace (best effort)

Prescribed Packet Artifact Order

Submit as a single indexed package (folders or a bookmarked PDF) using exactly this numbering. Each folder maps to a section of the guidelines so reviewers can navigate directly to governing requirements.

Order	Artifact	Contents / Source
00	Cover sheet and submission letter	Partner, product/model, firmware version, submission ID, pathway(s), single POC
01	Core Requirements Checklist	Appendix B mapping: Core Requirement -> Test IDs -> Evidence reference (reviewer’s index)
02	PRD Response Matrix	Product Requirements Doc—line-by-line response to PRD Table 2 Core Requirements: Comply / Deviate / Exception
03	Materials, Safety and Compliance Disclosures	Disclosure tables from Step 2
04	Standards and Regulatory Certificates	Appendix D: IEEE 1547/2800, UL 9540/9540A, NFPA 855, CE/UKCA, IEC 62443, etc.
05	Test Reports 1-12	One subfolder per test (05-01 to 05-12), each containing Appendix A evidence set
06	EMT / Model Package	Appendix C: EMT model, dq impedance plots, Nyquist/passivity artifact, version-controlled parameter export
07	Business and Supply Chain Readiness	Section 4: throughput, 10×/24-month scale plan, supply-chain risk, failure-mode acknowledgment
08	Quality and Reliability	Section 5: QMS/traceability, reliability targets & model, environmental/durability, FAT/burn-in, serviceability
09	Deviations and Known-Issues Log	Consolidated list across all tests (Appendix A requirement)
10	Third-Party Attestation	Signed statement from Lab/Expert (Path B/C): scope, methods, independence. N/A for Path A

Required Contents for Each Test Report (Folder 05-XX)

This report must be presented in the following order.

Test configuration (single-line + controller settings + SOC)
Raw time-series data (CSV)
Summary plots (PDF)
Pass/Fail statement tied to criteria
Known issues and deviations (Appendix A)

Test Coverage and Location Map

Test	Title	Type	Report Folder
1	Telemetry Verification and Data Integrity	Hardware (grid-connected)	05-01
2	Grid-Adaptive V/f Regulation (Islanded)	Hardware (islanded bus)	05-02
3	Current-Limit Characterization (P-first / Q-first / Mixed)	Hardware	05-03
4	AI Load Buffering / Ramp-Rate Smoothing	Hardware	05-04
5	EMT Validation (weak grid, SCR sweep)	Model-only (Appendix C)	05-05 + 06
6	Demand Response (DR) Dispatch	Hardware	05-06
7	LVRT / HVRT Ride-Through	Hardware	05-07
8	Grid to Island Transition	Hardware	05-08
9	Generator Following	Hardware	05-09
10	Black Start	Hardware	05-10
11	SOC Drift / Energy Balance	Hardware	05-11
12	Control Transparency	Hardware + Model	05-12 + 06

Instrumentation Requirements

Instrumentation minimums (accuracy, sampling rate, and pre/post-trigger windows) from Step 4 of the BESS Qualification Overview section apply to all tests and must be evidenced in each report configuration section (05-XX, item 1).