Pinmux and GPIO Configuration#

The pinmux configuration file provides pinmux and GPIO configuration, which is generated by using the pinmux spreadsheet.

The pinmux DTS file is in the Linux_for_Tegra/bootloader/generic/BCT directory.

The following is the DTS format example of a pinmux configuration file:

#include "t264-pinctrl-tegra.h"

#include "./tegra264-mb1-bct-gpio-p3960-0010.dtsi"

pinmux@ac281000 {
                common {
                        /* SFIO Pin Configuration */
                        shutdown_n {
                                nvidia,pins = "shutdown_n";
                                nvidia,function = "shutdown_n";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        gen2_i2c_scl_pcc0 {
                                nvidia,pins = "gen2_i2c_scl_pcc0";
                                nvidia,function = "i2c2_clk";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        gen2_i2c_sda_pcc1 {
                                nvidia,pins = "gen2_i2c_sda_pcc1";
                                nvidia,function = "i2c2_dat";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        gen3_i2c_scl_pcc2 {
                                nvidia,pins = "gen3_i2c_scl_pcc2";
                                nvidia,function = "i2c3_clk";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };

                        gen3_i2c_sda_pcc3 {
                                nvidia,pins = "gen3_i2c_sda_pcc3";
                                nvidia,function = "i2c3_dat";
                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
                                nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
                                nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
                        };
            ⋮

The following is the DTS format example of a GPIO configuration file:

#include "tegra264-gpio.h"

gpio@ac300000 {
         default {
                gpio-input = <
                        TEGRA264_MAIN_GPIO(F, 7)
                        TEGRA264_MAIN_GPIO(G, 0)
                        TEGRA264_MAIN_GPIO(H, 2)
                        TEGRA264_MAIN_GPIO(H, 3)
                        TEGRA264_MAIN_GPIO(H, 4)
                        TEGRA264_MAIN_GPIO(H, 5)
                        TEGRA264_MAIN_GPIO(J, 7)
                        TEGRA264_MAIN_GPIO(K, 0)
                        TEGRA264_MAIN_GPIO(K, 1)
                        TEGRA264_MAIN_GPIO(K, 2)
                        TEGRA264_MAIN_GPIO(K, 3)
                        TEGRA264_MAIN_GPIO(K, 4)
                        TEGRA264_MAIN_GPIO(K, 5)
                        TEGRA264_MAIN_GPIO(M, 0)
                        TEGRA264_MAIN_GPIO(P, 7)
                        TEGRA264_MAIN_GPIO(Q, 0)
                        TEGRA264_MAIN_GPIO(Q, 1)
                        TEGRA264_MAIN_GPIO(Q, 4)
                        TEGRA264_MAIN_GPIO(S, 1)
                        TEGRA264_MAIN_GPIO(T, 6)
                        TEGRA264_MAIN_GPIO(U, 1)
                        TEGRA264_MAIN_GPIO(Y, 6)
                        TEGRA264_MAIN_GPIO(Z, 0)
                        TEGRA264_MAIN_GPIO(Z, 5)
                        TEGRA264_MAIN_GPIO(Z, 6)
                        TEGRA264_MAIN_GPIO(Z, 7)
                        TEGRA264_MAIN_GPIO(AL, 0)
                        TEGRA264_MAIN_GPIO(AL, 1)
                        >;
                gpio-output-low = <
                        TEGRA264_MAIN_GPIO(H, 0)
                        TEGRA264_MAIN_GPIO(H, 1)
                        TEGRA264_MAIN_GPIO(H, 6)
                        TEGRA264_MAIN_GPIO(H, 7)
                        TEGRA264_MAIN_GPIO(J, 1)
                        TEGRA264_MAIN_GPIO(J, 2)
                        TEGRA264_MAIN_GPIO(L, 2)
                        TEGRA264_MAIN_GPIO(U, 7)
                        TEGRA264_MAIN_GPIO(V, 7)
/* C2C x2 mode, set pin low */
#ifdef ENABLE_C2C_X2_MODE
                        TEGRA264_MAIN_GPIO(W, 0)
#endif
                        >;
                gpio-output-high = <
                        TEGRA264_MAIN_GPIO(F, 0)
                        TEGRA264_MAIN_GPIO(F, 1)
                        TEGRA264_MAIN_GPIO(F, 2)
                        TEGRA264_MAIN_GPIO(J, 0)
                        TEGRA264_MAIN_GPIO(L, 3)
                        TEGRA264_MAIN_GPIO(Q, 2)
                        TEGRA264_MAIN_GPIO(Q, 3)
                        TEGRA264_MAIN_GPIO(Q, 5)
                        TEGRA264_MAIN_GPIO(R, 0)
                        TEGRA264_MAIN_GPIO(U, 3)
                        TEGRA264_MAIN_GPIO(U, 4)
                        TEGRA264_MAIN_GPIO(U, 5)
/* C2C x4 mode, set pin high */
#ifndef ENABLE_C2C_X2_MODE
                        TEGRA264_MAIN_GPIO(W, 0)
#endif
                        TEGRA264_MAIN_GPIO(W, 1)
                        TEGRA264_MAIN_GPIO(AL, 2)
                        >;
        };
};