Jetson Thor Series

NVIDIA^® Jetson™ Linux supports these software features, which provide users a complete package to bring up Linux on Jetson Thor devices.

Bootloader

Bootloader Binary	Feature	Notes
BPMP processor boot binaries	Storage location	Cold boot: QSPI RCM boot: Downloaded over USB recovery port
	Next stage storage location	Cold boot: QSPI RCM boot: Downloaded over USB recovery port
	Next stage	UEFI
	Storage device support	QSPI
	Partition table support	GPT (with protective MBR)
	File system support	None
	I/O bus support Console UART	I2C

Toolchain

Feature	Tool chains	Notes
Aarch64	gcc-13.2-glibc-2.28	For 64-bit kernel and user space

Kernel

Interface	Feature
Linux kernel	Version 6.8.12

Camera Interface

Platform	Interface	Feature	Notes
Jetson Thor	Camera support (MGBe input support)	SIPL (Safe Image Processing Library) [With HW ISP & MGBe]	MGBe0, MGBe1, MGBe2, MGBe3

Note

We recommend using a camera with a frame rate of less than or equal to 60 FPS.

LSIO

Module	Feature	Notes
UART	PIO mode	FIFO access using CPU.
	DMA mode	FIFO access using DMA.
	Hardware-/software-based flow control	Flow control line toggling from hardware or software.
	Buffer throttling	Flow control based on data in receive buffer.
	RX and TX DMA mode selection	DMA mode transfer on RX and TX or on only one path.
	Interrupt mode	Data transfer complete handling through interrupt.
	Polling mode	Data transfer complete handling through polling.
	MCR control	Modem control access.
	Baud rate/port configuration	Changing port configuration.
	Baud rate adjustment	Adjusting baud rate to fall within tolerance range.
I2C controller	Speed mode (standard, FM, FM+)
	Repeat start	Repeat start on transfer of data.
	No start	No address cycle after repeat start.
	Packet mode
	Normal/byte mode
	7-bit/10-bit addressing mode	7-bit/10-bit addressing mode.
	DMA mode	APB/GPC DMA for FIFO access.
	Clock gating and clock always on	Clock control after each transfer for power saving.
	Runtime PM	Runtime power management.
	Dynamic clock speed change	Change speed of the bus.
	Interrupt-based	Transfer complete handling using interrupt.
	Polling	Transfer complete handling using polling.
	Bit banging for data transfer	Use GPIO APIs for data transfer.
	Multiple transfer request	Multiple transfer request.
	Bus clear support	Bus clear handling when bus is held by
	>4K on software-based split	>4K on software-based split.
	>64K on software-based split	>64K on software-based split.
SPI controller	Packed/unpacked	Data can be put on FIFO in packed or unpacked format. Packed format reduces the number of I/O accesses on FIFO.
	Full duplex mode	Device can read and write data simultaneously.
	Least significant bit	Option to send least significant bit first from packets.
	Dual SPI	SPI PICO/POCI (previously MOSI/MISO) can act as RX and TX.
	Least significant byte first	Option to send least significant byte first from packets.
	Hardware-based CS control and CS setup/hold time	Hardware control the CS and maintain CS setup and hold time.
	Software or hardware chip select polarity section	Chip select can be active high or active low based on the external device property.
	Supported modes 0–3	SPI communication support mode 0, 1, 2, or 3.
	DMA mode	Data written to and read from FIFO using DMA mode.
	PIO (non-DMA) mode	CPU has direct access to FIFO for read and write.
	GPIO-based chip select	CS line is controlled by the GPIO APIs.
	SPI different clock rates	Set the interface clock speed based on what device can support.
	Prod configuration	Platform-/chip-specific configuration of controller and interface.
	Clock delay between packets	Provision for delay between packets.
	Clock gating and clock always on	Dynamic clock enable/disable for power save.
	Runtime PM	Runtime power management.
	Interrupt-based	Transfer-done handling through interrupt.
	Polling	Transfer-done handling through polling.
	Different packet bit length
	Multiple-transfer request	Multiple SPI transfer request from a single call.
GPIO	GPIO request/free	GPIO access permission.
	Pinmux integration with GPIOS	GPIO APIs call pinmux for required pin configuration.
	Direction set/get	GPIO direction configuration.
	Value set/get	GPIO value set to pin and get from pin.
	Interrupt support from all pins
	Wake-up support for SC7
	GPIO register dump
	Support for libgpiod library and tools
	Suspend/resume
Pinmux	Function configuration	Pinmux function configuration.
	Pinmux configuration	Configuration of various pinmux properties, such as pull up/pull down, input, and tristate.
	Suspend/resume	Save and restore pinmux context.
	Drive strength	Drive strength configuration of pins.
	Prod setting
	Static pinmux configuration
	Dynamic pinmux configuration
	Pinmux register dump
	Pinmux configuration dumping
	Pinmux-GPIO integration
APBDMA/ GPCDMA	Memory to memory
	Memory to I/O
	I/O to memory
	Cyclic-once mode
	Transfer done through interrupt mode
	Multiple transfer requests	Queue mechanism for transfer requests.
Watchdog	Watchdog framework support
	System reset on CPU hang	System reset on WDT expiry.
	Suspend/resume support	Suspend/resume handling.
	Watchdog interrupt support	WDT reset on ISR.
	Watchdog polling/ping support	WDT start/stop/pin from user space.
PWM	PWM ops	PWM registration to framework.
	Prod setting	Tegra-specific controller configuration.
	Clock accuracy calculation
PMC	Controlling I/O PAD voltage (PWR_DETECT)	Pad voltage configuration by software.
	I/O DPD configuration	Deep power-down configuration.
	IO_NOPOWER through regulator	IO_NOPOWER configuration.
	Read/write PMC registers	PMC register access interface.
	PMC config for BootROM I2C	PMC configuration for BootROM I2C/MMIO commands.
	PMC LED blink	PMC provides the control for blinking LED, including in deep-sleep mode. The blinking control is a PWM signal.
	PMC soft LED breathing	PMC soft LED breathing to control LED ramp up, ramp down, and on time.
Tachometer	Read RPM
BPMP I2C controller	Speed mode (standard, FM, FM+)	Bus speed configuration.
	Packet mode	I2C controller configuration in packet mode.
	Normal/byte mode	I2C controller configuration in normal mode.
	7-bit/10-bit addressing mode
	DMA mode	I2C FIFO access through APB DMA.
	Bus-clear support	Bus-clear handling when bus is held by device.
UTC-UART	PIO mode	FIFO access using CPU.
	DMA mode	FIFO access using DMA.
	Hardware flow control	Flow control line toggling from hardware and software.
	FIFO mode	FIFO mode of UART controller.
SPE DMA	Memory to memory
	Memory to I/O
	I/O to memory
	Continuous mode support	Cyclic mode.
I2C SLAVE	Normal/byte mode	I2C controller configuration in normal mode.
	FIFO mode	I2C controller configuration in FIFO mode.
	7-bit addressing	7-bit addressing.
	10-bit addressing	10-bit addressing.
	Repeat start	Repeat start on transfer of data.
	Clock stretching	Clock line stretching.
CAN 2.0 A (only available on FSI domain)	CAN FD	CAN FD increases the maximum data throughput to ~3.7 Mbps. 10 Mbps over 10 meters. Maximum signal frequency: 15 Mbps.
	TX Standard CAN message	TX Standard CAN with 11-bit message message identifiers, originally specified to operate at a maximum frequency of 250 Kbps. Maximum signal frequency: 1 Mbps. Available bitrates: 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	RX Standard CAN message	RX Standard CAN with bitrates of 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	TX+RX Standard CAN message	TX+RX Standard CAN with bitrates of 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	TX Extended CAN message	TX Extended CAN with 29-bit message identifiers, originally specified to operate at a maximum frequency of 1 Mbps. Available bitrates: 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	RX Extended CAN message	RX Extended CAN with bitrates of 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	TX+RX Extended CAN message	TX+RX Extended CAN with bitrates of 125 Kbps, 250 Kbps, 500 Kbps, and 1 Mbps.
	CAN loopback	Internal controller loopback.
	Standard FD (BRS/non-BRS)	Standard FD frame with bitrate switching and non-bitrate switching.
	Extended FD (BRS/non-BRS)	Extended FD frame with bitrate switching and non-bitrate switching.
	Timestamping	Timestamp generation of TX/RX frames.
	Listen-only mode	Listen-only mode to monitor CAN bus.
	Restart bus-off	Restart bus after CAN bus-off state.
QSPI	Interface widths	Single, Dual, and Quad supported.
	SDR and DDR modes	Data rates on one or both clock edges.
	Bit lengths	Packets of 8, 16, and 32 bits supported.
	Transfer mode 0	Transfer mode 0 for SDR and DDR.
	DMA/PIO mode selection	Option to select data written to or read from FIFO using DMA or CPU.
	Packed/unpacked	Data can be put in packed or unpacked format on FIFO. Packed format reduces the number of I/O accesses.
	Endianness LSByte and LSBit	Option to send least-significant byte or bit first from packet.
	Hardware-based chip select control and CS setup/hold time	Hardware control of chip select pin and CS setup and hold time.
	Software or hardware chip select polarity selection	Chip select can be active high or active low based on the external device property.
	Combined sequence mode	CDM, ADDR, and DATA transferred in single GO resulting in single interrupt.
	Various clock rates	Set the interface clock speed based on what device can support.
	Golden Register settings	Platform-/chip-specific configuration of controller and interface.
	Active clock delay between packets	Provision to have delay between packets.
	Runtime power management

HSIO

Module	Feature	Notes
Ethernet (Realtek R8126)	NFS boot
	WOL or remote Wakeup
	TCP Segmentation Offload support (TSO)
	TCP/UDP Checksum offload
	IEEE 802.1Q VLAN tagging
	IEEE 802.1P Layer 2 Priority Encoding
	Receive-Side Scaling (RSS)
	Jumbo frame to 9 KB
	Suspend/resume support over NFS
	Iperf throughput on 5G link
PCIe	Controllers with x8 link width	Max x8 link width (few controllers).
	Controllers with x4 link width	Max x4 link width (few controllers).
	Controllers with x2 link width	Max x4 link width (few controllers).
	Controllers with x1 link width	Max x1 link width (few controllers).
	Legacy interrupts	Applicable to all controllers.
	MSI & MSI-X interrupts	Applicable to all controllers.
	128-byte maximum payload size	Applicable to all controllers.
	256-byte maximum payload size	Applicable to all controllers.
	Gen-1 speed	Applicable to all controllers.
	Gen-2 speed	Applicable to all controllers.
	Gen-3 speed	Applicable to all controllers.
	Gen-4 speed (not applicable to Orin Nano)	Applicable to all controllers.
	Advanced error reporting (AER)	Applicable to all controllers.
	DMA support in Root Port	Applicable only to C2, C4 and C5 controllers.
	Endpoint mode support	C4 and C5 controllers.
SDMMC	DR50	eMMC interface running in DDR mode at 50 MHz.
	HS200	eMMC interface running in SDR mode at 200 MHz.
	HS400	eMMC interface running in DDR mode at 200 MHz.
	HS533	eMMC interface running in DDR mode at 267 MHz.
	HW tuning	Supports tuning in SDMMC controller.
	Packed commands	Read and write commands can be packed in groups (either all read or all write) that transfer data for all commands in the group in one transfer on the bus, to reduce overhead.
	Cache	Similar to CPU cache, but implemented in eMMC; helps improve performance.
	Discard	Erases data if necessary during background erase events.
	Sanitize	Physically removes data from unmapped user address space.
	RPMB	Secure access.
	BKOPS	Allows execution of background operations when host is not being serviced.
	HPI	High-priority interrupt to stop ongoing background operations and reliable writes.
	Power-off notification	Allows device to prepare itself to power off properly and improve user experience during power-on.
	Sleep	Minimizes power consumption of the eMMC device.
	RTPM	Software feature to save power by switching off clocks when no transactions are on the bus.
	Field firmware upgrade	Update eMMC firmware.
	Device Life Estimation types A and B	Device Health is a mechanism to get vital NAND flash program/erase cycles information as a percentage of useful flash lifespan. Type A: SLC device health information. Type B: MLC device health information.
	PRE EOL information	Provides indication about device lifetime reflected by average reserved blocks.
	Hardware command queue	Performed by SD/MMC controller.
	Enhanced strobe mode (ESM) in HS400 mode	Optional for devices; indicated by STROBE_SUPPORT[184] register of EXT_CSD.
	eMMC CQ CQIC feature	Generates coalesced interrupts when the interrupt coalescing mechanism is enabled.
	Suspend/resume and shutdown
UFS	PWM-G1, PWM-G2, PWM-G3, PWM-G4, PWM-G5, PWM-G6	UFS (m-phy) interface runs in low performance (PWM-Gx) modes.
	HS-G1, HS-G2, HS-G3, HS-G4	UFS (m-phy) interface runs in high performance (HS-Gx) modes.
	Native Command Queue support
	Hibernation	Low power state.
	Runtime time power management	Driver issues software hibernation entry in runtime suspend, and hibernation exit in runtime resume.
	Auto hibernation	Hibernation triggered by controller.
	PWM SLOW modes
	PWM SLOW_AUTO modes
	HS FAST modes
	HS FAST_AUTO modes
	HS RATE_A series
	HS RATE_B series
	UFS Inline Encryption
	UFS WriteBooster
USB 3.0	SuperSpeedPlus host	USB host in 3.1 Gen2 mode (10 Gbps).
	SuperSpeed host	USB host in 3.0 mode (5 Gbps).
	High Speed host	USB host in 2.0 mode (480 Mbps).
	Full Speed host	USB host in 2.0 or 1.2 mode (12 Mbps).
	Low Speed host	USB host in 2.0 or 1.2 mode (1.5 Mbps).
	Auto-suspend	USB host suspends the port/connected device if there is no activity.
	Remote wake-up	USB host resumes the port/connected device if wake-up is triggered by the device.
	Auto-resume	USB host resumes the port/connected device if wake-up is triggered by the host.
	ELPG for xUSB High Speed partition	Engine-level power gating support for xUSB High Speed partition.
	ELPG for xUSB SuperSpeed partition	Engine-level power gating support for xUSB SuperSpeed partition.
	Lower power state (U3 state)
	LPM states (U1, U2 states)
	Hot plug support	USB drives can be removed and connected while system is active.
	Port multiplier support	Hub for USB.
	Host mass storage	Protocol for storage devices.
	Host USB video class	Protocol for camera devices.
	Host USB ECM	Protocol for ethernet over USB.
	Host USB audio class	Protocol for audio over USB.
	Host USB modem—NCM	NCM protocol support for modem functionality.
	USB HID protocol	Human interface devices.
	SuperSpeed device (xUSB)	USB device in 3.0 mode.
	High Speed device (xUSB)	USB device in 2.0 mode.
	BC1.2 charging support	Support for battery charging per BC1.2 spec.
	Apple charger	Support for detecting Apple charger.
	MTP device mode	MTP protocol support for data transfer.
	ADB device mode	ADB protocol support for data transfer.
	RNDIS device mode	RNDIS protocol support for data transfer.
	OTG	USB host and device (cable-based detection).
	Adapt Heavy-Security Falcon 6.0 Micro-controller with integrated Secured Co-Processor
	Stream performance enhancement
	Support new Extended TBC Capability defined in xHCI specification
	Add support for xhci 1.2 spec changes
	I.3.5 - Intel Time Stamp Correlation Capability
	I.4.7 - USB3 Protocol PORTLI Definition
	I.4.9 - Slot Context (Offset 08h)
	USB_ID detect by VGPIO
	Recovery Mode
	Fuel Gauge/Battery Charging

HDMI

Feature	Details
EDID support	Read and parse EDID.
Hot-plug detection	Hot-plug detection with HDMI® monitors and TVs.
HDMI 1.4	Support for HDMI 1.4 (480p, 720p, 1080p, and 4K at 30 Hz).
HDMI 2.1 TMDS	Support for HDMI 2.1 (4K at 30 Hz and 60 Hz).
Driver suspend/resume	Driver suspend/resume for low power.
HDMI as primary display	Support HDMI as the primary display.
Sideband information	Sends the sideband information, such as infoframes and audio data, to the panel during video refresh.

DisplayPort

Feature	Details
EDID	Read and parse EDID.
DP hot-plug support	Hot-plug detection with DP monitors or TV.
Full link training	Handshake signaling between host and device.
HPD_IRQ event	Feedback from the panels in case of link synchronization loss.
Driver suspend/resume	Driver suspend/resume for low power.
Primary display	Support DP as primary display.
DP MST	Support two different multiple streams on different monitors.
Link rates 1.62, 2.7, 5.4, and 8.1 Gbps	Link rates supported by the driver up to HBR3.
Aux link	Support DP aux link.
Sideband information	Sends the sideband information, such as infoframes and audio data, to the panel during video refresh.
Display Stream Compression	Supports DSC 1.2. DSC is a compression method that reduces bandwidth requirements without significant visual quality loss, enabling higher resolutions and refresh rates.

Security Engine

Algorithm	Notes
AES-CBC/ECB/OFB/CTR/XTS	Uses AES1 engine running on SE2 through Host1x bus.
AES-CMAC	Uses AES1 engine running on SE2 through Host1x bus.
AEAD-AES_CCM/GCM	Uses AES1 engine running on SE2 through Host1x bus.
HMAC-SHA	Uses HASH engine running on SE4 through Host1x bus.
SHA1/2/3-224/256/384/512	Uses HASH engine running on SE4 through Host1x bus.
SM4 - CBC/ECB/CTR/XTS	Uses AES0 engine running on SE2 through Host1x bus.
SM3	Uses HASH engine running on SE4 through Host1x bus.
Key distribution system (KDS)	Region setup, KEY_MOV, KEY_INVLD

Power Modes (Profiles)

Features:

• Reference power profiles such as 40W, 75W, 95W, 120W, and MAXN are supported for the various Jetson Thor modules.

• NVPModel interface for power mode selection and custom mode creation.

RTC

Features:

• Alarm.

• Wake-up from SC7.

System

Features:

• Reboot support.

• Shutdown support.

• SC7.

• cpuidle.

• Wake from idle.

• Wake from sleep.

• CPU hotplug.

• DVFS.

• CPU/GPU frequency governor.

• EMC bandwidth manager.

• Power monitor.

• Clock and thermal management.

• initrd support.

• System boot with ATF as secure monitor.

• Experimental generic timestamping engine (GTE) support for LIC IRQ lines and AON GPIOs.

Porting to custom platforms

To adapt the software to custom platforms, follow <Adaptation Guide link> for NVIDIA Jetson Thor.