The MM2L20-AR has selectable retiming (CDR) in both transmit and receive function. This retiming function is designed for 25 - 26Gbps operation and must be bypassed for 10/14Gbps operation. The SFF-8472 (rev 12.2) standard does not expressly support CDR control. This section explains how it is implemented.
The transmit and receive data rate can be selected using either the rate select IO pins RS0 and RS1 (refer to the Pin Description section), or by using the 2-wire (I2C) control signals. RS0 controls the receiver and RS1 controls the transmitter as, listed below:
CDR Control and Rate
Parameter | State | CDR Control | Rate |
Logic OR of RS0 pin and RS0 bit | Low/0 | Receiver CDR bypass | Receiver data rate = Low |
High/1 | Receiver CDR enabled | Receiver data rate = High | |
Logic OR of RS1 pin and RS1 bit | Low/0 | Transmitter CDR bypass | Transmitter data rate = Low |
High/1 | Transmitter CDR enabled | Transmitter data rate = High |
The default state of RS0 and RS1 select registers is ‘1’ (high), which to MM2L20-AR indicates a 25.78Gbps nominal rate with receiver and transmitter CDRs enabled.
The logic state of RS0 is the logic OR of the external RS0 pin, and the RS0 bit (page A2h address 110d bit 3).
The logic state of RS1 is the logic OR of the external RS1 pin and the RS1 bit (page A2h, address 118d bit 3).
Unfortunately, the SFF-8472 (rev 12.2) standard does not specify any rate select value for 25.78Gbps operation. Hence, the value of the rate select register (page A0h address 13d) = 00h (rate unspecified). This is summarized in the table below.
Note that SFF-8431 specifies the use of RS0/1 to distinguish between data rates below or above 4.25Gbps. SFF-8472 does not specify the settings for 25.78Gbps operation.
SFF-8472 Memory Map Rate Fields
Field | Address | R/W | Value | Notes |
Rate Identifier | Address A0h, Byte 13 | R | 00h | 00h - Unspecified. |
Rate select implemented | Address A0h, Byte 65 bit 5 | R | ‘1’ | --- |
Optional soft RATE_SELECT control and monitoring implemented | Address A0h, Byte 93 bit 3 | R | ‘1’ | --- |
Optional soft Rate Select control implemented per SFF-8431 | Address A0h, Byte 93 bit 1 | R | ‘0’ | --- |
RS(1) State | Address A2h, Byte 110 bit 5 | R | N/A | Represents the current RS(1) state (Logic OR of RS1 pin and RS1 bit) |
RS(0) State | Address A2h, Byte 110 bit 4 | R | N/A | Represents the current RS(0) state (Logic OR of RS0 pin and RS0 bit) |
Soft Rate_Select(0) [Soft RS(0)] | Address A2h, Byte 110 bit 3 | R/W | ‘1’ | Soft Rate Select is set to high speed, CDR enabled by default. |
Soft Rate_Select(1) [Soft RS(1)] | Address A2h, Byte 118 bit 3 | R/W | ‘1’ | Soft Rate Select is set to high speed, CDR enabled by default. |