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PVA SDK

PVA SDK - Home PVA SDK - Home

PVA SDK

Table of Contents

  • Release Notes
  • Getting Started
    • Installation
    • SDK Samples
    • Deploying Applications
  • Step-by-Step Tutorials
    • PVA Basics
      • Hello World! - Host, Device, Executable and CmdProgram
      • SyncObject, Fence and Stream
      • VMEM Scalars and CheckCmdStatus
      • VMEM Buffers, MemAlloc and DataFlows
    • Processing Tiles in Parallel
      • Raster Data Flow (RDF) and Tiles
      • RDF Double Buffering
      • Scheduling APIs
    • Developing, Optimizing and Profiling a Complete PVA Program
      • RDF Halo Configuration
      • VPU Programming Basics
      • Optimizing VPU Programs
      • Profiling Tools
    • Using Developer Tools for Debugging PVA Applications
      • VPU Debugging with LLDB (NVVPU Toolchain)
    • Advanced PVA Optimization Techniques
      • Region of Interest (ROI) Gather via GatherScatter Dataflow (GSDF)
      • Accelerating Bilinear Interpolation via the Sampler APIs
      • ROI Align Layer on VPU
      • ROI Align Optimization on PVA
      • Using L2 SRAM for Efficient ROI Gathering
    • Interacting with Other Engines
      • CUDA Interoperability
      • NvSci Interoperability
    • PVA Accelerated Primitives Library (APL)
  • Frequently Asked Questions
  • Architecture
  • Reference Manuals
    • DMA Configuration Details
  • Development Tools
    • Build System
    • NVVPU Toolchain
    • VPU Debugging
    • GDB Symbols for Host Code Debugging
    • ASIP Programmer
      • Installing ASIP Programmer
      • Using ASIP Programmer
        • On-chip Debugging
        • Debug over IP with ChessDE
        • On-chip Debug with Cable
        • ChessDE Debugging Tutorial
      • Native Model
      • Following the PVA SDK Tutorials with ASIP Programmer
    • Nsight Systems
  • VPU Application Signing
  • Copyright and Licenses
  • API Maturity and Deprecated list
    • Deprecated

API Reference

  • Host C++ API
    • CUDA Interoperability
    • Context
    • Dataflow configuration
    • NvSci Interoperability
    • Program
    • Resource
    • Stream
    • Synchronization
    • System
  • Host C API
    • CUDA Interoperability
    • Context
      • CUPVA_COMMAND_UNKNOWN
      • CUPVA_SUBMISSION_UNKNOWN
    • Dataflow configuration
    • NvSci Interoperability
    • Program
    • Resource
    • Stream
    • Synchronization
    • System
  • Host type Conversions
  • Device API
    • Basic DataFlow API
    • DynamicDataFlow API
    • GatherScatterDataFlow API
      • GSDF_SURFACE_MIN_TILEBUFFER_SIZE
      • GSDF_SURFACE_MIN_TILE_PITCH
      • GSDF_SURFACE_MIN_TILE_STRIDE
      • GSDF_SURFACE_TILE_OFFSET
      • GSDF_UNIFORM
      • VMEM_GSDF_HANDLER
    • RasterDataFlow API
      • RDF_CIRCULAR
      • RDF_CIRCULAR_COLUMNMAJOR
      • RDF_CIRCULAR_ROWMAJOR
      • RDF_DOUBLE
      • RDF_SINGLE
      • VMEM_RDF_UNIFIED
    • Sampler API
    • SequenceDataFlow API
      • VMEM_SEQDF_HANDLER
    • System utilities
      • CUPVA_VPU_MAIN
    • TensorDataFlow API
      • TDF_DOUBLE
      • TDF_SINGLE
      • VMEM_TDF_HANDLER
    • VPU utilities
      • CUPVA_ALIGNED
      • CUPVA_CIRCULAR_BUFFER_LENGTH
      • CUPVA_DOUBLE_BUFFER_LENGTH
      • CUPVA_EXPORT
      • CUPVA_SINGLE_BUFFER_LENGTH
      • EXTERN_VMEM
      • EXTERN_VMEM_DMA_CONFIG
      • EXTERN_VMEM_POINTER
      • EXTERN_VMEM_SURFACE
      • INIT_AGEN1
      • INIT_AGEN2
      • INIT_AGEN3
      • INIT_AGEN4
      • INIT_AGEN5
      • INIT_AGEN6
      • VMEM
      • VMEM_NOEXPORT
      • VMEM_POINTER
      • VMEM_SURFACE
  • PVA Accelerated Primitives Library
    • Harris Corner
      • PVAAPL_HARRIS_SCRATCH_SIZE
    • Non-maximum suppression
      • PVAAPL_NMS_SCRATCH_SIZE
    • Separable convolution
  • Utility Library
  • Platform
    • CUPVA_DECLARE_EXECUTABLE
    • CUPVA_EXECUTABLE_DATA
    • CUPVA_EXECUTABLE_SIZE
    • PVA_DECLARE_EXECUTABLE
    • PVA_EXECUTABLE_DATA
    • PVA_EXECUTABLE_SIZE
  • API Reference Index
  • Development Tools
  • ASIP Programmer

ASIP Programmer#

ASIP Programmer is an optional retargetable toolchain for building VPU code. The core SDK provides EMU, NVVPU, and LLDB without this addition. ASIP Programmer provides the Chess compiler, ChessDE, and the native model, and is required for safety builds. Speak to your NVIDIA representative for access.

  • Installing ASIP Programmer
    • Licensing
    • Compiler Selection
  • Using ASIP Programmer
    • ChessDE Debugging
  • Chess linker and BCF files
  • Chess C/C++ frontends
  • Chess-clang migration guide
    • Function Inlining Control
    • Memory Fence
    • Prevent Breaking-Up Load and AGEN Restore Operations
    • Vector Demotion Operation with Interleaving
    • Function Name Mangling
    • Performance Optimization Tips
  • Native Model
    • Native Build Instructions
    • Native Debugging
    • Using Native on Windows with WSL2
    • Native Limitations
  • Following the PVA SDK Tutorials with ASIP Programmer
    • Native Model
    • ChessDE debugging

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GDB Symbols for Host Code Debugging

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Installing ASIP Programmer

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Last updated on Oct 13, 2026.