Pin Description

PCI Express Pins Description

The below table lists the PCI Express pins description. For further details, please refer to PCI Express Interface.

PCI Express Pin Description

The below table lists the NC-SI pins description. For further details, please refer to NC-SI Management Interface.

NC-SI Management Pins Description

Pin #	Type	I/O	Description
1	REF_CLK	Input	Clock reference for receive, transmit, and control interface
2	GND	Power	Ground
3	ARB_IN	Input	Network Controller hardware arbitration
4	GND	Power	Ground
5	ARB_OUT	Output	Network Controller hardware arbitration
6	GND	Power	Ground
7	RXD0	Output	Receive data
8	GND	Power	Ground
9	RXD1	Output	Receive data
10	GND	Power	Ground
11	CRS_DV	Output	Carrier Sense/Receive Data Valid
12	GND	Power	Ground
13	TXD0	Input	Transmit data
14	GND	Power	Ground
15	TXD1	Input	Transmit data
16	GND	Power	Ground
17	TX_EN	Input	Transmit enable
18	GND	Power	Ground
19	Not Connected	-	-
20	GND	Power	Ground
21	SDA (Not Used)	I/O	N/A
22	GND	Power	Ground
23	SCL (Not Used)	Input	N/A
24	GND	Power	Ground
25	GND	Power	Ground
26	GND	Power	Ground
27	3.3V (Not Used)	Power	-
28	3.3V (Not Used)	Power	-
29	3.3V (Not Used)	Power	-
30	3.3V (Not Used)	Power	-

The below table lists the JTAG CoreSight 10 pins description. For further details, please refer to JTAG CoreSight 10 Interface.

JTAG CoreSight 10 Pins Description

Pin#	Signal Name	Voltage Domain	Description
1	VTREF	A	The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
2	TMS	A	The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
3	GND	NA	Ground.
4	TCK	A	The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
5	GND	NA	Ground.
6	TDO	A	The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
7	KEY (NC)	NA	This pin must not be present on the target connector.
8	TDI	A	The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
9	GND	NA	Ground.
10	nSRST	A	The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.