Pin Description

PCI Express Pins Description

The below table lists the PCI Express pins description. For further details, please refer to PCI Express Interface.

PCI Express Pin Description

Pin #	Signal Name	Description	Pin #	Signal Name	Description
A1	PRSNT1#	Mechanical Present	B1	12V
A2	12V		B2	12V
A3	12V		B3	12V
A4	GND		B4	GND
A5	TCK	JTAG	B5	SMCLK	Host SMBus
A6	TDI	JTAG	B6	SMDAT	Host SMBus
A7	TDO	JTAG	B7	GND
A8	TMS	JTAG	B8	3.3V
A9	3.3V		B9	TRST#	JTAG
A10	3.3V		B10	3.3V_AUX
A11	PERST#	PCIe Reset	B11	WAKW#/RSVD
A12	GND		B12	RSVD
A13	REFCLK+	Host Reference Clock	B13	GND
A14	REFCLK-	Host Reference Clock	B14	PETP0
A15	GND		B15	PETN0
A16	PERP0		B16	GND
A17	PERN0		B17	RSVD
A18	GND		B18	GND
A19	RSVD		B19	PETP1
A20	GND		B20	PETN1
A21	PERP1		B21	GND
A22	PERN1		B22	GND
A23	GND		B23	PETP2
A24	GND		B24	PETN2
A25	PERP2		B25	GND
A26	PERN2		B26	GND
A27	GND		B27	PETP3
A28	GND		B28	PETN3
A29	PERP3		B29	GND
A30	PERN3		B30	RSVD
A31	GND		B31	RSVD
A32	RSVD		B32	GND
A33	RSVD		B33	PETP4
A34	GND		B34	PETN4
A35	PERP4		B35	GND
A36	PERN4		B36	GND
A37	GND		B37	PETP5
A38	GND		B38	PETN5
A39	PERP5		B39	GND
A40	PERN5		B40	GND
A41	GND		B41	PETP6
A42	GND		B42	PETN6
A43	PERP6		B43	GND
A44	PERN6		B44	GND
A45	GND		B45	PETP7
A46	GND		B46	PETN7
A47	PERP7		B47	GND
A48	PERN07		B48	PRSNT2#	Mechanical Present
A49	GND		B49	GND

The below table lists the NC-SI pins description. For further details, please refer to NC-SI Management Interface.

NC-SI Management Pins Description

Pin #	Type	I/O	Description
1	REF_CLK	Input	Clock reference for receive, transmit, and control interface
2	GND	Power	Ground
3	ARB_IN	Input	Network Controller hardware arbitration
4	GND	Power	Ground
5	ARB_OUT	Output	Network Controller hardware arbitration
6	GND	Power	Ground
7	RXD0	Output	Receive data
8	GND	Power	Ground
9	RXD1	Output	Receive data
10	GND	Power	Ground
11	CRS_DV	Output	Carrier Sense/Receive Data Valid
12	GND	Power	Ground
13	TXD0	Input	Transmit data
14	GND	Power	Ground
15	TXD1	Input	Transmit data
16	GND	Power	Ground
17	TX_EN	Input	Transmit enable
18	GND	Power	Ground
19	Not Connected	-	-
20	GND	Power	Ground
21	SDA (Not Used)	I/O	N/A
22	GND	Power	Ground
23	SCL (Not Used)	Input	N/A
24	GND	Power	Ground
25	GND	Power	Ground
26	GND	Power	Ground
27	3.3V (Not Used)	Power	-
28	3.3V (Not Used)	Power	-
29	3.3V (Not Used)	Power	-
30	3.3V (Not Used)	Power	-

The below table lists the JTAG CoreSight 10 pins description. For further details, please refer to JTAG CoreSight 10 Interface.

JTAG CoreSight 10 Pins Description

Pin#	Signal Name	Voltage Domain	Description
1	VTREF	A	The Voltage Target Reference pin supplies DSTREAM with the debug rail voltage of the target to match its I/O logic levels. VTREF can be tied HIGH on the target. If VTREF is pulled HIGH by a resistor, its value must be no greater than 100Ω.
2	TMS	A	The Test Mode Select pin sets the state of the Test Access Port (TAP) controller on the target. TMS can be pulled HIGH on the target to keep the TAP controller inactive when not in use.
3	GND	NA	Ground.
4	TCK	A	The Test Clock pin clocks data into the TDI and TMS inputs of the target. TCK is typically pulled HIGH on the target.
5	GND	NA	Ground.
6	TDO	A	The Test Data Out pin receives serial data from the target during debugging. You are advised to series terminate TDO close to the target processor. TDO is typically pulled HIGH on the target.
7	KEY (NC)	NA	This pin must not be present on the target connector.
8	TDI	A	The Test Data In pin provides serial data to the target during debugging. TDI can be pulled HIGH on the target.
9	GND	NA	Ground.
10	nSRST	A	The System Reset pin fully resets the target. This signal can be initiated by DSTREAM or by the target board (which is then detected by DSTREAM). nSRST is typically pulled HIGH on the target and pulled strong-LOW to initiate a reset. The polarity and strength of nSRST is configurable.