NVIDIA BlueField-2 Ethernet DPU User Guide
NVIDIA BlueField-2 Ethernet DPU User Guide

Pin Description

DPU PCI Express x8 Pin Description

Pin #

Signal Name

Description

Pin #

Signal Name

Description

A1

PRSNT1#

Mechanical Present

B1

12V

A2

12V

B2

12V

A3

12V

B3

12V

A4

GND

B4

GND

A5

TCK

JTAG - Not Connected

B5

SMCLK

Host SMBus

A6

TDI

JTAG - Not Connected

B6

SMDAT

Host SMBus

A7

TDO

JTAG - Not Connected

B7

GND

A8

TMS

JTAG - Not Connected

B8

3.3V

3.3V - Not Connected

A9

3.3V

3.3V - Not Connected

B9

TRST#

JTAG - Not Connected

A10

3.3V

3.3V - Not Connected

B10

3.3V_AUX

A11

PERST#

PCIe Reset

B11

WAKE#/RSVD

A12

GND

B12

RSVD

A13

REFCLK+

Host Reference Clock

B13

GND

A14

REFCLK-

Host Reference Clock

B14

PETP0

A15

GND

B15

PETN0

A16

PERP0

B16

GND

A17

PERN0

B17

RSVD

A18

GND

B18

GND

A19

RSVD

B19

PETP1

A20

GND

B20

PETN1

A21

PERP1

B21

GND

A22

PERN1

B22

GND

A23

GND

B23

PETP2

A24

GND

B24

PETN2

A25

PERP2

B25

GND

A26

PERN2

B26

GND

A27

GND

B27

PETP3

A28

GND

B28

PETN3

A29

PERP3

B29

GND

A30

PERN3

B30

RSVD

A31

GND

B31

RSVD

A32

RSVD

B32

GND

A33

RSVD

B33

PETP4

A34

GND

B34

PETN4

A35

PERP4

B35

GND

A36

PERN4

B36

GND

A37

GND

B37

PETP5

A38

GND

B38

PETN5

A39

PERP5

B39

GND

A40

PERN5

B40

GND

A41

GND

B41

PETP6

A42

GND

B42

PETN6

A43

PERP6

B43

GND

A44

PERN6

B44

GND

A45

GND

B45

PETP7

A46

GND

B46

PETN7

A47

PERP7

B47

GND

A48

PERN7

B48

PRSNT2#

Mechanical Present

A49

GND

B49

GND


DPU PCI Express x16 Pin Description

Pin #

Signal Name

Description

Pin #

Signal Name

Description

A1

PRSNT1#

Mechanical Present

B1

12V

A2

12V

B2

12V

A3

12V

B3

12V

A4

GND

B4

GND

A5

TCK

JTAG - Not Connected

B5

SMCLK

Host SMBus

A6

TDI

JTAG - Not Connected

B6

SMDAT

Host SMBus

A7

TDO

JTAG - Not Connected

B7

GND

A8

TMS

JTAG - Not Connected

B8

3.3V

3.3V - Not Connected

A9

3.3V

3.3V - Not Connected

B9

TRST#

JTAG - Not Connected

A10

3.3V

3.3V - Not Connected

B10

3.3V_AUX

A11

PERST#

PCIe Reset

B11

WAKE#/RSVD

A12

GND

B12

RSVD

A13

REFCLK+

Host Reference Clock

B13

GND

A14

REFCLK-

Host Reference Clock

B14

PETP0

A15

GND

B15

PETN0

A16

PERP0

B16

GND

A17

PERN0

B17

RSVD

A18

GND

B18

GND

A19

RSVD

B19

PETP1

A20

GND

B20

PETN1

A21

PERP1

B21

GND

A22

PERN1

B22

GND

A23

GND

B23

PETP2

A24

GND

B24

PETN2

A25

PERP2

B25

GND

A26

PERN2

B26

GND

A27

GND

B27

PETP3

A28

GND

B28

PETN3

A29

PERP3

B29

GND

A30

PERN3

B30

RSVD

A31

GND

B31

RSVD

A32

RSVD

B32

GND

A33

RSVD

B33

PETP4

A34

GND

B34

PETN4

A35

PERP4

B35

GND

A36

PERN4

B36

GND

A37

GND

B37

PETP5

A38

GND

B38

PETN5

A39

PERP5

B39

GND

A40

PERN5

B40

GND

A41

GND

B41

PETP6

A42

GND

B42

PETN6

A43

PERP6

B43

GND

A44

PERN6

B44

GND

A45

GND

B45

PETP7

A46

GND

B46

PETN7

A47

PERP7

B47

GND

A48

PERN7

B48

RSVD

A49

GND

B49

GND

A50

RSVD

B50

PETP8

A51

GND

B51

PETN8

A52

PERP8

B52

GND

A53

PERN8

B53

GND

A54

GND

B54

PETP9

A55

GND

B55

PETN9

A56

PERP9

B56

GND

A57

PERN9

B57

GND

A58

GND

B58

PETP10

A59

GND

B59

PETN10

A60

PERP10

B60

GND

A61

PERN10

B61

GND

A62

GND

B62

PETP11

A63

GND

B63

PETN11

A64

PERP11

B64

GND

A65

PERN11

B65

GND

A66

GND

B66

PETP12

A67

GND

B67

PETN12

A68

PERP12

B68

GND

A69

PERN12

B69

GND

A70

GND

B70

PETP13

A71

GND

B71

PETN13

A72

PERP13

B72

GND

A73

PERN13

B73

GND

A74

GND

B74

PETP14

A75

GND

B75

PETN14

A76

PERP14

B76

GND

A77

PERN14

B77

GND

A78

GND

B78

PETP15

A79

GND

B79

PETN15

A80

PERP15

B80

GND

A81

PERN15

B81

PRSNT2#

Mechanical Present

A82

GND

B82

RSVD


The below table provides the External Power Supply pins of the external power supply interfaces on the DPU. For further details, please refer to External PCIe Power Supply Connector.

Warning

The mechanical pinout of the 6-pin external +12V power connector is shown below. The +12V connector is a GPU power PCIe standard connector. Care should be taken to ensure the power is applied to the correct pins as some 6-pin ATX type connector can have different pinouts.

Pin#

Signal Name

Description

1

12V

ATX Supplied 12V

2

12V

ATX Supplied 12V

3

12V

ATX Supplied 12V

4

GND

Power Return

5

GND

Power Return

6

GND

Power Return

The below table provides the 4-pin vertical USB connector on the DPU. For further details, please refer to USB Interface.

Pin #

Signal

1

+5V_USB

2

USB DP

3

USB DN

4

GND

The below tables list the NC-SI management interface pinout descriptions per card type. Please follow the link to the table coinciding with the OPN you have purchased.

OPNs

HW Versions

Link

MBF2H332A-AECOT, MBF2H332A-AECOT,

MBF2H332A-AENOT

A1xx - A3xx

30-pin Connector:

Table A - NC-SI Connector Pins

MBF2H332A-AECOT, MBF2H332A-AECOT,

MBF2H332A-AENOT

B1xx and Up

30-pin Connector:

Table B - NC-SI Connector Pins

MBF2M355A-VECOT, MBF2M355A-VESOT

A1xx and Up

MBF2H516A-CEEOT, MBF2H516A-CENOT

MBF2M516A-CECOT, MBF2M516A-CEEOT

MBF2M516A-CENOT, MBF2H512C-AECOT

MBF2H516C-CECOT, MBF2H516C-CESOT

MBF2H516C-CEUOT, MBF2M516C-CECOT

MBF2M516C-CESOT, MBF2H512C-AESOT

MBF2H512C-AEUOT

A1xx and Up

30-pin Connector:

Table C - NC-SI Connector Pins

MBF2H532C-AECOT, MBF2H532C-AESOT

A1xx - A5xx

MBF2H536C-CECOT, MBF2H536C-CESOT

A1xx - A7xx

MBF2H532C-AECOT, MBF2H532C-AESOT

MBF2H536C-CECOT, MBF2H536C-CESOT

B1xx and Up

20-pin Connector

Table D - NC-SI Connector Pins

MBF2H536C-CEUOT

A1xx and Up

Table A - NC-SI Connector Pins

Pin#

Signal Name

I/O

Description

Comments

1

REF_CLK

Input

50M REF CLK for NCSI BUS

RBT Reference clock. Synchronous clock reference for receive, transmit and control interface. The clock shall have a typical frequency of 50MHz ±50 ppm.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the DPU cable connector. The RBT_REF_CLK shall not be driven until 3.3V AUX is present on the DPU. The RBT_REF_CLK shall be continuous once it has started. For DPUs, this pin shall be connected between the connector and the RBT PHY. No external termination is required.

2

GND

GND

Ground

3

ARB_IN

Input

NCSI hardware arbitration input

NC-SI hardware arbitration input

If the baseboard supports multiple DPU cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_IN pin of the first populated DPU card to its RBT_ARB_OUT pin if it is the only card present or to the RBT_ARB_OUT pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated or powered off.

4

GND

GND

Ground

5

ARB_OUT

Output

NCSI hardware arbitration output

NC-SI hardware arbitration output.

If the baseboard supports multiple DPU cards connected to the same RBT interface, it shall implement logic that connects the RBT_ARB_OUT pin of the first populated DPU card to its RBT_ARB_IN pin if it is the only card present or to the RBT_ARB_IN pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic shall bypass slots that are not populated or powered off.

6

GND

GND

Ground

7

RX_D0

Output

Receive data

Output for SoC

Receive data. Data signals from the network controller to the BMC.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the DPU RBT PHY requirements.

8

GND

GND

Ground

9

RX_D1

Output

Receive data

Output for SoC

Receive data. Data signals from the network controller to the BMC.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the DPU RBT PHY requirements.

10

GND

GND

Ground

11

CRS_DV

Output

Carrier sense/Receive Data Valid

Carrier sense/receive data valid. This signal is used to indicate to the baseboard that the carrier sense/receive data is valid.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no DPU is installed. For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the SmartNIC RBT PHY requirements.

12

GND

GND

Ground

13

TX_D0

Input

Transmit data

Input for SoC.

Data signals from the BMC to the network controller.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the DPUcable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the DPU RBT PHY requirements.

14

GND

GND

Ground

15

TX_D1

Input

Transmit data

Input for SoC. Data signals from the BMC to the network controller.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the DPUcable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the DPU RBT PHY requirements.

16

GND

GND

Ground

17

TX_EN

Input

Transmit enable

Transmit enable.

For baseboards, this pin shall be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to ground on the baseboard between the RBT isolator and the DPU cable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin shall be connected between the connector and the RBT PHY. External termination determined by the DPU RBT PHY requirements.

18

GND

GND

Ground

19

NC

20

NC

21

I2C_SDA

Bidirectional

I2C Serial Data

GW_ARM1

22

GND

GND

Ground

23

I2C_SCL

Bidirectional

I2C Serial Clock

GW_ARM1

24

GND

GND

Ground

25

GND

GND

Ground

26

GND

GND

Ground

27

NC

28

UART_TX

Output

Transmit data

Output for SoC. 3.3V UART TX signal from the baseboard.

29

NC

30

UART_RX

Input

Receive data

3.3V UART RX signal to the baseboard.

Table B - NC-SI Connector Pins

Note

PACK_ID[2:0] signals allow for 8 unique card IDs. The system configurator sets the unique value per card via the connecting harness.

Pin #

Pin Name

I/O

Description / Comments

1

NCSI_REF_CLK

Input

50MHz REF CLK for NC-SI BUS

2

GND

GND

Ground

3

NCSI_ARB_IN

Input

NC-SI hardware arbitration input

4

PACK_ID0, connected to BlueField-2 NIC_GPIO[49]

Input

See the note above table

5

NCSI_ARB_OUT

Output

NC-SI hardware arbitration output

6

PACK_ID1, connected to BlueField-2 NIC_GPIO[47]

Input

See the note above table

7

NCSI_RX_D0

Output

Receive Data Out 0

8

GND

GND

Ground

9

NCSI_RX_D1

Output

Receive Data Out 1

10

GND

GND

Ground

11

NCSI_CRS_DV

Output

Carrier Sense / Receive Data Valid

12

GND

GND

Ground

13

NCSI_TX_D0

Input

Transmit Data In 0

14

GND

GND

Ground

15

NCSI_TX_D1

Input

Transmit Data In 0

16

GND

GND

Ground

17

NCSI_TX_EN

Input

Transmit Enable

18

GND

GND

Ground

19

Reserved

20

SOFT_RST#, connected to BlueField-2 device pin HOST_GPIO[7]

21

ARM_I2C1_SDA

Input/Output

Open-drain signal

22

ARM_NSRST#

Input/Output

Open-drain signal

23

ARM_I2C1_SCL

Input/Output

Open-drain signal

24

PACK_ID2, connected to BlueField-2 device pin NIC_GPIO[46]

Input

See description above table

25

GND

GND

Ground

26

Not Connected

27

Not Connected

28

BF_UART0_TX

Output

UART transmit serial data output

29

Not Connected

30

BF_UART0_RX

Input

UART transmit serial data input

Table C - NC-SI Connector Pins

Note

PACK_ID[2:0] signals allow for 8 unique card IDs. The system configurator sets the unique value per card via the connecting harness.

Pin #

Pin Name

I/O

Description / Comments

1

NCSI_REF_CLK

Input

50MHz REF CLK for NC-SI BUS

2

GND

GND

Ground

3

NCSI_ARB_IN

Input

NC-SI hardware arbitration input

4

PACK_ID0, connected to BlueField-2 device pin NIC_GPIO[49]

Input

See the note above table

5

NCSI_ARB_OUT

Output

NC-SI hardware arbitration output

6

PACK_ID1, connected to BlueField-2 device pin NIC_GPIO[47]

Input

See the note above table

7

NCSI_RX_D0

Output

Receive Data Out 0

8

GND

GND

Ground

9

NCSI_RX_D1

Output

Receive Data Out 1

10

GND

GND

Ground

11

NCSI_CRS_DV

Output

Carrier Sense / Receive Data Valid

12

GND

GND

Ground

13

NCSI_TX_D0

Input

Transmit Data In 0

14

GND

GND

Ground

15

NCSI_TX_D1

Input

Transmit Data In 0

16

GND

GND

Ground

17

NCSI_TX_EN

Input

Transmit Enable

18

GND

GND

Ground

19

Reserved

20

Reserved

21

BMC_I2C2_SDA

Input/Output

Open-drain signal

22

NIC_BMC_CTRL1, connected to BMC device pin W4 (Open Drain)

Input/Output

Open-drain signal

23

BMC_I2C2_SCL

Input/Output

Open-drain signal

24

PACK_ID2, connected to BlueField-2 device pin NIC_GPIO[46]

Input

See description above table

25

GND

GND

Ground

26

NIC_BMC_CTRL0, connected to BMC device pin Y3 (Open Drain)

27

Not Connected

28

BMC_TX5

Output

UART transmit serial data output

29

Not Connected

30

BMC_RX5

Input

UART transmit serial data input

Table D - 20-pin NC-SI Connector Pins

Note

PACK_ID[2:0] signals allow for 8 unique card IDs. The system configurator sets the unique value per card via the connecting harness.

Pin#

Pin Name

IO

Description/Comments

1

GND

Ground

Ground

2

PACK_ID1, connected to BlueField-2 NIC_GPIO[47]

Input

See the description above table regarding PACK_ID

Should be connected to the Primary controller NC-SI PACK_ID pins to set the appropriate package ID.

PACK_ID0 should be connected to the endpoint device GPIO associated with Package ID[0]. PACK_ID1 should be associated with Package ID0.

The baseboard should connect to GND or leave floating.

DPU should have a 4.7k PU.

3

RBT_RXD0

Output

Receive data Out 0. Data signals from the network controller to the BMC.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull-down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

4

RBT_REF_CLK

Input

RBT Reference clock. Synchronous clock reference for receive, transmit, and control interface. The clock should have a typical frequency of 50MHz ±50 ppm.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the DPU cable connector. The RBT_REF_CLK should not be driven until 3.3V AUX is present on the DPU. The RBT_REF_CLK should be continuous once it has started. For DPUs, this pin should be connected between the connector and the RBT PHY. No external termination is required.

50MHz REF CLK for NC-SI BUS

5

RBT_RXD1

Output

Receive Data Out 1. Data signals from the network controller to the BMC.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull-down resistor to GND on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no card is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

6

GND

Ground

Ground

7

RBT_CRS_DV

Output

Carrier sense/receive data valid. This signal indicates to the baseboard that the carrier sense/receive data is valid.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull-down resistor on the baseboard between the BMC and the RBT isolator to prevent the signal from floating when no DPU is installed.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

8

RBT_ISOLATE_N

Output

Signal used to indicate the SmartNIC has powered and is ready for NC-SI physical layer connection to be present. When low the baseboard circuitry will isolate the NC-SI connection to the SmartNIC. When high normal NC-SI RBT connectivity is available.

Baseboards should terminate this with a 47K-100K PD resistor.

SmartNICs should terminate with a 10k PU resistor.

9

GND

Ground

Ground

10

PACK_ID0, connected to BlueField-2 NIC_GPIO[49]

Input

See note above table regarding NC-SI PACK_ID

should be connected to the Primary controller NC-SI PACK_ID pins to set the appropriate package ID.

PACK_ID0 should be connected to the endpoint device GPIO associated with Package ID[0]. PACK_ID1 should be associated with PACK_ID[1].

The baseboard should connect to GND or leave floating.

DPU should have a 4.7k PU.

11

NCSI_TX_EN

Input

Transmit enable.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull-down resistor to ground on the baseboard between the RBT isolator and the DPU cable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

12

GND

Ground

Ground

13

NCSI_TX_D0

Input

Transmit Data In 0.

Data signals from the BMC to the network controller.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull down resistor to GND on the baseboard between the RBT isolator and the DPUcable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

14

BMC_RX5

Input

UART transmit serial data input. 3.3V UART TX signal from the baseboard Ground

15

NCSI_TX_D1

Input

Transmit Data In 0. Data signals from the BMC to the network controller.

For baseboards, this pin should be connected between the baseboard NC-SI over RBT PHY and the connector. This signal requires a 100 kΩ pull-down resistor to GND on the baseboard between the RBT isolator and the DPUcable connector to prevent the card-side signals from floating when the RBT signals are isolated.

For DPUs, this pin should be connected between the connector and the RBT PHY. External termination is determined by the DPU RBT PHY requirements.

16

BMC_TX5

Output

UART transmit serial data output. 3.3V UART TX signal to the baseboard.

17

PRESENCE_N

Output

Presence of SmartNIC

The baseboard should implement a 200 Ω series resistor and 4.7kohm pull-up resistor to 3.3V AUX.

SmartNIC should tie this to GND.

18

GND

Ground

Ground

19

NCSI_ARB_IN

Input

NC-SI hardware arbitration input

If the baseboard supports multiple DPU cards connected to the same RBT interface, it should implement logic that connects the RBT_ARB_IN pin of the first populated DPU card to its RBT_ARB_OUT pin if it is the only card present or to the RBT_ARB_OUT pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic should bypass slots that are not populated or powered off.

20

NCSI_ARB_OUT

Output

NC-SI hardware arbitration output.

If the baseboard supports multiple DPU cards connected to the same RBT interface, it should implement logic that connects the RBT_ARB_OUT pin of the first populated DPU card to its RBT_ARB_IN pin if it is the only card present or to the RBT_ARB_IN pin of the next populated card and so on sequentially for all cards on the specified RBT bus to ensure the arbitration ring is complete. This logic should bypass slots that are not populated or powered off.


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