1.20. Field Identifiers

Field Identifiers

Defines

#define DCGM_FI_CUDA_DRIVER_VERSION 5
#define DCGM_FI_DEV_ACCOUNTING_DATA 205
#define DCGM_FI_DEV_APP_MEM_CLOCK 111
#define DCGM_FI_DEV_APP_SM_CLOCK 110
#define DCGM_FI_DEV_AUTOBOOST 120
#define DCGM_FI_DEV_BAR1_FREE 93
#define DCGM_FI_DEV_BAR1_TOTAL 90
#define DCGM_FI_DEV_BAR1_USED 92
#define DCGM_FI_DEV_BOARD_LIMIT_VIOLATION 243
#define DCGM_FI_DEV_BRAND 51
#define DCGM_FI_DEV_CLOCK_THROTTLE_REASONS 112
#define DCGM_FI_DEV_COMPUTE_MODE 65
#define DCGM_FI_DEV_COMPUTE_PIDS 221
#define DCGM_FI_DEV_CORRECTABLE_REMAPPED_ROWS 394
#define DCGM_FI_DEV_COUNT 4
#define DCGM_FI_DEV_CPU_AFFINITY_0 70
#define DCGM_FI_DEV_CPU_AFFINITY_1 71
#define DCGM_FI_DEV_CPU_AFFINITY_2 72
#define DCGM_FI_DEV_CPU_AFFINITY_3 73
#define DCGM_FI_DEV_CREATABLE_VGPU_TYPE_IDS 502
#define DCGM_FI_DEV_CUDA_COMPUTE_CAPABILITY 63
#define DCGM_FI_DEV_CUDA_VISIBLE_DEVICES_STR 68
#define DCGM_FI_DEV_DEC_UTIL 207
#define DCGM_FI_DEV_ECC_CURRENT 300
#define DCGM_FI_DEV_ECC_DBE_AGG_DEV 329
#define DCGM_FI_DEV_ECC_DBE_AGG_L1 325
#define DCGM_FI_DEV_ECC_DBE_AGG_L2 327
#define DCGM_FI_DEV_ECC_DBE_AGG_REG 331
#define DCGM_FI_DEV_ECC_DBE_AGG_TEX 333
#define DCGM_FI_DEV_ECC_DBE_AGG_TOTAL 313
#define DCGM_FI_DEV_ECC_DBE_VOL_DEV 319
#define DCGM_FI_DEV_ECC_DBE_VOL_L1 315
#define DCGM_FI_DEV_ECC_DBE_VOL_L2 317
#define DCGM_FI_DEV_ECC_DBE_VOL_REG 321
#define DCGM_FI_DEV_ECC_DBE_VOL_TEX 323
#define DCGM_FI_DEV_ECC_DBE_VOL_TOTAL 311
#define DCGM_FI_DEV_ECC_INFOROM_VER 80
#define DCGM_FI_DEV_ECC_PENDING 301
#define DCGM_FI_DEV_ECC_SBE_AGG_DEV 328
#define DCGM_FI_DEV_ECC_SBE_AGG_L1 324
#define DCGM_FI_DEV_ECC_SBE_AGG_L2 326
#define DCGM_FI_DEV_ECC_SBE_AGG_REG 330
#define DCGM_FI_DEV_ECC_SBE_AGG_TEX 332
#define DCGM_FI_DEV_ECC_SBE_AGG_TOTAL 312
#define DCGM_FI_DEV_ECC_SBE_VOL_DEV 318
#define DCGM_FI_DEV_ECC_SBE_VOL_L1 314
#define DCGM_FI_DEV_ECC_SBE_VOL_L2 316
#define DCGM_FI_DEV_ECC_SBE_VOL_REG 320
#define DCGM_FI_DEV_ECC_SBE_VOL_TEX 322
#define DCGM_FI_DEV_ECC_SBE_VOL_TOTAL 310
#define DCGM_FI_DEV_ENC_STATS 506
#define DCGM_FI_DEV_ENC_UTIL 206
#define DCGM_FI_DEV_ENFORCED_POWER_LIMIT 164
#define DCGM_FI_DEV_FAN_SPEED 191
#define DCGM_FI_DEV_FBC_SESSIONS_INFO 508
#define DCGM_FI_DEV_FBC_STATS 507
#define DCGM_FI_DEV_FB_FREE 251
#define DCGM_FI_DEV_FB_TOTAL 250
#define DCGM_FI_DEV_FB_USED 252
#define DCGM_FI_DEV_GPU_MAX_OP_TEMP 152
#define DCGM_FI_DEV_GPU_TEMP 150
#define DCGM_FI_DEV_GPU_UTIL 203
#define DCGM_FI_DEV_GRAPHICS_PIDS 220
#define DCGM_FI_DEV_INFOROM_CONFIG_CHECK 83
#define DCGM_FI_DEV_INFOROM_CONFIG_VALID 84
#define DCGM_FI_DEV_INFOROM_IMAGE_VER 82
#define DCGM_FI_DEV_LOW_UTIL_VIOLATION 244
#define DCGM_FI_DEV_MAX_MEM_CLOCK 114
#define DCGM_FI_DEV_MAX_SM_CLOCK 113
#define DCGM_FI_DEV_MAX_VIDEO_CLOCK 115
#define DCGM_FI_DEV_MEMORY_TEMP 140
#define DCGM_FI_DEV_MEM_CLOCK 101
#define DCGM_FI_DEV_MEM_COPY_UTIL 204
#define DCGM_FI_DEV_MEM_COPY_UTIL_SAMPLES 210
#define DCGM_FI_DEV_MEM_MAX_OP_TEMP 151
#define DCGM_FI_DEV_MIG_MODE 67
#define DCGM_FI_DEV_MINOR_NUMBER 55
#define DCGM_FI_DEV_NAME 50
#define DCGM_FI_DEV_NVML_INDEX 52
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P00 781
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P01 783
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P02 785
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P03 787
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P04 789
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P05 791
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P06 793
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P07 795
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P08 797
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P09 799
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P10 801
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P11 803
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P12 805
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P13 807
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P14 809
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P15 811
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P16 813
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P17 815
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P00 821
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P01 823
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P02 825
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P03 827
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P04 829
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P05 831
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P06 833
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P07 835
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P08 837
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P09 839
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P10 841
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P11 843
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P12 845
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P13 847
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P14 849
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P15 851
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P16 853
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P17 855
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P00 780
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P01 782
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P02 784
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P03 786
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P04 788
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P05 790
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P06 792
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P07 794
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P08 796
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P09 798
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P10 800
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P11 802
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P12 804
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P13 806
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P14 808
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P15 810
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P16 812
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P17 814
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P00 820
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P01 822
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P02 824
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P03 826
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P04 828
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P05 830
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P06 832
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P07 834
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P08 836
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P09 838
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P10 840
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P11 842
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P12 844
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P13 846
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P14 848
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P15 850
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P16 852
#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P17 854
#define DCGM_FI_DEV_NVSWITCH_FATAL_ERRORS 856
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P00 702
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P01 706
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P02 710
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P03 714
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P04 718
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P05 722
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P06 726
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P07 730
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P08 734
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P09 738
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P10 742
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P11 746
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P12 750
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P13 754
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P14 758
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P15 762
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P16 766
#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P17 770
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P00 700
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P01 704
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P02 708
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P03 712
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P04 716
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P05 720
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P06 724
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P07 728
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P08 732
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P09 736
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P10 740
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P11 744
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P12 748
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P13 752
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P14 756
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P15 760
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P16 764
#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P17 768
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P00 703
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P01 707
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P02 711
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P03 715
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P04 719
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P05 723
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P06 727
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P07 731
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P08 735
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P09 739
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P10 743
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P11 747
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P12 751
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P13 755
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P14 759
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P15 763
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P16 767
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P17 771
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P00 701
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P01 705
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P02 709
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P03 713
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P04 717
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P05 721
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P06 725
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P07 729
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P08 733
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P09 737
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P10 741
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P11 745
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P12 749
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P13 753
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P14 757
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P15 761
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P16 765
#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P17 769
#define DCGM_FI_DEV_NVSWITCH_NON_FATAL_ERRORS 857
#define DCGM_FI_DEV_OEM_INFOROM_VER 56
#define DCGM_FI_DEV_PCIE_LINK_GEN 237
#define DCGM_FI_DEV_PCIE_LINK_WIDTH 238
#define DCGM_FI_DEV_PCIE_MAX_LINK_GEN 235
#define DCGM_FI_DEV_PCIE_MAX_LINK_WIDTH 236
#define DCGM_FI_DEV_PCIE_REPLAY_COUNTER 202
#define DCGM_FI_DEV_PCIE_RX_THROUGHPUT 201
#define DCGM_FI_DEV_PCIE_TX_THROUGHPUT 200
#define DCGM_FI_DEV_PCI_BUSID 57
#define DCGM_FI_DEV_PCI_COMBINED_ID 58
#define DCGM_FI_DEV_PCI_SUBSYS_ID 59
#define DCGM_FI_DEV_PERSISTENCE_MODE 66
#define DCGM_FI_DEV_POWER_INFOROM_VER 81
#define DCGM_FI_DEV_POWER_MGMT_LIMIT 160
#define DCGM_FI_DEV_POWER_MGMT_LIMIT_DEF 163
#define DCGM_FI_DEV_POWER_MGMT_LIMIT_MAX 162
#define DCGM_FI_DEV_POWER_MGMT_LIMIT_MIN 161
#define DCGM_FI_DEV_POWER_USAGE 155
#define DCGM_FI_DEV_POWER_VIOLATION 240
#define DCGM_FI_DEV_PSTATE 190
#define DCGM_FI_DEV_RELIABILITY_VIOLATION 245
#define DCGM_FI_DEV_RETIRED_DBE 391
#define DCGM_FI_DEV_RETIRED_PENDING 392
#define DCGM_FI_DEV_RETIRED_SBE 390
#define DCGM_FI_DEV_ROW_REMAP_FAILURE 395
#define DCGM_FI_DEV_SERIAL 53
#define DCGM_FI_DEV_SHUTDOWN_TEMP 159
#define DCGM_FI_DEV_SLOWDOWN_TEMP 158
#define DCGM_FI_DEV_SM_CLOCK 100
#define DCGM_FI_DEV_SUPPORTED_CLOCKS 130
#define DCGM_FI_DEV_SUPPORTED_TYPE_INFO 501
#define DCGM_FI_DEV_SYNC_BOOST_VIOLATION 242
#define DCGM_FI_DEV_THERMAL_VIOLATION 241
#define DCGM_FI_DEV_TOTAL_APP_CLOCKS_VIOLATION 246
#define DCGM_FI_DEV_TOTAL_BASE_CLOCKS_VIOLATION 247
#define DCGM_FI_DEV_TOTAL_ENERGY_CONSUMPTION 156
#define DCGM_FI_DEV_UNCORRECTABLE_REMAPPED_ROWS 393
#define DCGM_FI_DEV_UUID 54
#define DCGM_FI_DEV_VBIOS_VERSION 85
#define DCGM_FI_DEV_VGPU_DRIVER_VERSION 524
#define DCGM_FI_DEV_VGPU_ENC_SESSIONS_INFO 529
#define DCGM_FI_DEV_VGPU_ENC_STATS 528
#define DCGM_FI_DEV_VGPU_FBC_SESSIONS_INFO 531
#define DCGM_FI_DEV_VGPU_FBC_STATS 530
#define DCGM_FI_DEV_VGPU_FRAME_RATE_LIMIT 527
#define DCGM_FI_DEV_VGPU_INSTANCE_IDS 503
#define DCGM_FI_DEV_VGPU_LICENSE_STATUS 526
#define DCGM_FI_DEV_VGPU_MEMORY_USAGE 525
#define DCGM_FI_DEV_VGPU_PER_PROCESS_UTILIZATION 505
#define DCGM_FI_DEV_VGPU_TYPE 522
#define DCGM_FI_DEV_VGPU_UTILIZATIONS 504
#define DCGM_FI_DEV_VGPU_UUID 523
#define DCGM_FI_DEV_VGPU_VM_ID 520
#define DCGM_FI_DEV_VGPU_VM_NAME 521
#define DCGM_FI_DEV_VIDEO_CLOCK 102
#define DCGM_FI_DEV_VIRTUAL_MODE 500
#define DCGM_FI_DEV_XID_ERRORS 230
#define DCGM_FI_DRIVER_VERSION 1
#define DCGM_FI_FIRST_NVSWITCH_FIELD_ID 700
#define DCGM_FI_FIRST_VGPU_FIELD_ID 520
#define DCGM_FI_GPU_TOPOLOGY_AFFINITY 62
#define DCGM_FI_GPU_TOPOLOGY_NVLINK 61
#define DCGM_FI_GPU_TOPOLOGY_PCI 60
#define DCGM_FI_INTERNAL_FIELDS_0_END 699
#define DCGM_FI_INTERNAL_FIELDS_0_START 600
#define DCGM_FI_LAST_NVSWITCH_FIELD_ID 860
#define DCGM_FI_LAST_VGPU_FIELD_ID 570
#define DCGM_FI_MAX_FIELDS 1013
#define DCGM_FI_MAX_NVSWITCH_FIELDS
#define DCGM_FI_MAX_VGPU_FIELDS
#define DCGM_FI_PROF_DRAM_ACTIVE 1005
#define DCGM_FI_PROF_GR_ENGINE_ACTIVE 1001
#define DCGM_FI_PROF_NVLINK_RX_BYTES 1012
#define DCGM_FI_PROF_NVLINK_TX_BYTES 1011
#define DCGM_FI_PROF_PCIE_RX_BYTES 1010
#define DCGM_FI_PROF_PCIE_TX_BYTES 1009
#define DCGM_FI_PROF_PIPE_FP16_ACTIVE 1008
#define DCGM_FI_PROF_PIPE_FP32_ACTIVE 1007
#define DCGM_FI_PROF_PIPE_FP64_ACTIVE 1006
#define DCGM_FI_PROF_PIPE_TENSOR_ACTIVE 1004
#define DCGM_FI_PROF_SM_ACTIVE 1002
#define DCGM_FI_PROF_SM_OCCUPANCY 1003
#define DCGM_FI_SYNC_BOOST 91
#define DCGM_FI_UNKNOWN 0

Functions

dcgm_field_meta_p DcgmFieldGetById ( unsigned short fieldId )
dcgm_field_meta_p DcgmFieldGetByTag ( char* tag )
char* DcgmFieldsGetEntityGroupString ( dcgm_field_entity_group_t entityGroupId )
int  DcgmFieldsInit ( void )
int  DcgmFieldsTerm ( void )

Defines

#define DCGM_FI_CUDA_DRIVER_VERSION 5

Cuda Driver Version Retrieves a number with the major value in the thousands place and the minor value in the hundreds place. CUDA 11.1 = 11100

#define DCGM_FI_DEV_ACCOUNTING_DATA 205

Process accounting stats.

This field is only supported when the host engine is running as root unless you enable accounting ahead of time. Accounting mode can be enabled by running "nvidia-smi -am 1" as root on the same node the host engine is running on.

#define DCGM_FI_DEV_APP_MEM_CLOCK 111

Memory Application clocks

#define DCGM_FI_DEV_APP_SM_CLOCK 110

SM Application clocks

#define DCGM_FI_DEV_AUTOBOOST 120

Auto-boost for the device (1 = enabled. 0 = disabled)

#define DCGM_FI_DEV_BAR1_FREE 93

Free BAR1 of the GPU in MB

#define DCGM_FI_DEV_BAR1_TOTAL 90

Total BAR1 of the GPU in MB

#define DCGM_FI_DEV_BAR1_USED 92

Used BAR1 of the GPU in MB

#define DCGM_FI_DEV_BOARD_LIMIT_VIOLATION 243

Board violation limit.

#define DCGM_FI_DEV_BRAND 51

Device Brand

#define DCGM_FI_DEV_CLOCK_THROTTLE_REASONS 112

Current clock throttle reasons (bitmask of DCGM_CLOCKS_THROTTLE_REASON_*)

#define DCGM_FI_DEV_COMPUTE_MODE 65

Compute mode for the device

#define DCGM_FI_DEV_COMPUTE_PIDS 221

Compute processes running on the GPU.

#define DCGM_FI_DEV_CORRECTABLE_REMAPPED_ROWS 394

Number of remapped rows for correctable errors

#define DCGM_FI_DEV_COUNT 4

Number of Devices on the node

#define DCGM_FI_DEV_CPU_AFFINITY_0 70

Device CPU affinity. part 1/8 = cpus 0 - 63

#define DCGM_FI_DEV_CPU_AFFINITY_1 71

Device CPU affinity. part 1/8 = cpus 64 - 127

#define DCGM_FI_DEV_CPU_AFFINITY_2 72

Device CPU affinity. part 2/8 = cpus 128 - 191

#define DCGM_FI_DEV_CPU_AFFINITY_3 73

Device CPU affinity. part 3/8 = cpus 192 - 255

#define DCGM_FI_DEV_CREATABLE_VGPU_TYPE_IDS 502

Includes Count and currently Creatable vGPU types on a device

#define DCGM_FI_DEV_CUDA_COMPUTE_CAPABILITY 63

Cuda compute capability for the device. The major version is the upper 32 bits and the minor version is the lower 32 bits.

#define DCGM_FI_DEV_CUDA_VISIBLE_DEVICES_STR 68

The string that CUDA_VISIBLE_DEVICES should be set to for this entity (including MIG)

#define DCGM_FI_DEV_DEC_UTIL 207

Decoder Utilization

#define DCGM_FI_DEV_ECC_CURRENT 300

Current ECC mode for the device

#define DCGM_FI_DEV_ECC_DBE_AGG_DEV 329

Device memory double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_AGG_L1 325

L1 cache double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_AGG_L2 327

L2 cache double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_AGG_REG 331

Register File double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_AGG_TEX 333

Texture memory double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_AGG_TOTAL 313

Total double bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_DBE_VOL_DEV 319

Device memory double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_DBE_VOL_L1 315

L1 cache double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_DBE_VOL_L2 317

L2 cache double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_DBE_VOL_REG 321

Register file double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_DBE_VOL_TEX 323

Texture memory double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_DBE_VOL_TOTAL 311

Total double bit volatile ECC errors

#define DCGM_FI_DEV_ECC_INFOROM_VER 80

ECC inforom version

#define DCGM_FI_DEV_ECC_PENDING 301

Pending ECC mode for the device

#define DCGM_FI_DEV_ECC_SBE_AGG_DEV 328

Device memory single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_AGG_L1 324

L1 cache single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_AGG_L2 326

L2 cache single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_AGG_REG 330

Register File single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_AGG_TEX 332

Texture memory single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_AGG_TOTAL 312

Total single bit aggregate (persistent) ECC errors Note: monotonically increasing

#define DCGM_FI_DEV_ECC_SBE_VOL_DEV 318

Device memory single bit volatile ECC errors

#define DCGM_FI_DEV_ECC_SBE_VOL_L1 314

L1 cache single bit volatile ECC errors

#define DCGM_FI_DEV_ECC_SBE_VOL_L2 316

L2 cache single bit volatile ECC errors

#define DCGM_FI_DEV_ECC_SBE_VOL_REG 320

Register file single bit volatile ECC errors

#define DCGM_FI_DEV_ECC_SBE_VOL_TEX 322

Texture memory single bit volatile ECC errors

#define DCGM_FI_DEV_ECC_SBE_VOL_TOTAL 310

Total single bit volatile ECC errors

#define DCGM_FI_DEV_ENC_STATS 506

Current encoder statistics for a given device

#define DCGM_FI_DEV_ENC_UTIL 206

Encoder Utilization

#define DCGM_FI_DEV_ENFORCED_POWER_LIMIT 164

Effective power limit that the driver enforces after taking into account all limiters

#define DCGM_FI_DEV_FAN_SPEED 191

Fan speed for the device in percent 0-100

#define DCGM_FI_DEV_FBC_SESSIONS_INFO 508

Information about active frame buffer capture sessions on a target device

#define DCGM_FI_DEV_FBC_STATS 507

Statistics of current active frame buffer capture sessions on a given device

#define DCGM_FI_DEV_FB_FREE 251

Free Frame Buffer in MB

#define DCGM_FI_DEV_FB_TOTAL 250

Total Frame Buffer of the GPU in MB

#define DCGM_FI_DEV_FB_USED 252

Used Frame Buffer in MB

#define DCGM_FI_DEV_GPU_MAX_OP_TEMP 152

Maximum operating temperature for this GPU

#define DCGM_FI_DEV_GPU_TEMP 150

Current temperature readings for the device, in degrees C

#define DCGM_FI_DEV_GPU_UTIL 203

GPU Utilization

#define DCGM_FI_DEV_GRAPHICS_PIDS 220

Graphics processes running on the GPU.

#define DCGM_FI_DEV_INFOROM_CONFIG_CHECK 83

Inforom configuration checksum

#define DCGM_FI_DEV_INFOROM_CONFIG_VALID 84

Reads the infoROM from the flash and verifies the checksums

#define DCGM_FI_DEV_INFOROM_IMAGE_VER 82

Inforom image version

#define DCGM_FI_DEV_LOW_UTIL_VIOLATION 244

Low utilisation violation limit.

#define DCGM_FI_DEV_MAX_MEM_CLOCK 114

Maximum supported Memory clock for the device

#define DCGM_FI_DEV_MAX_SM_CLOCK 113

Maximum supported SM clock for the device

#define DCGM_FI_DEV_MAX_VIDEO_CLOCK 115

Maximum supported Video encoder/decoder clock for the device

#define DCGM_FI_DEV_MEMORY_TEMP 140

Memory temperature for the device

#define DCGM_FI_DEV_MEM_CLOCK 101

Memory clock for the device

#define DCGM_FI_DEV_MEM_COPY_UTIL 204

Memory Utilization

#define DCGM_FI_DEV_MEM_COPY_UTIL_SAMPLES 210

Memory utilization samples

#define DCGM_FI_DEV_MEM_MAX_OP_TEMP 151

Maximum operating temperature for the memory of this GPU

#define DCGM_FI_DEV_MIG_MODE 67

MIG mode for the device Boolean: 0 is disabled, 1 is enabled

#define DCGM_FI_DEV_MINOR_NUMBER 55

Device node minor number /dev/nvidia#

#define DCGM_FI_DEV_NAME 50

Name of the GPU device

#define DCGM_FI_DEV_NVML_INDEX 52

NVML index of this GPU

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P00 781

NVSwitch Rx Bandwidth Counter 0 for port 0

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P01 783

NVSwitch Rx Bandwidth Counter 0 for port 1

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P02 785

NVSwitch Rx Bandwidth Counter 0 for port 2

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P03 787

NVSwitch Rx Bandwidth Counter 0 for port 3

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P04 789

NVSwitch Rx Bandwidth Counter 0 for port 4

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P05 791

NVSwitch Rx Bandwidth Counter 0 for port 5

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P06 793

NVSwitch Rx Bandwidth Counter 0 for port 6

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P07 795

NVSwitch Rx Bandwidth Counter 0 for port 7

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P08 797

NVSwitch Rx Bandwidth Counter 0 for port 8

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P09 799

NVSwitch Rx Bandwidth Counter 0 for port 9

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P10 801

NVSwitch Rx Bandwidth Counter 0 for port 10

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P11 803

NVSwitch Rx Bandwidth Counter 0 for port 11

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P12 805

NVSwitch Rx Bandwidth Counter 0 for port 12

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P13 807

NVSwitch Rx Bandwidth Counter 0 for port 13

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P14 809

NVSwitch Rx Bandwidth Counter 0 for port 14

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P15 811

NVSwitch Rx Bandwidth Counter 0 for port 15

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P16 813

NVSwitch Rx Bandwidth Counter 0 for port 16

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_0_P17 815

NVSwitch Rx Bandwidth Counter 0 for port 17

NVSwitch Tx and RX Bandwidth Counter 1 for each port

By default, Counter 1 counts packets.

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P00 821

NVSwitch Rx Bandwidth Counter 1 for port 0

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P01 823

NVSwitch Rx Bandwidth Counter 1 for port 1

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P02 825

NVSwitch Rx Bandwidth Counter 1 for port 2

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P03 827

NVSwitch Rx Bandwidth Counter 1 for port 3

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P04 829

NVSwitch Rx Bandwidth Counter 1 for port 4

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P05 831

NVSwitch Rx Bandwidth Counter 1 for port 5

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P06 833

NVSwitch Rx Bandwidth Counter 1 for port 6

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P07 835

NVSwitch Rx Bandwidth Counter 1 for port 7

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P08 837

NVSwitch Rx Bandwidth Counter 1 for port 8

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P09 839

NVSwitch Rx Bandwidth Counter 1 for port 9

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P10 841

NVSwitch Rx Bandwidth Counter 1 for port 10

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P11 843

NVSwitch Rx Bandwidth Counter 1 for port 11

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P12 845

NVSwitch Rx Bandwidth Counter 1 for port 12

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P13 847

NVSwitch Rx Bandwidth Counter 1 for port 13

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P14 849

NVSwitch Rx Bandwidth Counter 1 for port 14

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P15 851

NVSwitch Rx Bandwidth Counter 1 for port 15

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P16 853

NVSwitch Rx Bandwidth Counter 1 for port 16

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_RX_1_P17 855

NVSwitch Rx Bandwidth Counter 1 for port 17

NVSwitch error counters

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P00 780

NVSwitch Tx Bandwidth Counter 0 for port 0

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P01 782

NVSwitch Tx Bandwidth Counter 0 for port 1

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P02 784

NVSwitch Tx Bandwidth Counter 0 for port 2

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P03 786

NVSwitch Tx Bandwidth Counter 0 for port 3

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P04 788

NVSwitch Tx Bandwidth Counter 0 for port 4

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P05 790

NVSwitch Tx Bandwidth Counter 0 for port 5

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P06 792

NVSwitch Tx Bandwidth Counter 0 for port 6

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P07 794

NVSwitch Tx Bandwidth Counter 0 for port 7

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P08 796

NVSwitch Tx Bandwidth Counter 0 for port 8

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P09 798

NVSwitch Tx Bandwidth Counter 0 for port 9

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P10 800

NVSwitch Tx Bandwidth Counter 0 for port 10

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P11 802

NVSwitch Tx Bandwidth Counter 0 for port 11

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P12 804

NVSwitch Tx Bandwidth Counter 0 for port 12

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P13 806

NVSwitch Tx Bandwidth Counter 0 for port 13

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P14 808

NVSwitch Tx Bandwidth Counter 0 for port 14

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P15 810

NVSwitch Tx Bandwidth Counter 0 for port 15

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P16 812

NVSwitch Tx Bandwidth Counter 0 for port 16

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_0_P17 814

NVSwitch Tx Bandwidth Counter 0 for port 17

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P00 820

NVSwitch Tx Bandwidth Counter 1 for port 0

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P01 822

NVSwitch Tx Bandwidth Counter 1 for port 1

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P02 824

NVSwitch Tx Bandwidth Counter 1 for port 2

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P03 826

NVSwitch Tx Bandwidth Counter 1 for port 3

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P04 828

NVSwitch Tx Bandwidth Counter 1 for port 4

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P05 830

NVSwitch Tx Bandwidth Counter 1 for port 5

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P06 832

NVSwitch Tx Bandwidth Counter 1 for port 6

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P07 834

NVSwitch Tx Bandwidth Counter 1 for port 7

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P08 836

NVSwitch Tx Bandwidth Counter 1 for port 8

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P09 838

NVSwitch Tx Bandwidth Counter 1 for port 9

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P10 840

NVSwitch Tx Bandwidth Counter 0 for port 10

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P11 842

NVSwitch Tx Bandwidth Counter 1 for port 11

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P12 844

NVSwitch Tx Bandwidth Counter 1 for port 12

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P13 846

NVSwitch Tx Bandwidth Counter 0 for port 13

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P14 848

NVSwitch Tx Bandwidth Counter 1 for port 14

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P15 850

NVSwitch Tx Bandwidth Counter 1 for port 15

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P16 852

NVSwitch Tx Bandwidth Counter 1 for port 16

#define DCGM_FI_DEV_NVSWITCH_BANDWIDTH_TX_1_P17 854

NVSwitch Tx Bandwidth Counter 1 for port 17

#define DCGM_FI_DEV_NVSWITCH_FATAL_ERRORS 856

NVSwitch fatal error information. Note: value field indicates the specific SXid reported

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P00 702

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P01 706

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P02 710

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P03 714

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P04 718

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P05 722

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P06 726

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P07 730

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P08 734

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P09 738

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P10 742

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P11 746

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P12 750

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P13 754

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P14 758

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P15 762

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P16 766

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_HIGH_P17 770

High latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P00 700

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P01 704

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P02 708

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P03 712

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P04 716

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P05 720

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P06 724

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P07 728

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P08 732

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P09 736

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P10 740

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P11 744

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P12 748

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P13 752

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P14 756

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P15 760

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P16 764

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_LOW_P17 768

Low latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P00 703

Max latency bin

NVSwitch latency bins for port 1

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P01 707

Max latency bin

NVSwitch latency bins for port 2

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P02 711

Max latency bin

NVSwitch latency bins for port 3

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P03 715

Max latency bin

NVSwitch latency bins for port 4

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P04 719

Max latency bin

NVSwitch latency bins for port 5

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P05 723

Max latency bin

NVSwitch latency bins for port 6

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P06 727

Max latency bin

NVSwitch latency bins for port 7

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P07 731

Max latency bin

NVSwitch latency bins for port 8

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P08 735

Max latency bin

NVSwitch latency bins for port 9

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P09 739

Max latency bin

NVSwitch latency bins for port 10

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P10 743

Max latency bin

NVSwitch latency bins for port 11

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P11 747

Max latency bin

NVSwitch latency bins for port 12

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P12 751

Max latency bin

NVSwitch latency bins for port 13

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P13 755

Max latency bin

NVSwitch latency bins for port 14

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P14 759

Max latency bin

NVSwitch latency bins for port 15

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P15 763

Max latency bin

NVSwitch latency bins for port 16

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P16 767

Max latency bin

NVSwitch latency bins for port 17

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MAX_P17 771

Max latency bin

NVSwitch Tx and Rx Counter 0 for each port

By default, Counter 0 counts bytes.

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P00 701

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P01 705

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P02 709

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P03 713

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P04 717

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P05 721

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P06 725

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P07 729

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P08 733

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P09 737

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P10 741

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P11 745

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P12 749

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P13 753

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P14 757

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P15 761

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P16 765

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_LATENCY_MED_P17 769

Medium latency bin

#define DCGM_FI_DEV_NVSWITCH_NON_FATAL_ERRORS 857

NVSwitch non fatal error information. Note: value field indicates the specific SXid reported

#define DCGM_FI_DEV_OEM_INFOROM_VER 56

OEM inforom version

#define DCGM_FI_DEV_PCIE_LINK_GEN 237

PCIe Current Link Generation

#define DCGM_FI_DEV_PCIE_LINK_WIDTH 238

PCIe Current Link Width

#define DCGM_FI_DEV_PCIE_MAX_LINK_GEN 235

PCIe Max Link Generation

#define DCGM_FI_DEV_PCIE_MAX_LINK_WIDTH 236

PCIe Max Link Width

#define DCGM_FI_DEV_PCIE_REPLAY_COUNTER 202

PCIe replay counter

#define DCGM_FI_DEV_PCIE_RX_THROUGHPUT 201

PCIe Rx utilization information

Deprecated: Use DCGM_FI_PROF_PCIE_RX_BYTES instead.

#define DCGM_FI_DEV_PCIE_TX_THROUGHPUT 200

PCIe Tx utilization information

Deprecated: Use DCGM_FI_PROF_PCIE_TX_BYTES instead.

#define DCGM_FI_DEV_PCI_BUSID 57

PCI attributes for the device

#define DCGM_FI_DEV_PCI_COMBINED_ID 58

The combined 16-bit device id and 16-bit vendor id

#define DCGM_FI_DEV_PCI_SUBSYS_ID 59

The 32-bit Sub System Device ID

#define DCGM_FI_DEV_PERSISTENCE_MODE 66

Persistence mode for the device Boolean: 0 is disabled, 1 is enabled

#define DCGM_FI_DEV_POWER_INFOROM_VER 81

Power management object inforom version

#define DCGM_FI_DEV_POWER_MGMT_LIMIT 160

Current Power limit for the device

#define DCGM_FI_DEV_POWER_MGMT_LIMIT_DEF 163

Default power management limit for the device

#define DCGM_FI_DEV_POWER_MGMT_LIMIT_MAX 162

Maximum power management limit for the device

#define DCGM_FI_DEV_POWER_MGMT_LIMIT_MIN 161

Minimum power management limit for the device

#define DCGM_FI_DEV_POWER_USAGE 155

Power usage for the device in Watts

#define DCGM_FI_DEV_POWER_VIOLATION 240

Power Violation time in usec

#define DCGM_FI_DEV_PSTATE 190

Performance state (P-State) 0-15. 0=highest

#define DCGM_FI_DEV_RELIABILITY_VIOLATION 245

Reliability violation limit.

#define DCGM_FI_DEV_RETIRED_DBE 391

Number of retired pages because of double bit errors Note: monotonically increasing

#define DCGM_FI_DEV_RETIRED_PENDING 392

Number of pages pending retirement

#define DCGM_FI_DEV_RETIRED_SBE 390

Number of retired pages because of single bit errors Note: monotonically increasing

#define DCGM_FI_DEV_ROW_REMAP_FAILURE 395

Whether remapping of rows has failed

#define DCGM_FI_DEV_SERIAL 53

Device Serial Number

#define DCGM_FI_DEV_SHUTDOWN_TEMP 159

Shutdown temperature for the device

#define DCGM_FI_DEV_SLOWDOWN_TEMP 158

Slowdown temperature for the device

#define DCGM_FI_DEV_SM_CLOCK 100

SM clock for the device

#define DCGM_FI_DEV_SUPPORTED_CLOCKS 130

Supported clocks for the device

#define DCGM_FI_DEV_SUPPORTED_TYPE_INFO 501

Includes Count and Static info of vGPU types supported on a device

#define DCGM_FI_DEV_SYNC_BOOST_VIOLATION 242

Sync Boost Violation time in usec

#define DCGM_FI_DEV_THERMAL_VIOLATION 241

Thermal Violation time in usec

#define DCGM_FI_DEV_TOTAL_APP_CLOCKS_VIOLATION 246

App clock violation limit.

#define DCGM_FI_DEV_TOTAL_BASE_CLOCKS_VIOLATION 247

Base clock violation limit.

#define DCGM_FI_DEV_TOTAL_ENERGY_CONSUMPTION 156

Total energy consumption for the GPU in mJ since the driver was last reloaded

#define DCGM_FI_DEV_UNCORRECTABLE_REMAPPED_ROWS 393

Number of remapped rows for uncorrectable errors

#define DCGM_FI_DEV_UUID 54

UUID corresponding to the device

#define DCGM_FI_DEV_VBIOS_VERSION 85

VBIOS version of the device

#define DCGM_FI_DEV_VGPU_DRIVER_VERSION 524

Driver version of the vGPU instance

#define DCGM_FI_DEV_VGPU_ENC_SESSIONS_INFO 529

Information about all active encoder sessions on the vGPU instance

#define DCGM_FI_DEV_VGPU_ENC_STATS 528

Current encoder statistics of the vGPU instance

#define DCGM_FI_DEV_VGPU_FBC_SESSIONS_INFO 531

Information about active frame buffer capture sessions on the vGPU instance

#define DCGM_FI_DEV_VGPU_FBC_STATS 530

Statistics of current active frame buffer capture sessions on the vGPU instance

#define DCGM_FI_DEV_VGPU_FRAME_RATE_LIMIT 527

Frame rate limit of the vGPU instance

#define DCGM_FI_DEV_VGPU_INSTANCE_IDS 503

Includes Count and currently Active vGPU Instances on a device

#define DCGM_FI_DEV_VGPU_LICENSE_STATUS 526

License status of the vGPU instance

#define DCGM_FI_DEV_VGPU_MEMORY_USAGE 525

Memory usage of the vGPU instance

#define DCGM_FI_DEV_VGPU_PER_PROCESS_UTILIZATION 505

Utilization values for processes running within vGPU VMs using the device

#define DCGM_FI_DEV_VGPU_TYPE 522

vGPU type of the vGPU instance

#define DCGM_FI_DEV_VGPU_UTILIZATIONS 504

Utilization values for vGPUs running on the device

#define DCGM_FI_DEV_VGPU_UUID 523

UUID of the vGPU instance

#define DCGM_FI_DEV_VGPU_VM_ID 520

VM ID of the vGPU instance

#define DCGM_FI_DEV_VGPU_VM_NAME 521

VM name of the vGPU instance

#define DCGM_FI_DEV_VIDEO_CLOCK 102

Video encoder/decoder clock for the device

#define DCGM_FI_DEV_VIRTUAL_MODE 500

Virtualization Mode corresponding to the GPU.

One of DCGM_GPU_VIRTUALIZATION_MODE_* constants.

#define DCGM_FI_DEV_XID_ERRORS 230

XID errors. The value is the specific XID error

#define DCGM_FI_DRIVER_VERSION 1

Driver Version

#define DCGM_FI_FIRST_NVSWITCH_FIELD_ID 700

Starting field ID of the NVSwitch instance

#define DCGM_FI_FIRST_VGPU_FIELD_ID 520

Starting field ID of the vGPU instance

#define DCGM_FI_GPU_TOPOLOGY_AFFINITY 62

Affinity of all GPUs on the system (static)

#define DCGM_FI_GPU_TOPOLOGY_NVLINK 61

Topology of all GPUs on the system via NVLINK (static)

#define DCGM_FI_GPU_TOPOLOGY_PCI 60

Topology of all GPUs on the system via PCI (static)

#define DCGM_FI_INTERNAL_FIELDS_0_END 699

Last ID for all the internal fields

NVSwitch entity field IDs start here.

NVSwitch latency bins for port 0

#define DCGM_FI_INTERNAL_FIELDS_0_START 600

Starting ID for all the internal fields

#define DCGM_FI_LAST_NVSWITCH_FIELD_ID 860

Last field ID of the NVSwitch instance

#define DCGM_FI_LAST_VGPU_FIELD_ID 570

Last field ID of the vGPU instance

#define DCGM_FI_MAX_FIELDS 1013

1 greater than maximum fields above. This is the 1 greater than the maximum field id that could be allocated

#define DCGM_FI_MAX_NVSWITCH_FIELDS

For now max NVSwitch field Ids taken as difference of DCGM_FI_LAST_NVSWITCH_FIELD_ID and DCGM_FI_FIRST_NVSWITCH_FIELD_ID + 1 i.e. 200

Value

DCGM_FI_LAST_NVSWITCH_FIELD_ID - DCGM_FI_FIRST_NVSWITCH_FIELD_ID + 1

#define DCGM_FI_MAX_VGPU_FIELDS

For now max vGPU field Ids taken as difference of DCGM_FI_LAST_VGPU_FIELD_ID and DCGM_FI_LAST_VGPU_FIELD_ID i.e. 50

Value

DCGM_FI_LAST_VGPU_FIELD_ID - DCGM_FI_FIRST_VGPU_FIELD_ID

#define DCGM_FI_PROF_DRAM_ACTIVE 1005

The ratio of cycles the device memory interface is active sending or receiving data.

#define DCGM_FI_PROF_GR_ENGINE_ACTIVE 1001

Profiling Fields. These all start with DCGM_FI_PROF_* Ratio of time the graphics engine is active. The graphics engine is active if a graphics/compute context is bound and the graphics pipe or compute pipe is busy.

#define DCGM_FI_PROF_NVLINK_RX_BYTES 1012

The number of bytes of active NvLink rx (read) data including both header and payload.

#define DCGM_FI_PROF_NVLINK_TX_BYTES 1011

The number of bytes of active NvLink tx (transmit) data including both header and payload.

#define DCGM_FI_PROF_PCIE_RX_BYTES 1010

The number of bytes of active PCIe rx (read) data including both header and payload.

Note that this is from the perspective of the GPU, so copying data from host to device (HtoD) would be reflected in this metric.

#define DCGM_FI_PROF_PCIE_TX_BYTES 1009

The number of bytes of active PCIe tx (transmit) data including both header and payload.

Note that this is from the perspective of the GPU, so copying data from device to host (DtoH) would be reflected in this metric.

#define DCGM_FI_PROF_PIPE_FP16_ACTIVE 1008

Ratio of cycles the fp16 pipe is active. This does not include HMMA.

#define DCGM_FI_PROF_PIPE_FP32_ACTIVE 1007

Ratio of cycles the fp32 pipe is active.

#define DCGM_FI_PROF_PIPE_FP64_ACTIVE 1006

Ratio of cycles the fp64 pipe is active.

#define DCGM_FI_PROF_PIPE_TENSOR_ACTIVE 1004

The ratio of cycles the tensor (HMMA) pipe is active (off the peak sustained elapsed cycles)

#define DCGM_FI_PROF_SM_ACTIVE 1002

The ratio of cycles an SM has at least 1 warp assigned (computed from the number of cycles and elapsed cycles)

#define DCGM_FI_PROF_SM_OCCUPANCY 1003

The ratio of number of warps resident on an SM. (number of resident as a ratio of the theoretical maximum number of warps per elapsed cycle)

#define DCGM_FI_SYNC_BOOST 91

Deprecated - Sync boost settings on the node

#define DCGM_FI_UNKNOWN 0

NULL field

Functions

dcgm_field_meta_p DcgmFieldGetById ( unsigned short fieldId )
Parameters
fieldId
IN: One of the field IDs (DCGM_FI_?)
Returns

0 On Failure >0 Pointer to field metadata structure if found.

Description

Get a pointer to the metadata for a field by its field ID. See DCGM_FI_? for a list of field IDs.

dcgm_field_meta_p DcgmFieldGetByTag ( char* tag )
Parameters
tag
IN: Tag for the field of interest
Returns

0 On failure or not found >0 Pointer to field metadata structure if found

Description

Get a pointer to the metadata for a field by its field tag.

char* DcgmFieldsGetEntityGroupString ( dcgm_field_entity_group_t entityGroupId )
Returns

  • Pointer to a string like GPU/NvSwitch..etc
  • Null on error

Description

Get the string version of a entityGroupId

int DcgmFieldsInit ( void )
Returns

0 On success <0 On error

Description

Initialize the DcgmFields module. Call this once from inside your program

int DcgmFieldsTerm ( void )
Returns

0 On success <0 On error

Description

Terminates the DcgmFields module. Call this once from inside your program