NVML API Reference Guide (PDF) - vR384 (older) - Last updated October 31, 2017 - Send Feedback

2.1. Device Structs

Classes

struct 
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union 
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Defines

#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 32
#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE 16
#define NVML_MAX_PHYSICAL_BRIDGE (128)
#define NVML_NVLINK_MAX_LINKS 6
#define NVML_VALUE_NOT_AVAILABLE (-1)

Enumerations

enum nvmlBridgeChipType_t
enum nvmlGpuTopologyLevel_t
enum nvmlNvLinkCapability_t
enum nvmlNvLinkErrorCounter_t
enum nvmlNvLinkUtilizationCountPktTypes_t
enum nvmlNvLinkUtilizationCountUnits_t
enum nvmlPcieUtilCounter_t
enum nvmlPerfPolicyType_t
enum nvmlSamplingType_t
enum nvmlValueType_t

Defines

#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 32

Buffer size guaranteed to be large enough for pci bus id

#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE 16

Buffer size guaranteed to be large enough for pci bus id for busIdLegacy

#define NVML_MAX_PHYSICAL_BRIDGE (128)

Maximum limit on Physical Bridges per Board

#define NVML_NVLINK_MAX_LINKS 6

Maximum number of NvLink links supported

#define NVML_VALUE_NOT_AVAILABLE (-1)

Special constant that some fields take when they are not available. Used when only part of the struct is not available.

Each structure explicitly states when to check for this value.

Enumerations

enum nvmlBridgeChipType_t

Enum to represent type of bridge chip

Values
NVML_BRIDGE_CHIP_PLX = 0
NVML_BRIDGE_CHIP_BRO4 = 1
enum nvmlGpuTopologyLevel_t

Represents level relationships within a system between two GPUs The enums are spaced to allow for future relationships

Values
NVML_TOPOLOGY_INTERNAL = 0
NVML_TOPOLOGY_SINGLE = 10
NVML_TOPOLOGY_MULTIPLE = 20
NVML_TOPOLOGY_HOSTBRIDGE = 30
NVML_TOPOLOGY_NODE = 40
NVML_TOPOLOGY_SYSTEM = 50
enum nvmlNvLinkCapability_t

Enum to represent NvLink queryable capabilities

Values
NVML_NVLINK_CAP_P2P_SUPPORTED = 0
NVML_NVLINK_CAP_SYSMEM_ACCESS = 1
NVML_NVLINK_CAP_P2P_ATOMICS = 2
NVML_NVLINK_CAP_SYSMEM_ATOMICS = 3
NVML_NVLINK_CAP_SLI_BRIDGE = 4
NVML_NVLINK_CAP_VALID = 5
NVML_NVLINK_CAP_COUNT
enum nvmlNvLinkErrorCounter_t

Enum to represent NvLink queryable error counters

Values
NVML_NVLINK_ERROR_DL_REPLAY = 0
NVML_NVLINK_ERROR_DL_RECOVERY = 1
NVML_NVLINK_ERROR_DL_CRC_FLIT = 2
NVML_NVLINK_ERROR_DL_CRC_DATA = 3
NVML_NVLINK_ERROR_COUNT
enum nvmlNvLinkUtilizationCountPktTypes_t

Enum to represent the NvLink utilization counter packet types to count ** this is ONLY applicable with the units as packets or bytes ** as specified in nvmlNvLinkUtilizationCountUnits_t ** all packet filter descriptions are target GPU centric ** these can be "OR'd" together

Values
NVML_NVLINK_COUNTER_PKTFILTER_NOP = 0x1
NVML_NVLINK_COUNTER_PKTFILTER_READ = 0x2
NVML_NVLINK_COUNTER_PKTFILTER_WRITE = 0x4
NVML_NVLINK_COUNTER_PKTFILTER_RATOM = 0x8
NVML_NVLINK_COUNTER_PKTFILTER_NRATOM = 0x10
NVML_NVLINK_COUNTER_PKTFILTER_FLUSH = 0x20
NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA = 0x40
NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA = 0x80
NVML_NVLINK_COUNTER_PKTFILTER_ALL = 0xFF
enum nvmlNvLinkUtilizationCountUnits_t

Enum to represent the NvLink utilization counter packet units

Values
NVML_NVLINK_COUNTER_UNIT_CYCLES = 0
NVML_NVLINK_COUNTER_UNIT_PACKETS = 1
NVML_NVLINK_COUNTER_UNIT_BYTES = 2
NVML_NVLINK_COUNTER_UNIT_COUNT
enum nvmlPcieUtilCounter_t

Represents the queryable PCIe utilization counters

Values
NVML_PCIE_UTIL_TX_BYTES = 0
NVML_PCIE_UTIL_RX_BYTES = 1
NVML_PCIE_UTIL_COUNT
enum nvmlPerfPolicyType_t

Represents type of perf policy for which violation times can be queried

Values
NVML_PERF_POLICY_POWER = 0
How long did power violations cause the GPU to be below application clocks.
NVML_PERF_POLICY_THERMAL = 1
How long did thermal violations cause the GPU to be below application clocks.
NVML_PERF_POLICY_SYNC_BOOST = 2
How long did sync boost cause the GPU to be below application clocks.
NVML_PERF_POLICY_BOARD_LIMIT = 3
How long did the board limit cause the GPU to be below application clocks.
NVML_PERF_POLICY_LOW_UTILIZATION = 4
How long did low utilization cause the GPU to be below application clocks.
NVML_PERF_POLICY_RELIABILITY = 5
How long did the board reliability limit cause the GPU to be below application clocks.
NVML_PERF_POLICY_TOTAL_APP_CLOCKS = 10
Total time the GPU was held below application clocks by any limiter (0 - 5 above).
NVML_PERF_POLICY_TOTAL_BASE_CLOCKS = 11
Total time the GPU was held below base clocks.
NVML_PERF_POLICY_COUNT
enum nvmlSamplingType_t

Represents Type of Sampling Event

Values
NVML_TOTAL_POWER_SAMPLES = 0
To represent total power drawn by GPU.
NVML_GPU_UTILIZATION_SAMPLES = 1
To represent percent of time during which one or more kernels was executing on the GPU.
NVML_MEMORY_UTILIZATION_SAMPLES = 2
To represent percent of time during which global (device) memory was being read or written.
NVML_ENC_UTILIZATION_SAMPLES = 3
To represent percent of time during which NVENC remains busy.
NVML_DEC_UTILIZATION_SAMPLES = 4
To represent percent of time during which NVDEC remains busy.
NVML_PROCESSOR_CLK_SAMPLES = 5
To represent processor clock samples.
NVML_MEMORY_CLK_SAMPLES = 6
To represent memory clock samples.
NVML_SAMPLINGTYPE_COUNT
enum nvmlValueType_t

Represents the type for sample value returned

Values
NVML_VALUE_TYPE_DOUBLE = 0
NVML_VALUE_TYPE_UNSIGNED_INT = 1
NVML_VALUE_TYPE_UNSIGNED_LONG = 2
NVML_VALUE_TYPE_UNSIGNED_LONG_LONG = 3
NVML_VALUE_TYPE_SIGNED_LONG_LONG = 4
NVML_VALUE_TYPE_COUNT

NVML API Reference Guide (PDF) - vR384 (older) - Last updated October 31, 2017 - Send Feedback