Examples

Aerial CUDA-Accelerated RAN 24-1 (Archive)

https://gitlab-master.nvidia.com/gputelecom/cumac/-/tree/develop/testVectors?ref_type=heads

Each test vector contains parameters and data arrays defined in the cuMAC API structures: cumacCellGrpUeStatus, cumacCellGrpPrms, and cumacSchdSol.

Parameter configurations can be specified using this file: parameters.h

Use the testbench multiCellSchedulerUeSelection to create TVs:

  • DL TV:

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    ./build/examples/multiCellSchedulerUeSelection/multiCellSchedulerUeSelection -t 1

  • UL TV:

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    ./build/examples/multiCellSchedulerUeSelection/multiCellSchedulerUeSelection -d 0 -t 1

An H5 TV is created after the last simulated TTI. The assumption is that the simulation duration is long enough so that the scheduler algorithm’s performance converges.

Given the same input parameters of a single TTI, GPU and CPU implementations of the same scheduler algorithms should give the same output solution.

Two types of tests:

  • Per scheduler module tests: DL/UL UE selection, DL/UL PRG allocation, DL/UL layer selection, and DL/UL MCS selection

  • Complete DL/UL scheduler pipeline tests

TV loading-based single-TTI testbench: tvLoadingTest

After building cumac, use the following commend to check input arguments of the testbench: ./build/examples/tvLoadingTest/tvLoadingTest -h

  • Per scheduler module tests:

    • DL UE selection:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 1 -m 01000

    • DL PRG allocation:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 1 -m 00100

    • DL layer selection:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 1 -m 00010

    • DL MCS selection:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 1 -m 00001

    • UL scheduler modules can be tested by setting input argument: -d 0

  • Complete DL/UL scheduler pipeline tests

    • DL/UL scheduler modules executed sequentially: UE selection > PRG allocation > layer selection > MCS selection

    • DL scheduler pipeline:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 1 -m 01111

    • UL scheduler pipeline:

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      ./build/examples/tvLoadingTest/tvLoadingTest -i [path to TV] -g 2 -d 0 -m 01111

Passing criteria:

Solutions computed by CPU and GPU should match exactly: testbench returns 1 (PASS) or 0 (FAIL)

With the same initial sate, GPU and CPU implementations of the same scheduler algorithms should achieve similar performance curves when running for a period of time.

  • Complete DL/UL scheduler pipeline tests

    • Continuous-time testbench: multiCellSchedulerUeSelection

    • After building cumac, use the following commend to check input arguments of the testbench:

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      ./build/examples/multiCellSchedulerUeSelection/multiCellSchedulerUeSelection -h

    • No need to use pre-generated H5 TVs. All parameters are computed using cuMAC internal simulator.

    • Simulator configuration can be specified using file: parameters.h

    • DL/UL scheduler modules executed sequentially: UE selection > PRG allocation > layer selection > MCS selection

    • DL scheduler pipeline test:

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      ./build/examples/multiCellSchedulerUeSelection/multiCellSchedulerUeSelection

    • UL scheduler pipeline test:

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      ./build/examples/multiCellSchedulerUeSelection/multiCellSchedulerUeSelection -d 0

Passing criteria:

Performance curves achieved by GPU and CPU scheduler implementations should match: testbench returns 1 (PASS) or 0 (FAIL)

Two types of performance curves:

  • Sum throughput of all cells

  • CDF of per-UE throughput

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