IGX Thor Adaptation and Bring-Up

Applies to NVIDIA IGX Thor Developer Kit Mini and IGX Thor T5000 module.

Overview

This guide provides information for bringing up custom platforms based on the NVIDIA IGX Thor T5000 module.

For general guidelines on adapting and bringing up a custom carrier board using the NVIDIA Thor module, refer to the Jetson Thor Adaptation and Bring-Up guide in the Jetson Linux Developer Guide. Topics covered include:

• Board naming

• Root filesystem configuration

• MB1/MB2 BCT settings

• GPIO/pinmux configuration

• Flashing procedures

The sections below cover IGX T5000 specific configurations.

Configure the UPHY Lane

The IGX Thor T5000 module provides two UPHY blocks, UPHY0 and UPHY1, each supporting multiple lane mapping configurations. Set the desired configuration in the BPMP device tree using the uphy0-config and uphy1-config properties.

UPHY0 Lane Mapping

Config	Lane 0	Lane 1	Lane 2	Lane 3	Lane 4	Lane 5	Lane 6	Lane 7
6	USB3 x1 P0	USB3 x1 P1	USB3 x1 P2	PCIe C1 x1 (RP)	PCIe C2 x2 (DM)		PCIe C3 x2 (RP)
7 (default)	USB3 x1 P0	USB3 x1 P1	USB3 x1 P2	PCIe C1 x1 (RP)	PCIe C2 x2 (DM)		UFS x2

UPHY1 Lane Mapping

Config	Lane 0	Lane 1	Lane 2	Lane 3	Lane 4	Lane 5	Lane 6	Lane 7
0	PCIe C4 x8 (DM)
7 (default)	PCIe C5 x4 (DM)				MGBE0 10G	MGBE1 10G	MGBE2 10G	MGBE3 10G

UPHY Config on IGX Thor Developer Kit Mini

On the IGX Thor Developer Kit Mini, the default configuration uses UPHY0 Config 7 and UPHY1 Config 7, which provides the following lane assignments:

• UFS on UPHY0 L6–L7

• NVMe on UPHY1 L0–L3 (PCIe C5 x4)

• MGBE on UPHY1 L4–L7

Enable PCIe C4 x8 Mode

To use a PCIe port in x8 mode:

• Set UPHY1 to Config 0: UPHY1 L0–L7 are used for the PCIe C4 x8.

• MGBE and NVMe are not available on UPHY1 in this configuration.

• Note: UPHY0 can be used in Config 7 for UFS and Config 6 for NVMe on PCIe C3.

Use the following steps to update the BPMP DTB to enable PCIe C4 in x8 mode:

1. Convert the BPMP DTB to DTS:

   cd Linux_for_Tegra/bootloader/generic
   cp tegra264-bpmp-3834-0008-4071-xxxx.dtb tegra264-bpmp-3834-0008-4071-xxxx-orig.dtb
   dtc -I dtb -O dts tegra264-bpmp-3834-0008-4071-xxxx-orig.dtb > tegra264-bpmp-3834-0008-4071-xxxx.dts
   

2. Edit tegra264-bpmp-3834-0008-4071-xxxx.dts to make the following changes:

   // Set uphy1-config to 0
   uphy {
       status = "okay";
       uphy1-config = <0x00>;
       ...
   
   // Disable PCIe C5
   pcie@5 {
       status = "disabled";
       ...
   
   // Enable PCIe C4
   pcie@4 {
       status = "okay";
       ...
   

3. Convert the updated DTS back to DTB:

   dtc -I dts -O dtb tegra264-bpmp-3834-0008-4071-xxxx.dts > tegra264-bpmp-3834-0008-4071-xxxx.dtb
   

Enable the C4 controller in RP mode in your kernel DT. The example board configuration file Linux_for_Tegra/p3834-0008-p3971-0000.conf has PCIe C4 x8 enabled in RP mode by default. It can be used as a reference for kernel DT, pinmux, and clk/rst changes.

Note

PCIe C4 x8 mode is not compatible with the Safety Extension Package (SEP), because both UFS and NVMe storage are required when running SEP.