Topics
Topics
AR / VR
Cybersecurity
Edge Computing
Recommenders / Personalization
Computer Vision / Video Analytics
Data Center / Cloud
Generative AI / LLMs
Robotics
Content Creation / Rendering
Data Science
Networking
Simulation / Modeling / Design
Conversational AI
NVIDIA Developer
Blog
Forums
Sign In
Menu
Docs Hub
Topics
Topics
AR / VR
Cybersecurity
Edge Computing
Recommenders / Personalization
Computer Vision / Video Analytics
Data Center / Cloud
Generative AI / LLMs
Robotics
Content Creation / Rendering
Data Science
Networking
Simulation / Modeling / Design
Conversational AI
NVIDIA Developer
Blog
Forums
Sign In
Holoscan Sensor Bridge v2.5.0
Submit Search
Submit Search
NVIDIA Docs Hub Homepage
NVIDIA Holoscan
Holoscan Sensor Bridge v2.5.0
Holoscan Sensor Bridge FPGA IP
Holoscan Sensor Bridge FPGA IP
Contents
Overview
Holoscan Sensor Bridge IP Architecture
Resource Utilization
Port Description
Global Reset
User Register Ports
Sensor Interface Ports
Host Interface Ports
Peripheral Interface Ports
Clocking and Reset
Clocking
Resets
Dataplane
Sensor RX (Sensor to FPGA)
Sensor TX (Host to FPGA to Sensor)
Host TX (FPGA to Host)
Host RX (Host to FPGA)
Peripheral Interface
SPI
I2C
GPIO
Register Interface
User Registers
Precision Time Protocol (PTP)
PTP Use Case
PTP Profile
PTP Timer
PTP Configuration
PTP Performance
IP Integration
Top Level Module
User Configurability
System Initialization
Simulation
Hardware Debug
Data Generator
Packet Sequence Number (PSN) Registers
Peripheral Debug
Known IP Limitations
Previous
HSB Emulator
Next
Overview
© Copyright 2022-2024, NVIDIA.
Last updated on Dec 10, 2025
Close
content here
