IP Integration

The top level module of the Holoscan Sensor Bridge IP is “HOLOLINK_top”.

The Holoscan Sensor Bridge IP is designed to be easily configurable to various use case of the IP, such as number of sensors and Ethernet ports. It’s also designed to be compatible with multiple FPGA vendors. The following describes the configurations available to user.

Macro Definitions

The Holoscan Sensor Bridge definitions file, “HOLOLINK_def.svh”, defines the following macros.

The macros can be configured to user’s application of the Holoscan Sensor Bridge IP. The default macro value is the configuration that has been tested and verified.

Table 13

Build Revision

Parameter BUILD_REV[47:0] can be passed down to the “HOLOLINK_top” module to uniquely identify the FPGA build revision.

BOOTP Packet

The HSB IP transmits a broadcast BOOTP Request packet approximately once per second. BOOTP packets are used to enumerate the Holoscan Sensor Bridge to host and to change the IP address from default in case of multiple board enumeration. Holoscan Sensor Bridge IP BOOTP packets adhere to RFC-951. The Vendor Field of the BOOTP packet is used to communicate enumeration info and status of Holoscan Sensor Board to the host.

Holoscan Sensor Bridge IP BOOTP Vendor field is laid out in below table:

BOOTP enumeration info can be stored in non-volatile memory or from macros defined in the “HOLOLINK_def.svh”.

Mass production of boards with HOLOLINK IP requires an external EEPROM to store unique MAC address and board serial numbers. When Using evaluation platforms for test and bring-up, using the macro for fixed values are acceptable.

Each of the macros used for enumeration packet is further explained below.

UUID: This macro defines the unique identifier for the board. Holoscan uses this value to identify which board it is interfacing and fetch the correct bitfile for remote flash. For newly developed boards, users can generate and assign a new UUID. This macro must be defined and is not optionally stored in the non-volatile memory.

ENUM_EEPROM: When this macro is defined, the contents of the below macros are retrieved from an on-board, non-volatile memory upon boot-up. The contents of the below macros must be stored in specific address of the non-volatile memory. Further details can be provided upon request.

Macros listed below are used only if ENUM_EEPROM macro is undefined.

MAC_ADDR: This macro defines the UDP MAC Address of the FPGA. The MAC Address is incremented by 1 for each Host interface available. For example, if the MAC_ADDR macro is defined as 48’hCAFEC0FFEE00, Host Interface 0 will have address 48’hCAFEC0FFEE00 and Host Interface 1 will have address 48’hCAFEC0FFEE01, and so on.

BOARD_VER: This macro defines the Board Version.

BOARD_SN: This macro defines the Board Serial Number.

FPGA_CRC: This macro defines the CRC of the FPGA bit image and is used only if ENUM_EEPROM macro is undefined. The intended function is for software to check the validity of the FPGA bit image by checking it against what the software calculates. This function is not yet supported.

MISC: This macro defines miscellaneous information.

The Holoscan Sensor Bridge IP provides system initialization function to write to registers upon power up. This function is used to initialize the Ethernet block to establish ethernet connection between the FPGA and the host, and can be used for any other user function in the top level design.

The list of registers to be initialized is defined in “Hololink_def.svh” as “init_reg” array. The “init_reg” is an unpacked array, sized [N_INIT_REG] [63:0], where the N_INIT_REG macro defines the number of registers to be initialized and the 64-bit vector is used to define the 32- bit address of register at [63:32] and the 32-bit write data at [31:0].

To give an example of one of the init_reg array entry:

{32’h1000_0020, 32’h0000_00FF} //init_reg[0]

Will write to the User REG_INST_0 block address offset 0x0000_0020 the data 0x0000_00FF.

Once system initialization is complete, the “o_init_done” port will be asserted high in “i_apb_clk” domain. User can use this signal to gate their logic if it’s dependent on ethernet block initialization.