Multicell Capacity#
The tested L2 timeline is as follows:
FAPI SLOT.indication for Slot N is sent from L1 to L2 at the wall-clock time for Slot N-3 (i.e. 3 slot advance).
Supports 500us L2 processing budget and 7 beam peak and average patterns as defined below using 100MHz:
On Grace Hopper:
BFP9: 20 4T4R Peak cells / 20 4T4R average cells
while respecting the following configuration for 7 beam traffic patterns:
4T4R 7-beam config |
Configuration |
|
|---|---|---|
Peak |
Average |
|
Compression |
BFP9 and BFP14 |
BFP9 and BFP14 |
Max PxSCH PRB |
270 |
132 |
PxSCH layer count |
4DL/2UL |
4DL/2UL |
DL Throughput/cell |
1544.14 Mbps |
558.90 Mbps |
UL Throughput/cell |
196.70 Mbps |
79.91 Mbps |
Peak DL Fronthaul Bandwidth / cell |
11.06 Gbps BFP14 |
5.46 Gbps BFP14 |
7.14 Gbps BFP9 |
3.58 Gbps BFP9 |
|
Peak UL Fronthaul Bandwidth / cell |
11.88 Gbps BFP14 |
6.34 Gbps BFP14 |
8.03 Gbps BFP9 |
4.57 Gbps BFP9 |
|
SSB slots |
Frame 0 & 2: 0,1,2,3 |
Frame 0 & 2: 0,1,2,3 |
#SSB per slot |
Frame 0 & 2: 2,2,2,1 |
Frame 0 & 2: 2,2,2,1 |
TRS slots |
Frame 0-3: 6,7,8,9,10,11 |
Frame 0-3: 6,7,8,9,10,11 |
Frame 0 & 2: 16,17 |
Frame 0 & 2: 16,17 |
|
TRS Symbols |
Even cells: 6,10 |
Even cells: 6,10 |
Odd cells: 5,9 |
Odd cells: 5,9 |
|
CSI-RS slots |
Frame 0: 8,10,16 |
Frame 0: 8,10,16 |
Frame 1: 6,8,10 |
Frame 1: 6,8,10 |
|
Frame 2: 6 |
Frame 2: 6 |
|
CSI-RS Symbols |
Even cells: 12 |
Even cells: 12 |
Odd cells: 13 |
Odd cells: 13 |
|
PDCCH #DCI |
12 (6 DL + 6 UL per slot) |
12 (6 DL + 6 UL per slot) |
UE/TTI/Cell |
6 per DL slot, 6 per UL slot |
6 per DL slot, 6 per UL slot |
UCI on PUSCH HARQ+CSIP1+CSIP2 (bits) |
4+37+5 |
4+37+5 |
PUCCH format |
1 |
1 |
PUCCH payload (bits) |
18 |
18 |
PRACH format |
B4 |
B4 |
PRACH slots |
Frame 0-3: 5, 15 |
Frame 0-3: 5, 15 |
PRACH occasions |
Slot 5: 4, Slot 15: 3 |
Slot 5: 4, Slot 15: 3 |
On Grace Hopper:
BFP9: 1 64T64R Peak cell / 3 64T64R average cell
while respecting the following traffic patterns:
64T64R config |
Configuration |
|
|---|---|---|
Peak |
Average |
|
Compression |
BFP9 and BFP14 |
BFP9 and BFP14 |
Max PxSCH PRB |
273 |
136 |
PxSCH layer count |
8DL/2UL |
8DL/2UL |
DL Throughput/cell |
2464.93 Mbps |
1227.29 Mbps |
UL Throughput/cell |
224.50 Mbps |
107.37 Mbps |
SSB slots |
Frame 0 & 2: 0 |
Frame 0 & 2: 0 |
#SSB per slot |
Frame 0 & 2: 1 |
Frame 0 & 2: 1 |
TRS slots |
Frame 1 & 3: 0,1 |
Frame 1 & 3: 0,1 |
TRS Symbols |
Even cells: 5,9 |
Even cells: 5,9 |
Odd cells: 6,8 |
Odd cells: 6,8 |
|
CSI-RS slots |
Frame 1 & 3: 0,1 |
Frame 1 & 3: 0,1 |
CSI-RS Symbols |
Even cells: 13 |
Even cells: 13 |
Odd cells: 12 |
Odd cells: 12 |
|
PDCCH #DCI |
14 (8 DL + 6 UL per slot) |
14 (8 DL + 6 UL per slot) |
UE/TTI/Cell |
8 per DL slot, 6 per UL slot |
8 per DL slot, 6 per UL slot |
UCI on PUSCH HARQ+CSIP1+CSIP2 (bits) |
4+6+5 |
4+6+5 |
PUCCH format |
1 |
1 |
PUCCH payload (bits) |
Frame 0 & 2, slots 4, 5: 36 (HARQ) |
Frame 0 & 2, slots 4, 5: 36 (HARQ) |
Frame 1 & 3, slots 4, 5: 108 (SR) |
Frame 1 & 3, slots 4, 5: 108 (SR) |
|
PRACH format |
B4 |
B4 |
PRACH slots |
Frame 0-3: 5, 15 |
Frame 0-3: 5, 15 |
PRACH occasions |
Slot 5, 15: 1 |
Slot 5, 15: 1 |
CPU core usage for multicell benchmark (core isolation needed on all cores):
On Grace Hopper:
MIMO antenna configuration |
4T4R |
64T64R |
|---|---|---|
L1 CPU core count* |
10 |
13 |
Above core count does not include allocation for PTP applications (phc2sys+ptp4l)
Note
Stated performance achievement and CPU core count usage is for L1 workload only (additional non-L1 workloads in E2E setting may have an impact on the achieved performance and/or CPU core count usage)
Note
Performance achievement is measured by running L1 in steady-state traffic mode (e.g. impact of workloads such as cell reconfiguration on other cells is not captured)