bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl

VRNVL72 performance recipes for Qwen3.5-VL.

Module Contents

Functions

qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_bf16_config	Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, BF16 (alias of GB300).
qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_fp8cs_config	Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, FP8-CS (alias of GB300).
qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_fp8mx_config	Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, MXFP8, EP=4, HybridEP.
qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_bf16_config	Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, BF16 (alias of GB300).
qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_fp8cs_config	Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, FP8-CS (alias of GB300).
qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_fp8mx_config	Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, FP8-MX (alias of GB300).
qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_bf16_config	Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, BF16 (alias of GB300).
qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_fp8cs_config	Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, FP8-CS (alias of GB300).
qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_fp8mx_config	Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, MXFP8, EP=32, HybridEP.

API

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_bf16_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, BF16 (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_fp8cs_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, FP8-CS (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_35b_a3b_pretrain_8gpu_vrnvl72_fp8mx_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 35B-A3B pretrain: 8× VRNVL72, MXFP8, EP=4, HybridEP.

Starts from the GB300 MXFP8 recipe (CuTe DSL fused grouped MLP, cuDNN GDN, per-layer CUDA graphs, forced load balancing) and applies EP 4, MBS 4 and the kernel settings of the measured VRNVL72 runs, at GBS 1024.

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_bf16_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, BF16 (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_fp8cs_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, FP8-CS (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_122b_a10b_pretrain_32gpu_vrnvl72_fp8mx_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 122B-A10B pretrain: 32× VRNVL72, FP8-MX (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_bf16_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, BF16 (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_fp8cs_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, FP8-CS (alias of GB300).

bridge.perf_recipes.qwen_vl.vrnvl72.qwen35_vl.qwen35_vl_397b_a17b_pretrain_64gpu_vrnvl72_fp8mx_config() → megatron.bridge.perf_recipes.qwen_vl.common.ConfigContainer

Qwen3.5-VL 397B-A17B pretrain: 64× VRNVL72, MXFP8, EP=32, HybridEP.

Starts from the GB300 MXFP8 recipe (cuDNN GDN, per-layer CUDA graphs, forced load balancing) and adds the CuTe DSL fused grouped MLP and the settings of the measured VRNVL72 run.